LT1103/LT1105

Offline Switching Regulator

THE LT1103 IS OBSOLETE: THE LT1105 IS AVAILABLE, BUT NOT
FOR INFORMATION PURPOSES ONLY
Contact Analog Devices for Potential Replacement RECOMMENDED FOR NEW DESIGNS

FEATURES DESCRIPTION
n ±1% Line and Load Regulation with No Optocoupler The LT®1105 Offline Switching Regulator is designed
n Switch Frequency Up to 200kHz for high input voltage applications using an external FET
n Internal 2A Switch and Current Sense (LT1103) switch. The LT1105 is available and its totem pole out-
n Internal 1A Totem-Pole Driver (LT1105) put drives the gate of an external FET. Unique design of
n Start-Up Mode Draws Only 200µA the LT1105 eliminates the need for an optocoupler while
n Fully Protected Against Overloads still providing ±1% load and line regulation in a magnetic
n Overvoltage Lockout of Main Supply flux-sensed converter. This significantly simplifies the
n Protected Against Underdrive or Overdrive to FET design of offline power supplies and reduces the number
n Operates in Continuous or Discontinuous Mode of components which must cross the isolation barrier to
n Ideal for Flyback and Forward Topologies one, the transformer.
n Isolated Flyback Mode Has Fully Floating Outputs The LT1105 current mode switching techniques are well
suited to transformer isolated flyback and forward topolo-
APPLICATIONS gies while providing ease of frequency compensation with
n Up to 250W Isolated Mains Converter a minimum of external components.
n Up to 50W Isolated Telecom Converter All registered trademarks and trademarks are the property of their respective owners.

n Fully Isolated Multiple Outputs

n Distributed Power Conversion Networks

TYPICAL APPLICATION
Fully Isolated Flyback 100kHz 50W Converter with Load Regulation Compensation
OPTIONAL OUTPUT FILTER
85VAC TO 270VAC MBR2045 10µH
5V
1.5KE300A 10A
!!
GER
+ 5W +
! +
DAN LTAGE!
220k 50V
+ 1W *50V 470µF
MUR150
220µF
V O 3600µF
385V
499Ω HIGH
– *OUTPUT CAPACITOR IS THREE 1200µF,
1N4148 50V CAPACITORS IN PARALLEL TO
1000pF 100Ω ACHIEVE REQUIRED RIPPLE CURRENT
RATING AND LOW ESR.
BRIDGE
RECTIFIER
Load Regulation
+ BAV21 WINDINGS FOR 5.25
LINE BUK426-800A OPTIONAL
BAV21 1N4148 VSW 5.20
FILTER VIN ±12VDC OUTPUTS

39µF
+ LT1103
5.15
13k
35V 10Ω 5.10
1%
18.7k TRANSFORMER DATA:
5.05 220VAC
COILTRONICS CTX110228-3
VOUT (V)

FB 15V
GND VC OSC + 1µF
L(PRI) = 1.6mH 5.00
NPRI:NSEC = 1:0.05
4.75k 25V NBIAS:NSEC = 1:0.27 4.95
1% 110VAC 85VAC
0.047µF 390pF 4.90 270VAC
330Ω
4.85
0.047µF 0.1µF 4.80

LT1103 TA13 4.75

0 1 2 3 4 5 6 7 8 9 10
IOUT (A)
Danger!! Lethal Voltages Present – See Text LT1103 TA02

Rev. F

Document Feedback For more information LT1103/LT1105 1

LT1103/LT1105
DESCRIPTION WARNING
200kHz maximum switching frequency to achieve high
power density. Performance at switching frequencies DANGEROUS AND LETHAL POTENTIALS ARE
above 100kHz may be degraded due to internal timing PRESENT IN OFFLINE CIRCUITS!
constraints associated with fully isolated flyback mode. BEFORE PROCEEDING ANY FURTHER, THE
Included are the oscillator, control, and protection cir-
READER IS WARNED THAT CAUTION MUST
cuitry such as current limit and overvoltage lockout.
BE USED IN THE CONSTRUCTION, TESTING
AND USE OF OFFLINE CIRCUITS. HIGH
Switch frequency and maximum duty cycle are adjustable.
VOLTAGE, AC LINE-CONNECTED POTENTIALS
Bootstrap circuitry draws 200µA for start-up of isolated
ARE PRESENT IN THESE CIRCUITS. EXTREME
topologies. A 5V reference as well as a 15V gate bias
CAUTION MUST BE USED IN WORKING WITH
are available to power external primary-side circuitry. No
AND MAKING CONNECTIONS TO THESE
external current sense resistor is necessary with LT1103 CIRCUITS. REPEAT: OFFLINE CIRCUITS
because it is integrated with the high current switch. The CONTAIN DANGEROUS, AC LINE-CONNECTED
LT1105 brings out the input to the current limit amplifier HIGH VOLTAGE POTENTIALS. USE CAUTION.
and requires the use of an external sense resistor.
ALL TESTING PERFORMED ON AN OFFLINE
The LT1103/LT1105 have unique features not found on CIRCUIT MUST BE DONE WITH AN ISOLATION
other offline switching regulators. Adaptive antisat switch TRANSFORMER CONNECTED BETWEEN THE
drive allows wide ranging load currents while maintain- OFFLINE CIRCUIT’S INPUT AND THE AC LINE.
ing high efficiency. The external FET is protected from USERS AND CONSTRUCTORS OF OFFLINE
insufficient or excessive gate drive voltage with a drive CIRCUITS MUST OBSERVE THIS PRECAUTION
detection circuit. An externally activated shutdown mode WHEN CONNECTING TEST EQUIPMENT TO
reduces total supply current to less than 200µA, typical THE CIRCUIT TO AVOID ELECTRIC SHOCK.
for standby operation. Fully isolated and regulated outputs REPEAT: AN ISOLATION TRANSFORMER MUST
can be generated in the optional isolated flyback mode BE CONNECTED BETWEEN THE CIRCUIT INPUT
without the need for optocouplers or other isolated feed- AND THE AC LINE IF ANY TEST EQUIPMENT IS
back paths. TO BE CONNECTED.

ABSOLUTE MAXIMUM RATINGS (Note 1)

VIN.............................................................................30V Maximum Operating Ambient Temperature Range

VSW Output Voltage (LT1103)....................................50V LT1103C (OBSOLETE)............................... 0°C to 70°C
VSW Output Current (200ns)(LT1105)..................... ±1.5A LT1105C.................................................... 0°C to 70°C
VC, FB, OSC, SS...........................................................6V Maximum Operating Temperature Range
ILIM (LT1105)................................................................3V LT1103C (OBSOLETE)............................. 0°C to 100°C
OVLO Input Current...................................................1mA LT1105C.................................................. 0°C to 100°C
Lead Temperature (Soldering, 10 sec.)................... 300°C LT1105I............................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C

Rev. F

2 For more information LT1103/LT1105

 LT1103/LT1105
PIN CONFIGURATION
LT1105 LT1105 LT1103
TOP VIEW
FRONT VIEW
PWRGND 1 14 VSW
TOP VIEW 7 15V
OVLO 2 13 NC 6 VIN
GND 1 8 VSW 5 OSC
FB 3 12 NC
4 GND
ILIM 2 7 15V 3 VC
VC 4 11 15V
3 2 FB
5V 5 10 VIN FB 6 VIN
1 VSW
SS 6 9 OSC VC 4 5 OSC
T7 PACKAGE
GND 7 8 ILIM 7-LEAD TO-220
N8 PACKAGE
8-LEAD PDIP CASE IS CONNECTED TO GROUND. LEADS ARE FORMED
N PACKAGE TJMAX = 100°C, θJA = 50°C/W
TJMAX = 100°C, θJA = 130°C/W
14-LEAD PDIP
PINS 1 AND 7 MUST BE TIED TOGETHER OBSOLETE PACKAGE
TJMAX = 100°C, θJA = 100°C/W

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT1105CN#PBF N/A LT1105CN 14-Lead PDIP 0°C to 100°C
LT1105IN#PBF N/A LT1105IN 14-Lead PDIP –40°C to 125°C
LT1105CN8#PBF N/A LT1105CN8 8-Lead PDIP 0°C to 100°C
LT1105IN8#PBF N/A LT1105IN8 8-Lead PDIP –40°C to 125°C
OBSOLETE PACKAGE
LT1103CT7#PBF LT1103CT7#TRPBF LT1103CT7 7-Lead TO-220 0°C to 100°C
Contact the factory for parts specified with wider operating temperature ranges.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
For more information on lead free part marking, go to: http://www.adi.com/leadfree/
For more information on tape and reel specifications, go to: http://www.adi.com/tapeandreel/

ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VC = 0.85V, OVLO = 0V, VSW Open, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IQ Supply Current 8V < VIN < 30V, After Device Has Started l 10 20 30 mA
ISTART Start-Up Current VIN < VIN Start Threshold l 200 400 µA
Industrial Grade l 450 µA
VIN Start Threshold l 14.5 16.0 17.5 V
VIN Shutdown Threshold Note: Switching Stops When VSW < 10V (LT1103) l 5.0 7.0 8.0 V
Note: Switching Stops When VGATE < 10V (LT1105)
VREF 5V Reference Voltage l 4.80 4.95 5.20 V
VREF Line Regulation 10V < VIN < 30V l 0.025 0.1 %V
VREF Load Regulation 0mA < IL < 20mA l 0.025 0.05 %mA
VREF Short-Circuit Current Commercial Grade l 25 60 110 mA
Industrial Grade l 20 120 mA
15V Short-Circuit Current Commercial Grade l 30 130 mA
Industrial Grade l 25 140 mA

Rev. F

For more information LT1103/LT1105 3

LT1103/LT1105
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VC = 0.85V, OVLO = 0V, VSW Open, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VGATE 15V Gate Bias Reference 17 < VIN < 30V, 0mA < IL < 30mA l 13.8 15.0 16.2 V
15V Dropout Voltage VIN = 15V, IL = 30mA l 2.0 2.5 V
15V Short-Circuit Current l 30 70 130 mA
SF Oscillator Scaling Factor FB = 4V, VC = Open, Measured at VSW, ISW = 25mA, 36 40 44 Hz • µF
OVLO = 5V, fOSC = SF/COSC, 40kHz < fOSC < 200kHz l 32 40 48 Hz • µF
Oscillator Valley Voltage 2.0 V
Oscillator Peak Voltage 4.5 V
DC Preset Max Switch Duty Cycle FB = 4V, VC = Open, fOSC = 40kHz, ISW = 25mA, l 58 65 72 %
(LT1103) Note: Maximum Duty Cycle Can Be Altered at OSC Pin
Preset Max Switch Duty Cycle FB = 4V, VC = Open, fOSC = 40kHz, ISW = 25mA, l 56 63 70 %
(LT1105) Note: Maximum Duty Cycle Can Be Altered at OSC Pin
Industrial Grade l 55 75 %
OVLO Threshold Overvoltage Lockout Threshold at Which Switching is Inhibited l 2.3 2.5 2.7 V
Industrial Grade l 2.2 2.8 V
OVLO Input Bias Current OVLO = 2V, Measured Out of Pin (Note 2) l 1.0 3.0 µA
VFB FB Threshold Voltage I(VC) = 0mA 4.425 4.50 4.575 V
l 4.400 4.50 4.600 V
FB Input Bias Current FB = VFB (Note 3) l 5 10 20 µA
Industrial Grade l 4 22 µA
Change in FB Input FB = VFB, VC = 1V to 4V (Note 3) 8 11 13 µA/V
Bias Current with Change in VC l 7 11 14 µA/V
Industrial Grade l 6 15 µA/V
FB Threshold Line Regulation 10V < VIN < 30V l 0.025 0.10 %/V
gm Error Amp Transconductance ∆I(VC) = ±50µA 9000 12000 17500 µmho
l 6000 12000 20000 µmho
l 5000 24000 µmho
AV Error Amp Voltage Gain 1V < VC < 3V l 500 1250 V/V
Industrial Grade l 450 V/V
VC Switching Threshold Switch Duty Cycle = 0% l 0.85 1.25 1.4 mA
Shutdown Threshold Voltage l 50 150 250 mV
Industrial Grade l 50 300 mV
Error Amp Source Current l 150 275 µA
Error Amp Sink Current l 1.5 3 4.5 mA
Industrial Grade l 0.7 4.5 mA
Error Amp Clamp Voltage FB = 4.75V l 0.3 0.7 0.9 V
FB = 4.0V l 4.2 4.4 4.6 V
Soft-Start Charging Current SS = 0V l 25 40 60 µA
Industrial Grade l 20 75 µA
Soft-Start Reset Current VIN = 6V, SS = 0.3V l 1 2 mA
Output Switch Leakage VSW = 45V l 500 µA
(LT1103) VSW = 15V l 200 µA
BV Switch Breakdown Voltage ISW = 5mA l 50 70 V
(LT1103)
VSW Current Limit (LT1103) Duty Cycle = 25% (Note 4) l 2.0 2.5 3.0 A
Output Switch On Resistance l 0.4 0.75 Ω
(LT1103)

Rev. F

4 For more information LT1103/LT1105

 LT1103/LT1105
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 20V, VC = 0.85V, OVLO = 0V, VSW Open, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
∆IIN IQ Increase During Switch On Time ISW = 0.5A to 1.5A l 30 50 mA/A
∆ISW (LT1103)
Switch Output High Level ISW = 200mA, VGATE = 15V l 13.00 13.5 V
(LT1105) ISW = 750mA, VGATE = 15V l 12.50 13.2 V
Switch Output High Level ISW = 200mA, VGATE = 15V l 12.75 V
Industrial Grade ISW = 750mA, VGATE = 15V l 12.25 V
Switch Output Low Level ISW = 200mA l 0.25 0.50 V
(LT1105) ISW = 750mA l 0.75 1.50 V
Rise Time (LT1105) CL = 1000pF 50 ns
Fall Time (LT1105) CL = 1000pF 20 ns
ILIM Threshold Voltage (LT1105) Duty Cycle = 25% (Note 5) l 300 375 450 mV
Low Switch Drive Lockout Measured at VSW (LT1103) l 9.0 9.5 10.5 V
Threshold Measured at 15V Gate Bias Reference (LT1105)
High Switch Drive Lockout Measured at VSW (LT1103) l 17.0 18.5 20.0 V
Threshold Measured at 15V Gate Bias Reference (LT1105)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 4: Current limit on VSW is constant for DC < 35% and decreases for
may cause permanent damage to the device. Exposure to any Absolute DC > 35% due to internal slope compensation circuity. The LT1103 switch
Maximum Rating condition for extended periods may affect device current limit is given by ILIM = 1.76 (1.536 – DC) above 35% duty cycle.
reliability and lifetime. Note 5: The current limit threshold voltage is constant for DC < 35% and
Note 2: The OVLO pin is clamped with a 5.5V Zener and can sink a decreases for DC > 35% due to internal slope compensation circuitry. The
maximum input current of 1mA. LT1105 switch current limit threshold voltage is given by VLIM = 0.225
Note 3: FB input bias current changes as a function of the VC pin voltage. (1.7 – DC) above 35% duty cycle.
Rate of change of FB input bias current is 11µA/V of change on VC. By
including a resistor in series with the FB pin, load regulation can be set to
zero.

TYPICAL PERFORMANCE CHARACTERISTICS

Start-Up Supply Current vs Quiescent Supply Current vs
Supply Current vs Input Voltage Input Voltage Input Voltage
25 500 22
450 21
QUIESCENT SUPPLY CURRENT (mA)
START-UP SUPPLY CURRENT (µA)

25°C
20 400 20 125°C
SUPPLY CURRENT (mA)

350 19 25°C
15 300 25°C 18
125°C
250 17

10 200 16 –55°C
–55°C
150 15

5 100 14
ISHUT 50 13
ISTART
0 0 12
0 5 10 15 20 25 30 0 3 6 9 12 15 0 5 10 15 20 25 30 35 40
INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V)
LT1103 G01 LT1103 G02 LT1103 G03

Rev. F

For more information LT1103/LT1105 5

LT1103/LT1105
TYPICAL PERFORMANCE CHARACTERISTICS
Quiescent Supply Current vs Shutdown Supply Current vs Input Shutdown Supply Current vs
Temperature Voltage VC Voltage
22 500 500
21 450 450
QUIESCENT SUPPLY CURRENT (mA)

SHUTDOWN SUPPLY CURRENT (µA)

20 30V 400 400

SHUTDOWN CURRENT (µA)

19 350 350
18 300 300
17 250 250
8V VC = 75mV 25°C 125°C
16 200 200
15 150 150
VC = 0
14 100 100 –55°C

13 50 50
12 0 0
–75 –50 –25 0 25 50 75 100 125 150 175 0 5 10 15 20 25 30 35 0 20 40 60 80 100 120 140 160 180 200
TEMPERATURE (°C) INPUT VOLTAGE (V) VC (mV)
LT1103 G04 LT1103 G05 LT1103 G06

VIN Start-Up Threshold vs VIN Shutdown Threshold vs Output Switch Frequency vs

Temperature Temperature Temperature
17.5 8.0 45
COSC = 1000pF

OUTPUT SWITCH FREQUENCY (kHz)

17.0
VIN SHUTDOWN THRESHOLD (V)
VIN START-UP THRESHOLD (V)

7.7 43

16.5
7.4 41
16.0
7.1 39
15.5

6.8 37
15.0

14.5 6.5 35
–75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
LT1103 G07 LT1103 G08 LT1103 G09

Preset Switch Maximum Duty Switch Oscillator Frequency vs Overvoltage Lockout Threshold vs
Cycle vs Temperature Capacitance Temperature
75 1000 3.0
COSC = 1000pF
OVERVOLTAGE LOCKOUT THRESHOLD (V)
PRESET SWITCH DUTY CYCLE (%)

72 2.8
SWITCH FREQUENCY (kHz)

69 2.6
100
66 2.4

63 2.2

60 10 2.0
–75 –50 –25 0 25 50 75 100 125 150 175 100 1000 10000 –75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C) CAPACITANCE (pF) TEMPERATURE (°C)
LT1103 G10 LT1103 G11 LT1103 G12

Rev. F

6 For more information LT1103/LT1105

 LT1103/LT1105
TYPICAL PERFORMANCE CHARACTERISTICS
OVLO Input Bias Current vs Soft-Start Charging Current vs Soft-Start Reset Current vs
Temperature Temperature Temperature
0 60 5
OVLO = 2V

SOFT-START CHARGING CURRENT (µA)

SOFT-START RESET CURRENT (mA)

–0.5 50
OVLO INPUT BIAS CURRENT (µA)

–1.0 40
3
–1.5 30
2
–2.0 20

1
–2.5 10

–3.0 0 0
–75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
LT1103 G13 LT1103 G14 LT1103 G15

5V Reference Voltage vs 5V Load Regulation vs 5V Line Regulation vs

Temperature Temperature Temperature
5.20 0.025 0.05

5.15
5V LOAD REGULATION (%/mA)

0.020 0.04
5V REFERENCE VOLTAGE (V)

5V LINE REGULATION (%/V)

5.10

5.05 0.015 0.03

5.00

4.95 0.010 0.02

4.90
0.005 0.01
4.85

4.80 0 0
–75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
LT1103 G16 LT1103 G17 LT1103 G18

5V Reference Short-Circuit 15V Gate Bias Reference vs 15V Gate Bias Dropout Voltage vs
Current vs Temperature Temperature Temperature
110 16.2 2.5
5V REFERENCE SHORT-CIRCUIT CURRENT (mA)

15V GATE BIAS DROPOUT VOLTAGE (V)

100
15.8
15V GATE BIAS REFERENCE (V)

2.0
90
15.4
80 1.5

70 15.0

60 1.0
14.6
50
0.5
14.2
40

30 13.8 0
–75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (C) TEMPERATURE (°C) TEMPERATURE (°C)
LT1103 G19 LT1103 G20 LT1103 G21

Rev. F

For more information LT1103/LT1105 7

 LT1103/LT1105
TYPICAL PERFORMANCE CHARACTERISTICS
15V Gate Bias Short-Circuit Low Switch Drive Lockout High Switch Drive Lockout
Current vs Temperature Threshold vs Temperature Threshold vs Temperature
130 10.5 20.0

HIGH SWITCH DRIVE LOCKOUT THRESHOLD (V)

15V GATE BIAS SHORT-CIRCUIT CURRENT (mA)

LOW SWITCH DRIVE LOCKOUT THRESHOLD (V)

19.5
110 10.2

19.0
90 9.9
18.5
70 9.6
18.0

50 9.3
17.5

30 9.0 17.0
–75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
LT1103 G22 LT1103 G23 LT1103 G24

Change in FB Input Bias Current

Feedback Threshold vs FB Input Bias Current vs with Change in VC vs Temperature
Temperature Temperature (VC = 1V) (VC = 1V to 4V)
4.60 20 14

CHANGE IN FB INPUT BIAS CURRENT

13
4.56 16
FB INPUT BIAS CURRENT (µA)

WITH CHANGE IN VC (µA/V)

FEEDBACK THRESHOLD (V)

12

4.52 12
11

10
4.48 8

9
4.44 4
8

4.40 0 7
–75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
LT1103 G25 LT1103 G26 LT1103 G27

Error Amplifier Transconductance Error Amplifier Transconductance Error Amplifier Voltage Gain vs
vs Temperature and Phase vs Frequency Temperature
ERROR AMPLIFIER TRANSCONDUCTANCE (µmho)

25000 0.020 200 2500

ERROR AMPLIFIER TRANSCONDUCTANCE (mho)

0.018 PHASE 180

ERROR AMPLIFIER VOLTAGE GAIN (V/ V)

0.016 160
20000 gm 2000
0.014 140
PHASE (DEGREES)

0.012 120
15000 0.010 100 1500
0.008 80
0.006 60
10000 1000
0.004 40
gm
0.002 20
PHASE
5000 0 0 500
–75 –50 –25 0 25 50 75 100 125 150 175 0.1 1 10 100 1000 –75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C) FREQUENCY (kHz) TEMPERATURE (°C)
LT1103 G28 LT1103 G29 LT1103 G30

Rev. F

8 For more information LT1103/LT1105

 LT1103/LT1105
TYPICAL PERFORMANCE CHARACTERISTICS
Error Amplifier Source Current vs Error Amplifier Sink Current vs Error Amplifier High Clamp
Temperature Temperature Voltage vs Temperature (FB = 4V)
350 4.5 4.5

ERROR AMPLIFIER HIGH CLAMP VOLTAGE (V)

ERROR AMPLIFIER SOURCE CURRENT (µA)

ERROR AMPLIFIER SINK CURRENT (mA)

325
4.0
4.4
300
3.5
275 4.3

250 3.0

225 4.2
2.5
200
4.1
2.0
175

150 1.5 4.0

–75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
LT1103 G31 LT1103 G32 LT1103 G33

Error Amplifier Low Clamp

Voltage vs Temperature VC Switching Threshold Voltage LT1103 Output Switch Leakage
(FB = 4.75V) vs Temperature Current vs Temperature

LT1103 OUTPUT SWITCH LEAKAGE CURRENT (µA)

0.9 1.5 200
ERROR AMPLIFIER LOW CLAMP VOLTAGE (V)

0.8
VC SWITCHING THRESHOLD (V)

1.3 160

0.7 VSW = 45V

1.1 120
0.6
0.9 80 VSW = 15V
0.5

0.7 40
0.4

0.3 0.5 0
–75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
LT1103 G34 LT1103 G35 LT1103 G36

LT1103 Switch Saturation Voltage LT1103 VSW Current Limit vs LT1103 VSW Current Limit vs
vs Temperature Duty Cycle Temperature
1.2 3.0 3.0
LT1103 SWITCH SATURATION VOLTAGE (V)

–55°C DC = 25%
2.9
1.0 2.5
LT1103 VSW CURRENT LIMIT (A)

25°C
LT1103 VSW CURRENT LIMIT (A)

2.8

125°C 2.7
0.8 2.0
ISW = 1.5A 2.6
0.6 1.5 2.5
2.4
0.4 1.0
2.3
ISW = 0.5A
2.2
0.2 0.5
2.1
0 0 2.0
–75 –50 –25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60 70 80 –75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C) DUTY CYCLE (%) TEMPERATURE (°C)
LT1103 G38 LT1103 G39 LT1103 G40

Rev. F

For more information LT1103/LT1105 9

LT1103/LT1105
TYPICAL PERFORMANCE CHARACTERISTICS
LT1103 Driver Current vs LT1105 VSW Low Saturation LT1105 VSW High Saturation
Temperature Voltage vs Temperature Voltage vs Temperature
50 3.0 3.0

LT1105 VSW HIGH SATURATION VOLTAGE (V)

LT1105 VSW LOW SATURATION VOLTAGE (V)
2.5 2.5
LT1103 DRIVER CURRENT (mA/A)

40

ISW = 750mA
2.0 2.0
30
1.5 1.5
20 ISW = 200mA
ISW = 750mA
1.0 1.0

10
0.5 ISW = 200mA 0.5

0 0 0
–75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
LT1103 G41 LT1103 G42 LT1103 G43

LT1105 Current Limit Threshold LT1105 VSW Rise Time vs LT1105 VSW Fall Time vs
Voltage vs Temperature Temperature Temperature
LT1105 CURRENT LIMIT THRESHOLD VOLTAGE (mV)

450 100 100

DC = 25°C
425
80 80

LT1105 VSW FALL TIME (ns)

LT1105 VSW RISE TIME (ns)

400
60 CLOAD = 4700pF 60
375 CLOAD = 4700pF
40 CLOAD = 1000pF 40
350

20 20
325
CLOAD = 1000pF
300 0 0
–75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175 –75 –50 –25 0 25 50 75 100 125 150 175
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
LT1103 G46 LT1103 G44 LT1103 G45

Rev. F

10 For more information LT1103/LT1105

 LT1103/LT1105
PIN FUNCTIONS
LT1103 VSW: The Switch Output pin is the collector of the internal
NPN power switch. This pin has a typical ON resistance of
FB: The Feedback pin is the inverting input to the sampling
0.4Ω and a minimum breakdown voltage of 50V. This pin
error amplifier. The noninverting input is tied to a 4.5V
also ties to the FET gate drive detection circuit.
reference. The FB pin is used for output voltage sensing.
The input bias current is a function of the control pin VC
voltage and can be used for load regulation compensa- LT1105
tion by including a resistor in series with the FB pin. The All functions on the LT1105 are equivalent to the LT1103
sampling error amplifier has a typical gm of 0.012 mhos with the exception of the VSW pin and the ILIM pin and the
and the output of the sampling error amplifier has asym- availability of the OVLO, 5V, and SS functions.
metrical slew rate to reduce overshoot during start-up
conditions or following the release of an output overload. OVLO: The Overvoltage Lockout pin inhibits switching
when the pin is pulled above its threshold voltage of 2.5V.
VC: The VC control pin is used for frequency compensa- OVLO is implemented with a resistor divider network from
tion, current limiting and shutdown. It is the high imped- the rectified DC line and is used to protect the external
ance output of the sampling error amplifier and the input FET from an overvoltage condition in the off state. This
of the current limit comparator. function is only available on the 14-lead PDIP.
GND: The Ground pin acts as both the negative sense 5V: A 5V reference is available to power primary-side cir-
point for the internal sampling error amplifier feedback cuitry. The temperature coefficient is typically 50ppm/°C
signal and as the high current path for the 2A switch. Also, and the output can source 25mA. This function is only
the case of the 7-lead TO-220 is connected to ground. available on the 14-lead PDIP.
Proper connections to ground for signal paths and high
current paths must be made in order to insure good load SS: The Soft-Start pin is used to either program start-up
regulation. time with a capacitor to ground or to set external current
limit with a resistor divider. The SS pin has a 40µA pull-up
OSC: The Oscillator pin sets the operating frequency current and is reset to 0V by a 1mA pull-down current dur-
of the regulator with one external capacitor to ground. ing start-up and shutdown. This function is only avail-able
Maximum duty cycle can also be adjusted by using an on the 14-lead PDIP.
external resistor to alter the charge/discharge ratio.
VSW: The Switch Output pin is the output of a 1A NPN
VIN: The Input Supply pin is designed to operate with volt- totem-pole stage. The VSW pin turns the external FET
ages of 12V to 30V. The supply current is typically 200µA on by pulling its gate high. Break-Before-Make action of
up to the start-up threshold of 16V. Normal operating 200ns on each switch edge is built in to eliminate cross
supply current is fairly flat at 18mA down to the shutdown conduction currents.
threshold of 7V. Switching is inhibited for VIN less than
12V due to the gate drive detection circuit. ILIM: The ILIM pin is the input to the current limit amplifier
and requires the use of a noninductive, power sense resis-
15V: A 15V reference is used to bias the gate of an exter- tor from ILIM to ground to set current limit. The typical
nal power FET. The voltage temperature coefficient is typi- current limit threshold voltage is 350mV. The typical input
cally 3mV/°C and the output can source 30mA. Typical bias current is 100µA out of the pin.
dropout voltage is 1.5V for VIN less than 17V and 30mA
of load current.

Rev. F

For more information LT1103/LT1105 11

LT1103/LT1105
BLOCK DIAGRAM
LT1103
VSW
OSC
GATE
15V BIAS
15V GATE DETECT
BIAS

OSCILLATOR
START-UP
16V
VIN LOGIC DRIVER
7V

SPIKE
BLANK

ANTISAT
COMP
5V 4.5V +
5V VREF CURRENT
LIMIT +
– AMP
AV = 10 0.15Ω
FB SAMPLING 6V –
ERROR AMP
gm = 0.012
40µA
0VLO
SHUT
DOWN
RESET
OVERVOLTAGE
2.5V LOCKOUT 0.15V

LT1103 BD

VC SS GND

LT1105

OSC
15V GATE
15V GATE BIAS
BIAS DETECT

OSCILLATOR
START-UP
16V DRIVER
VIN LOGIC
VSW
7V
DRIVER
SPIKE
BLANK

ANTISAT
COMP
5V 4.5V
5V
+ CURRENT
VREF LIMIT
ILIM
+
– AMP
AV = 10
SAMPLING 6V
FB
–
ERROR AMP
gm = 0.012
40µA
0VLO
SHUT
DOWN
RESET
OVERVOLTAGE
2.5V 0.15V
LOCKOUT

LT1105 BD

VC SS GND
Rev. F

12 For more information LT1103/LT1105

 LT1103/LT1105
OPERATION
LT1103 turning on if the gate voltage is less than 10V or greater than
20V, the industry standards for power MOSFET operation.
The LT1103 is a current mode switcher. Switch duty cycle
is controlled by switch current rather than directly by the The switch current is sensed internally and amplified to
output voltage. Referring to the block diagram, the switch trip the comparator and turn off the switch according to
is turned on at the start of each oscillator cycle. It is turned the VC pin control voltage. A blanking circuit suppresses
off when switch current reaches a predetermined level. the output of the current limit comparator for 500ns at
Control of output voltage is obtained by using the output the beginning of each switch cycle. This prevents false
of a voltage sensing error amplifier to set current trip tripping of the comparator due to current spikes caused
level. This technique has several advantages. First, it has by external parasitic capacitance and diode stored charge.
immediate response to input voltage variations, unlike The 4.5V Zener-based reference biases the positive input
ordinary switchers which have notoriously poor line tran- of the sampling error amplifier. The negative input (FB)
sient response. Second, it reduces the 90°phase shift at is used for output voltage sensing. The sampling error
mid frequencies in the transformer. This greatly simpli- amplifier allows the LT1103 to operate in fully isolated
fies closed-loop frequency compensation under widely flyback mode by regulating from the flyback voltage of
varying input voltage or output load conditions. Finally, it the bootstrap winding. The leakage inductance spike at
allows simple pulse-by-pulse current limiting to provide the leading edge of the flyback waveform is ignored with
maximum switch protection under output overload or a blanking circuit. The flyback waveform is directly pro-
short-circuit conditions. portional to the output voltage in a transformer-coupled
A start-up loop with hysteresis allows the IC supply volt- flyback topology. Output voltages are fully floating up
age to be bootstrapped from an extra primary side wind- to the breakdown voltage of the transformer windings.
ing on the power transformer. From 0V to 16V on VIN, the Multiple floating outputs are easily obtained with addi-
LT1103 is in a prestart mode and total input current is typ- tional windings.
ically 200µA. Above 16V, up to 30V, the 6V regulator that The error signal developed at the comparator input is
biases the internal circuitry and the externally available brought out externally. This VC pin has three functions
15V regulator is turned on. The internal circuitry remains including frequency compensation, current limit adjust-
biased on until VIN drops below 7V and the part returns to ment and total regulator shutdown. During normal opera-
the prestart mode. Output switching stops when the VSW tion, this pin sits at a voltage between 1.2V (low output
drive is less than 10V corresponding to VIN of about 12V.
current) and 4.4V (high output current). The error ampli-
The oscillator provides the basic clock for all internal tim- fier is a current output (gm) type, so this voltage can be
ing. Frequency is adjustable to 200kHz with one external externally clamped for adjusting current limit. Switch duty
capacitor from OSC to ground. The oscillator turns on the cycle goes to zero if the VC pin is pulled to ground through
output switch via the logic and driver circuitry. Adaptive a diode, placing the LT1103 in an idle mode. Pulling the
antisat circuitry detects the onset of saturation in the VC pin below 0.15V causes total regulator shutdown and
power switch and adjusts driver current instantaneously places the LT1103 in a prestart mode.
to limit switch saturation. This minimizes driver dissipa-
tion and provides very rapid turn-off of the switch. LT1105
The LT1103 is designed to drive the source of an exter- The LT1105 is a current mode switcher. Switch duty cycle
nal power FET in common gate configuration. The 15V is controlled by switch current rather than directly by out-
regulator biases the gate to guarantee the FET is on when put voltage. Referring to the block diagram, the switch is
the switch is on. Special drive detection circuitry senses turned on at the start of each oscillator cycle. It is turned
the gate bias voltage and prevents the output switch from off when switch current reaches a predetermined level.

Rev. F

For more information LT1103/LT1105 13

LT1103/LT1105

Control of output voltage is obtained by using the output circuit suppresses the output of the current limit com-
of a voltage sensing error amplifier to set current trip parator for 500ns at the beginning of each switch cycle.
level. This technique has several advantages. First, it has This prevents false tripping of the comparator due to cur-
immediate response to input voltage variations, unlike rent spikes caused by external parasitic capacitance and
ordinary switchers which have notoriously poor line tran- diode stored charge.
sient response. Second, it reduces the 90°phase shift at A 4.5V Zener-based reference biases the positive input
midfrequencies in the transformer. This greatly simpli- of the sampling error amplifier. The negative input (FB)
fies closed-loop frequency compensation under widely is used for output voltage sensing. The sampling error
varying input voltage or output load conditions. Finally, it amplifier allows the LT1105 to operate in fully isolated
allows simple pulse-by-pulse current limiting to provide flyback mode by regulating the flyback voltage of the
maximum switch protection under output overload or bootstrap winding. The leakage inductance spike at the
short-circuit conditions. leading edge of the flyback waveform is ignored with a
A start-up loop with hysteresis allows the IC supply volt- blanking circuit. The flyback waveform is directly propor-
age to be bootstrapped from an extra primary side wind- tional to the output voltage in the transformer coupled
ing on the power transformer. From 0V to 16V on VIN, flyback topology. Output voltages are fully floating up
the LT1105 is in prestart mode and total input current is to the breakdown voltage of the transformer windings.
typically 200µA. Above 16V, up to 30V, the 6V regulator Multiple floating outputs are easily obtained with addi-
that biases the internal circuitry and the externally avail- tional windings.
able 5V and 15V regulators are turned on. The internal The error signal developed at the comparator input is
circuitry remains biased on until VIN drops below 7V and brought out externally. The VC pin has three functions
the part returns to prestart mode. Output switching stops including frequency compensation, current limit adjust-
when the 15V gate bias reference is less than 10V cor- ment and total regulator shutdown. During normal opera-
responding to VIN of about 12V. tion, this pin sits at a voltage between 1.2V (low output
The oscillator provides the basic clock for all internal tim- current) and 4.4V (high output current). The error ampli-
ing. Frequency is adjustable to 200kHz with one external fier is a current output (gm) type, so this voltage can be
capacitor from OSC to ground. The oscillator turns on the externally clamped for adjusting current limit. Switch duty
output switch via the logic and driver circuitry. cycle goes to zero if the VC pin is pulled to ground through
a diode, placing the LT1105 in an idle mode. Pulling the
The LT1105 is designed to drive the gate of an external
VC pin below 0.15V causes total regulator shutdown and
power FET in common source configuration. The drivers
places the LT1105 in prestart mode.
and the 1A maximum totem-pole output stage are biased
from the 15V gate bias reference. Special drive detec- The SS pin implements soft-start with one external capac-
tion circuity senses the gate bias reference voltage and itor to ground. The internal pull-up current and clamp
prevents the output switch from turning on if this voltage transistor limit the voltage at VC to one diode drop above
is less than 10V or greater than 20V. Break-Before-Make the voltage at the SS pin, thereby controlling the rate of
action of 200ns is built into each switch edge to eliminate rise of switch current in the regulator. The SS pin is reset
cross conduction currents. to 0V when the LT1105 is in prestart mode.
Switch current is sensed externally through a precision, A final protection feature includes overvoltage lockout
power resistor. This allows for greater flexibility in switch monitoring of the main supply voltage on the OVLO pin.
current and output power than allowed by the LT1103. If the OVLO pin is greater than 2.5V, the output switch is
The voltage across the sense resistor is fed into the ILIM prevented from turning on. This function can be disabled
pin and amplified to trip the comparator and turn off the by grounding the OVLO pin.
switch according to the VC pin control voltage. A blanking

Rev. F

14 For more information LT1103/LT1105

 LT1103/LT1105
APPLICATIONS INFORMATION
Bootstrap Start maximum rectified DC input voltage. A final consideration
for the start-up resistor is to insure that the maximum
It is inefficient as well as impractical to power a switching
voltage rating of the resistor is not exceeded. Typical car-
regulator control IC from the rectified DC input as this
bon film resistors have a voltage rating of 250V. The most
voltage is several hundred volts. Self-biased switching
reliable and economical solution for the start-up resistor
regulator topologies take advantage of a lower voltage
is generally provided by placing several 0.25W resistors
auxiliary winding on the power transformer or inductor to
in series.
power the regulator, but require a start-up cycle to begin
regulation. The LT1103/LT1105 is designed to operate with supply
pin voltages up to 30V. However, the auxiliary bias wind-
Start-up circuitry with hysteresis built into the LT1103/
ing should be designed for a typical output voltage of
LT1105 allows the input voltage to increase from 0V to
17V to minimize IC power dissipation and efficiency loss.
16V before the regulator tries to start. During this time
the start-up current of the switching regulator is typi- Allowances must also be made for cross regulation of
the bias voltage due to variations in the rectified DC line
cally 200µA and all internal voltage regulators are off.
voltage and output load current.
The low quiescent current allows the input voltage to be
trickled up with only 500µA of current from the rectified Soft-Start
DC line voltage, thereby minimizing power dissipation in
the start-up resistor. At 16V, the internal voltage regula- Soft-start refers to the controlled increase of switch cur-
tors are turned on and switching begins. If enough power rent from a start-up or shutdown state. This allows the
feeds back through the auxiliary winding to keep the input power supply to come up to voltage in a controlled man-
voltage to the switching regulator above 12V, then switch- ner and charge the output capacitor without activating
ing continues and a bootstrap start is accomplished. If current limit. In general, soft-start is not required on the
the input voltage drops below 12V, then the FET drive LT1105 due to the design of the sampling error amplifier
detection circuit locks out switching. The input voltage gm stage which generates asymmetrical slew capability
continues to fall as the VIN bypass capacitor is discharged on the VC pin.
by the normal quiescent current of the LT1103/LT1105. This feature exhibits itself as a typical 3mA sink current
Once the input voltage falls below 7V, the internal volt- capability on the VC pin whereas source current is only
age regulators are turned off and the switching regulator 275µA. The low gm of the error amplifier allows small-
returns to the low start-up current state. A continuous valued compensation capacitors to be used on VC. This
“burp start” mode indicates a fault condition or an incom- allows the sink current to slew the compensation capaci-
plete power loop. tor quickly. Therefore, overshoot of the output voltage on
The trickle current required to bootstrap the regulator start-up sequences and recovery from overload or short-
input voltage is typically generated with a resistor from circuit conditions is prevented. However, if a longer start-
the rectified DC input voltage. When combined with the up period is required, the soft-start function can be used.
regulator input bypass capacitor, the start-up resistor cre- Soft-start is implemented with an internal 40µA pull-up
ates a ramp whose slope governs the turn-on time of the and a transistor clamp on the VC pin so that a single exter-
regulator as well as the period of the “burp start” mode. nal capacitor from SS ground can define the linear ramp
The design trade-offs are power dissipated in the trickle function. The voltage at VC is limited to one VBE above the
resistor, the turn-on time of the regulator, and the hold-up soft-start pin (SS). The time to maximum switch current is
time of the regulator input bypass capacitor. The value defined as the capacitance on SS multiplied by the active
of the start-up resistor is set by the minimum rectified range in volts of the VC pin divided by the pull-up current:
DC input voltage to guarantee sufficient start-up current.
The recommended minimum trickle current is 500µA. C• (3.2V)
T=
The power rating of the start-up resistor is set by the 40µA
Rev. F

For more information LT1103/LT1105 15

LT1103/LT1105
APPLICATIONS INFORMATION
SS is reset to 0V whenever VIN is less than 7V (prestart Ground (LT1103)
mode) or when shutdown is activated by pulling VC below The ground pin of the LT1103 is important because it acts
0.15V. The SS pin has a guaranteed reset sink current of as the negative sense point for the internal error amplifier
1mA when either the regulator supply voltage VIN falls feedback signal, the negative sense point for the current
below 7V or the regulator is placed in shutdown. limit amplifier, and as the high current path for the 2A
switch. The tab of the 7-lead TO-220 is internally con-
Shutdown
nected to GND (Pin 4).
The LT1103/LT1105 can be put in a low quiescent cur-
To avoid degradation of load regulation, the feedback
rent shutdown mode by pulling VC below 150mV. In the
resistor divider string and the reference side of the bias
shutdown mode the internal voltage regulators are turned
winding should be directly connected to the ground pin
off, SS is reset to 0V and the part draws less than 200µA.
on the package. These ground connections should not
To initiate shutdown, about 400µA must be pulled out
be mixed with high current carrying ground return paths.
of VC until the internal voltage regulators turn off. Then,
The length of the switch current ground path should be
less than 50µA pull-down current is required to maintain
as short as possible to the input supply bypass capacitor
shutdown. The shutdown function has about 60mV of
and low resistance for best performance. The case of the
hysteresis on the VC pin before the part returns to normal
LT1103 package is desirable to use as the high current
operation. Soft-start, if used, controls the recovery from
ground return path as this is a lower resistive and induc-
shutdown.
tive path than that of the actual package pin and will help
5V Reference minimize voltage spikes associated with the high dI/dt
switch current.
A 5V reference output is available for the user’s conve-
nience to power primary-side circuitry or to generate a Avoiding long wire runs to the ground pin minimizes
clamp voltage for switch current limiting. The output will load regulation effects and inductive voltages created by
source 25mA and the voltage temperature coefficient is the high dI/dt switch current. Ground plane techniques
typically 50ppm/°C. If bypassing of the 5V reference is should also be used and will help keep EMI to a mini-
required, a 0.1µF is recommended. Values of capacitance mum. Grounding techniques are illustrated in the Typical
greater than 1µF may be susceptible to ringing due to Applications section.
decreased phase margin. In such cases, the capacitive
Ground (LT1105)
load can be isolated from the reference output with a
small series resistor at the expense of load regulation The ground pin of the LT1105 is important because it acts
performance. as the negative sense point for the internal error amplifier
feedback signal and as the negative sense point for the
Overvoltage Lockout current limit amplifier. The LT1105 8-pin PDIP has Pin
The switching supply and primarily the external power 1 as its ground. The LT1105 14-pin PDIP has Pin 1 and
MOSFET can be protected from an extreme surge of the Pin 7 as grounds and must be tied together for proper
input line voltage with the overvoltage lockout feature operation.
implemented on the OVLO pin. If the voltage on OVLO To avoid degradation of load regulation, the feedback
rises above its typical threshold voltage of 2.5V, output resistor divider should be directly connected to the pack-
switching is inhibited. This feature can be implemented age ground pin. These ground connections should not
with a resistive divider off of the rectified DC input voltage. be mixed with high current carrying ground return paths.
This feature is only available on the LT1105 in the 14-lead The length of the switch current ground path should be
PDIP and must be tied to ground if left unused. as short as possible to the input supply bypass capacitor
and low resistance for best performance. This will help
Rev. F

16 For more information LT1103/LT1105

 LT1103/LT1105
APPLICATIONS INFORMATION
minimize voltage spikes associated with the high dI/dt Note that the capacitor value must change to maintain the
switch current. same frequency. For example, a 24k resistor from 5V to
OSC and a 440pF capacitor from OSC to ground will yield
Avoiding long wire runs to the ground pin minimizes
100kHz with 50% maximum duty cycle. A 56k resistor and
load regulation effects and inductive voltages created by
a 280pF capacitor from OSC to ground will yield 100kHz
the high dI/dt switch current. Ground plane techniques
with 80% maximum duty cycle.
should also be used and will help keep EMI to a mini-
mum. Grounding techniques are illustrated in the Typical The oscillator can be synchronized to an external clock by
Applications section. coupling a sync pulse into the OSC pin. The width of this
pulse should be a minimum of 500ns. The oscillator can
Oscillator only be synchronized up in frequency and the synchroniz-
The oscillator of the LT1103/LT1105 is a linear ramp type ing frequency must be greater than the maximum pos-
powered from the internal 6V bias line. The charging cur- sible unsynchronized frequency (for the chosen oscillator
rents and voltage thresholds are generated internally so capacitor value). The amplitude of the sync pulse must be
that only one external capacitor is required to set the fre- chosen so that the sum of the oscillator voltage amplitude
quency. The 150µA pull-up current, which is on all the plus the sync pulse amplitude does not exceed the 6V
time, sets the preset maximum on-time of the switch and bias reference. Otherwise, the oscillator pull-up current
the 450µA pull-down current which is turned on and off, source will saturate and erroneous operation will result.
sets the dead time. The threshold voltages are typically 2V If the LT1103/LT1105 is positioned on the primary side
and 4.5V, so for a 400pF capacitor the ramp-up time of the of the transformer and the external clock on the isolated
voltage on the OSC pin is 6.67µs and the ramp-down time secondary output side, the sync signal must be coupled
is 3.3µs, resulting in an operating frequency of 100kHz. into the OSC pin using a pulse transformer. The pulse
Although the oscillator, as well as the rest of the switching transformer must meet all safety/isolation requirements
regulator, will function at higher frequencies, 200kHz is as it also crosses the isolation boundary. An example of
the practical upper limit that will allow control range for externally synchronizing the oscillator is shown in the
line and load regulation. The lowest operating frequency Typical Applications section.
is limited by the sampling error amplifier to about 10kHz.
Gate Biasing (LT1103)
The frequency temperature coefficient is typically
The LT1103 is designed to drive an external power
–80ppm/°C with a good low T.C. capacitor. This means
MOSFET in the common gate or cascode connection with
that with a low temperature coefficient capacitor, the tem-
the VSW pin. The advantage is that the switch current
perature coefficient of the currents and the temperature
can be sensed internally, eliminating a low value, power
coefficient of the thresholds sum to –80ppm/°C over the
sense resistor. The gate needs to be biased at a voltage
commercial temperature range. Bowing in the tempera-
high enough to guarantee that the FET is saturated when
ture coefficient of the currents affects the frequency about
the open-collector source drive is on. This means 10V as
±3% at the extremes of the military temperature range.
specified in FET data sheets, plus 1V for the typical switch
The capacitor type chosen will have a direct effect on the
saturation voltage, plus a couple of volts for temperature
frequency tempco.
variations and processing tolerances. This leads to 15V
Maximum duty cycle is set internally by the pull-up and for a practical gate bias voltage.
pull-down currents, independent of frequency. It can be
Power MOSFETs are well suited to switching power sup-
adjusted externally by modifying the fixed pull-up current
plies because their high speed switching characteris-
with an additional resistor. In practice, one resistor from
tics promote high switching efficiency. To achieve high
the OSC pin to the 5V reference or to ground does the job.
switching speed, a special circuit in the LT1103 senses

Rev. F

For more information LT1103/LT1105 17

LT1103/LT1105
APPLICATIONS INFORMATION
the voltage at VSW prior to turning on the switch. VSW is itself to keep the switch just at the edge of saturation. Very
tied to the source of the FET and should represent the low switch current results in nearly zero driver current
bias voltage on the gate when the switch is off. When and high switch currents automatically increase driver
the switch first turns off, the drain flies back until it is current as necessary. The ratio of switch current to driver
clamped by a snubber network. The source also flies current is approximately 30:1. This ratio is determined by
high due to parasitic capacitive coupling on the FET and the sizing of the extra emitter and the value of the current
parasitic inductance of the leads. An extra diode from the source feeding the driver circuitry. The quasisaturation
source to the gate or VIN will provide insurance against state of the switch permits rapid turn-off without the need
fault conditions that might otherwise damage the FET. for reverse base emitter voltage drive.
The diode clamps the source to one diode drop above
the gate or VIN, thereby limiting the gate source reverse Gate Biasing (LT1105)
bias. Once the energy in the leakage inductance spike The LT1105 is designed to drive an external power
is dissipated and the primary is being regulated to its MOSFET in the common source configuration with the
flyback voltage, the diode shuts off. The source is then totem-pole output VSW pin. The advantage is added
floating and its voltage will be close to the gate voltage. switch current flexibility (limited only by the choice of
If the sensed voltage on VSW is less than 10V or greater external power FET) and higher output power applications
than 20V, the circuit prevents the switch from turning on. than allowed by LT1103. An external, noninductive, power
This protects the FET from dissipating high power in a sense resistor must be used in series with the source of
nonsaturated state or from excessive gate-source voltage. the FET to detect switch current and must be tied to the
The oscillator continues to run and the net effect is to skip input of the current limit amplifier. The gate needs to be
switching cycles until the gate bias voltage is corrected. biased at a voltage high enough to guarantee that the
One consequence of the gate bias detection circuit is that FET is saturated when the totem-pole gate drive is on.
the start-up window is 6V if the gate is biased from VIN This means 10V as specified in FET data sheets, plus
and to 4V if the gate is biased from the 15V output. This the totem-pole high side saturation voltage plus a couple
influences the size of the bypass capacitor on VIN. of volts for temperature variations and processing toler-
ances. This leads to 15V for a practical gate bias voltage.
VSW Output (LT1103)
Power MOSFETs are well suited to switching power sup-
The VSW pin of the LT1103 is the collector of an internal plies because their high speed switching characteris-
NPN power switch. This NPN has a typical on resistance tics promote high switching efficiency. To achieve high
of 0.4Ω and a typical breakdown voltage (BVCBO) of 75V. switching speed, the gate capacitance must be charged
Fast switching times and high efficiency are obtained by and discharged quickly with high peak currents. In par-
using a special driver loop which automatically adapts ticular, the turn-off current can be as high as the peak
base drive current to the minimum required to keep the switch current. The switching speed is controlled by
switch in a quasisaturated state. The key element in the the impedance seen by the gate capacitance. Practically
loop is an extra emitter on the output power transistor as speaking, zero impedance is not desirable because of the
seen in the block diagram. This emitter carries no current high frequency noise spikes introduced to the system.
when the NPN output transistor collector is high (unsatu- The gate bias supply which drives the totem-pole output
rated). In this condition, the driver circuit can deliver very stage should be bypassed with a 1µF low ESR capacitor
high base drive to the switch for fast turn-on. When the to ground. This capacitor supplies the energy to charge
switch saturates, the extra emitter acts as a collector of the gate capacitance during gate drive turn-on. The power
an NPN operating in inverted mode and pulls base current MOSFET should have a 5Ω resistor or larger in series with
away from the driver. This linear feedback loop serves its gate from the VSW pin to define the source impedance.

Rev. F

18 For more information LT1103/LT1105

 LT1103/LT1105
APPLICATIONS INFORMATION
The LT1105 provides a 15V regulated output intended switch just at the edge of saturation. This results in nearly
for driving the totem-pole output stage. It will source zero driver current. The quasisaturation state of the low
30mA into a capacitive load with no stability problems. side switch permits rapid turn-on of the external FET when
The output voltage temperature coefficient is 3mV/°C. If VSW pulls high.
VIN drops below 17V, the 15V output follows about 2.0V
below VIN until the part shuts down. If the 15V output is Fully Isolated Flyback Mode
pulled above 17.5V, it will sink 5mA. A unique sampling error amplifier included in the control
A special circuit in the LT1105 senses the voltage at the loop of the LT1103/LT1105 eliminates the need for an
15V regulated output prior to turning on the switch. The optoisolator while providing ±1% line and load regulation
15V regulator drives the totem-pole output stage and the in a magnetic flux-sensed flyback converter. In this mode,
VSW pin will pull the gate of the FET very close to the the flyback voltage on the primary during “switch off” time
value of the 15V output when VSW turns on. Therefore, is sensed and regulated. It is difficult to derive a feedback
the 15V output represents what the gate bias voltage on signal directly from the primary flyback voltage as this
the FET will be when the FET is turned on. If the sensed voltage is typically several hundred volts. A dedicated
voltage on the 15V output is less than 10V or greater winding is not required because the bias winding for the
than 20V, the circuit prevents the switch from turning regulator lends itself to flux-sensing. Flux-sensing made
on. This protects the FET from dissipating high power practical simplifies the design of off line power supplies
in a nonsaturated state or from excessive gate-source by minimizing the total number of external components
voltage. The oscillator continues to run and the net effect and reduces the components which must cross the isola-
is to skip switching cycles until the gate bias voltage is tion barrier to one, the transformer. This inherently implies
corrected. One consequence of the gate bias detection greater safety and reliability. The transformer must be
circuit is that the start-up window is 4V. This influences optimized for coupling between the bias winding and
the size of the bypass capacitor on VIN. the secondary output winding(s) while maintaining the
required isolation and minimizing the parasitic leakage
VSW Output (LT1105) inductances.
The VSW pin of the LT1105 is the output of a 1A totem- Although magnetic flux-sensing has been used in the
pole driver stage. This output stage turns an external past, the technique has exhibited poor output voltage
power MOSFET on by pulling its gate high. Break-Before- regulation due to the parasitics present in a transformer
Make action of 200ns is built into each switch edge to coupled design. Transformers which provide the safety
eliminate cross-conduction currents. Fast switching times and isolation as required by various international safety/
and high efficiency are obtained by using a low loss output regulatory agencies also provide the poorest output volt-
stage and a special driver loop which automatically adapts age regulation. Solutions to these parasitic elements have
base drive current to the totem-pole low side drive. The been achieved with the novel sampling error amplifier of
key element in the loop is an extra emitter on the output the LT1103/LT1105. A brief review of flyback converter
pull-down transistor as seen in the block diagram. This operation and the problems which create a poorly regu-
emitter carries no current when the low side transistor lated output will provide insight on how the sampling error
collector is high (unsaturated). In this condition, the driver amplifier of the LT1103/LT1105 addresses the regulation
can deliver very high base drive to the output transistor issue of magnetic flux sensed converters.
for fast turn-off. When the low side transistor saturates, The following figure shows a simplified diagram of a fly-
the extra emitter acts as a collector of an NPN operating back converter using magnetic flux sensing. The major
in inverted mode and pulls base current away from the parasitic elements present in the transformer coupled
driver. This linear feedback loop serves itself to keep the design are indicated. The relationships between the

Rev. F

For more information LT1103/LT1105 19

LT1103/LT1105
APPLICATIONS INFORMATION
primary voltage, the secondary voltage, the bias voltage to zero or changing polarity. Therefore, the voltage on
and the winding currents are indicated in the figures found the bias winding is only valid as a representation of the
on the following page for both continuous and discontinu- output voltage while the secondary is delivering current.
ous modes of operation. Although the bias winding flyback voltage is a representa-
Simplified Flyback Converter tion of the output voltage, its voltage is not constant. For
VIN
a brief period following the leakage inductance spike, the
L(IkPRI)
bias winding flyback voltage decreases due to nonlineari-
1:N
L(lkSEC) R D1 ties and parasitics present in the transformer. Following
VOUT this nonlinear behavior is a period where the bias winding
C1 flyback voltage decreases linearly. This behavior is easily
COMMON explained. Current flow in the secondary decreases lin-
S1 early at a rate determined by the voltage across the sec-
ondary and the inductance of the secondary. The parasitic
N = TURNS RATIO FROM SECONDARY TO PRIMARY.
VBIAS N1 = TURNS RATIO FROM SECONDARY TO BIAS. secondary leakage inductance appears as an impedance
N2 = N/N1
L(lkPRI) = PRIMARY LEAKAGE INDUCTANCE.
in series with the secondary winding. In addition, parasitic
L(lkSEC) = SECONDARY LEAKAGE INDUCTANCE. resistances exist in the secondary winding, the output
R = PARASITIC WINDING, DIODE AND OUTPUT
1:N1 CAPACITOR RESISTANCE.
LT1103 AI01
diode and the output capacitor. These impedances can
be combined to form a lumped sum equivalent and which
cause a voltage drop as secondary current flows. This
When the switch “turns on,” the primary winding sees the
voltage drop is coupled from the secondary to the bias
input voltage and the secondary and bias windings go to
winding flyback voltage and becomes more significant
negative voltages as a function of the turns ratio. Current
as the output is loaded more heavily. This voltage drop is
builds in the primary winding as the transformer stores
largest at the beginning of “switch off” time and smallest
energy. When the switch “turns off,” the voltage across
just prior to either all transformer energy being depleted
the switch flies back to a clamp level as defined by a snub-
or the switch turning on again.
ber network until the energy in the leakage inductance of
the primary dissipates. Leakage inductance is one of the The best representation of the output voltage is just prior
main parasitic elements in a flux-sensed converter and to either all transformer energy being used up and the
is modeled as an inductor in series with the primary and bias winding voltage collapsing to zero or just prior to
secondary of the transformer. These parasitic inductances the switch turning on again and the bias winding going
contribute to changes in the bias winding voltage and thus negative. This point in time also represents the small-
the output voltage with increasing load current. est forward voltage for the output diode. It is possible to
redefine the relationship between the secondary winding
The energy stored in the transformer transfers through
voltage and the bias winding voltage as:
the secondary and bias windings during “switch off” time.
Ideally, the voltage across the bias winding is set by the DC
VBIAS =
( VOUT + Vf +I • R P )
output voltage, the forward voltage of the output diode, N1
and the turns ratio of the transformer after the energy in
the leakage inductance spike of the primary is dissipated. where Vf is the forward voltage of the output diode, I is
the current flowing in the secondary, RP is the lumped
This relationship holds until the energy in the transformer
sum equivalent secondary parasitic impedance and N1 is
drops to zero (discontinuous mode) or the switch turns on
the transformer turns ratio from the secondary to the bias
again (continuous mode). Either case results in the volt-
winding. It is apparent that even though the above point
age across the secondary and bias windings decreasing

Rev. F

20 For more information LT1103/LT1105

 LT1103/LT1105
APPLICATIONS INFORMATION
Flyback Waveform for Continuous Mode Operation Flyback Waveform for Discontinuous Mode Operation

VZENER VZENER

PRIMARY SWITCH VOLTAGE PRIMARY SWITCH VOLTAGE

[VOUT + Vf + (ISEC • RP)]/N [VOUT + Vf + (ISEC • RP)]/N

a a
VIN VIN
AREA “a” = AREA “b” TO MAINTAIN AREA “a” = AREA “b” TO MAINTAIN
b b ZERO VOLTS ACROSS PRIMARY
ZERO VOLTS ACROSS PRIMARY
0V 0V

SECONDARY WINDING VOLTAGE SECONDARY WINDING VOLTAGE

[VOUT + Vf + (ISEC • RP)] [VOUT + Vf + (ISEC • RP)]
c c
0V 0V
AREA “c” = AREA “d” TO MAINTAIN AREA “c” = AREA “d” TO MAINTAIN
d d ZERO VOLTS ACROSS SECONDARY
ZERO VOLTS ACROSS SECONDARY
N • VIN N • VIN

BIAS WINDING VOLTAGE BIAS WINDING VOLTAGE

[VOUT + Vf + (ISEC • RP)]/N1
[VOUT + Vf + (ISEC • RP)]/N1 e
e
0V 0V
AREA “e” = AREA “f” TO MAINTAIN AREA “e” = AREA “f” TO MAINTAIN
f f
ZERO VOLTS ACROSS BIAS WINDING ZERO VOLTS ACROSS BIAS WINDING
N2 • VIN N2 • VIN

IPRI IPRI
∆I

PRIMARY CURRENT ∆I PRIMARY CURRENT

0A 0A

ISEC = IPRI/N ISEC = IPRI/N

SECONDARY CURRENT SECONDARY CURRENT

0A 0A

IPRI IPRI
∆I

SWITCH CURRENT ∆I SWITCH CURRENT

0A 0A

IPRI IPRI

SNUBBER DIODE CURRENT SNUBBER DIODE CURRENT

0A 0A
∆t = (IPRI)[L(lkPRI)]/ VSNUB ∆t = (IPRI)[L(lkPRI)]/VSNUB
LT1103 WF01

Rev. F

For more information LT1103/LT1105 21

LT1103/LT1105
APPLICATIONS INFORMATION
in time is the most accurate representation of the output flyback waveform as it changes with time and amplifies
voltage, the answer given by the bias winding voltage is the difference between the flyback signal and the internal
still off from the “true” answer by the amount I • RP/N1. 4.5V reference. Tracking is maintained until the point in
time where the bias winding voltage collapses as a result
The sampling error amplifier of the LT1103/LT1105 pro-
of all transformer energy being depleted (discontinuous
vides solutions to the errors associated with the bias
mode) or the switch turning on again (continuous mode).
winding flyback voltage. The error amplifier is comprised
The level detector circuit senses the fact that the bias
of a leakage inductance spike blanking circuit, a slew rate
winding flyback voltage is no longer a representation of
limited tracking amplifier, a level detector, a sample-and-
the output voltage and activates an internal peak detector.
hold, an output gm stage and load regulation compensa-
This effectively saves the most accurate representation of
tion circuitry. This all seems complicated at first glance,
the output voltage which is then buffered to the second
but its operation is straightforward and transparent to
stage of the error amplifier.
the user of the IC. When viewed from a system or block
level, the sampling error amplifier behaves like a simple The second stage of the error amplifier consists of a
transconductance amplifier. Here’s how it works. sample-and-hold. When the switch turns on, the sample-
and-hold samples the buffered error voltage for 1µs and
The sampling error amplifier takes advantage of the fact
then holds for the remainder of the switch cycle. This
that the voltage across the bias winding during at least a
held voltage is then processed by the output gm stage and
portion of switch off time is proportional to the DC output
converted into a control signal at the output of the error
voltage of the secondary winding. The feedback network
amplifier, the VC pin.
used to sense the bias winding voltage is no longer com-
prised of a traditional peak detector in conjunction with a The final adjustment in regulation is provided by the load
resistor divider network. The feedback network consists regulation compensation circuitry. As stated earlier, output
of a diode in series with the bias winding feeding the resis- regulation degrades with increasing load current (output
tor divider network directly. The resultant error signal is power). The effect is traced to secondary leakage induc-
then fed into the input of the error amplifier. The purpose tance and parasitic secondary winding, diode and output
of the diode in series with the bias winding is now not to capacitor resistances. Even though the tracking ampli-
peak detect, but to prevent the FB pin (input of the error fier has obtained the most accurate representation of the
amplifier) from being pulled negative and forward biasing output voltage, its answer is still flawed by the amount of
the substrate of the IC when the bias winding changes the voltage drop across the secondary parasitic lumped
polarity with “switch turn-on.” sum equivalent impedance which is coupled to the bias
winding voltage. This error increases with increasing load
The primary winding leakage inductance spike effects
current. Therefore, a technique for sensing load current
are first eliminated with an internal blanking circuit in the
conditions has been added to the LT1103/LT1105. The
LT1103/LT1105 which suppresses the input of the FB
switch current is proportional to the load current by the
pin for 1.5µs at the start of “switch off” time. This pre-
turns ratio of the transformer. A small current proportional
vents the primary leakage inductance spike from being
to switch current is generated in the LT1103/LT1105 and
propagated through the error amplifier and affecting the
fed back to the FB pin. This allows the input bias current
regulated output voltage.
of the sampling error amplifier to be a function of load
With the effects of the leakage inductance spike eliminated, current. A resistor in series with the FB pin generates
the effects of decreasing bias winding flyback voltage can a linear increase in the effective reference voltage with
be addressed. With the traditional diode/capacitor peak increasing load current. This translates to a linear increase
detector circuitry eliminated from the feedback network, in output voltage with increasing load current. By adjust-
the tracking amplifier of the LT1103/LT1105 follows the ing the value of the series resistor, the slope of the load

Rev. F

22 For more information LT1103/LT1105

 LT1103/LT1105
APPLICATIONS INFORMATION
compensation can be set to cancel the effects of these drops back to 0° (actually 180° since FB is an inverting
parasitic voltage drops. The feature can be ignored by input) when the reactance of CC is small compared to
eliminating the series resistor and lowering the equivalent RC. Thus, this RC series network forms a pole-zero pair.
divider impedance to swamp out the effects of the input The pole is set by the high impedance output of the error
bias current. amplifier and the value of CC on the VC pin. The zero is
formed by the value of CC and the value of RC in series
Frequency Compensation with CC on the VC pin. The RC series network will have
In order to prevent a regulator loop using the LT1103/ capacitor values in the range of 0.1µF to 1.0µF and series
LT1105 from oscillating, frequency compensation is resistor values in the range of 100Ω to 1000Ω .
required. Although the architecture of the LT1103/LT1105 It is noted that the RC network on the VC pin forms
is simple enough to lend itself to a mathematical approach the main compensation network for the regulator loop.
to frequency compensation, the added complication of However, if the load regulation compensation feature is
input/or output filters, unknown capacitor ESR, and gross used as explained in the section on fully-isolated flyback
operating point changes with input voltage and load cur- mode, additional frequency compensation components
rent variations all suggest a more practical empirical are required. The load regulation compensation feature
approach. Many hours spent on breadboards have shown involves the use of local positive feedback from the VC
that the simplest way to optimize the frequency compen- pin to the FB pin. Thus, it is possible to add enough load
sation of the LT1103/LT1105 is to use transient response regulation compensation to make the loop oscillate. In
techniques and an “RC” box to quickly iterate toward the order to prevent oscillation, it is necessary to roll off
final compensation network. Additional information on this local positive feedback at high frequencies. This is
this technique of frequency compensation can be found accomplished by placing a capacitor in parallel with the
in Linear Technology’s Application Note 19. compensation resistor which is in series with the FB pin.
In general, frequency compensation is accomplished with A value for this capacitor in the range of 0.01µF to 0.1µF is
an RC series network on the VC pin. The error amplifier recommended. The time constant associated with this RC
has a gm (voltage “in” to current “out”) of ≈ 12000 µmhos. combination will be longer than that associated with the
Voltage gain is determined by multiplying gm times the loop bandwidth. Thus, transient response will be affected
total equivalent error amplifier output loading, consisting in that settling time will be increased. However, this is typi-
of the error amplifier output impedance in parallel with the cally not as important as controlling the absolute under
series RC external frequency compensation network. At or overshoot amplitude of the system in response to load
DC, the external RC can be ignored. The output imped- current changes which could cause deleterious system
ance of the error amplifier is typically 100kΩ resulting in operation.
a voltage gain of ≈ 1200V/V. At frequencies just above DC,
Switching Regulator Topologies
the voltage gain is determined by the external compensa-
tion, RC and CC. The gain at mid frequencies is given by: Two basic switching regulator topologies are pertinent to
gm the LT1103/LT1105, the flyback and forward converter.
AV = The flyback converter employs a transformer to convert
2π • f • CC
one voltage to either a higher or lower output voltage.
The gain at high frequencies is given by: VOUT in continuous mode is defined as:
DC
AV = gm • RC VOUT = VIN • N•
(1–DC)
Phase shift from the FB pin to the VC pin is 90° at mid
frequencies where the external CC is controlling gain, then

Rev. F

For more information LT1103/LT1105 23

LT1103/LT1105
APPLICATIONS INFORMATION
where N is the transformer turns ratio of secondary to needed, a reasonable starting value is found by assigning
primary and DC is the duty cycle. This formula can be ∆I a value of 20% of the peak switch current (2A for the
rewritten in terms of duty cycle as: LT1103 and set by the external FET rating used with the
VOUT LT1105). With this design approach, LPRI is defined as:
DC =
( VOUT +N• VIN ) L PRI =
VIN
⎛ V ⎞
It is important to define the full range of input voltage, (ΔI)(f) ⎜1+ IN ⎟
⎝ VPRI ⎠
the range of output loading conditions and the regulation
requirements for a design. Duty cycle should be calcu- If maximum output power is not required, then ∆I can
lated for both minimum and maximum input voltage. be increased which results in lower primary inductance
In many applications, N can vary over a wide range with- and smaller magnetics. Maximum output power with an
out degrading performance. If maximum output power is isolated flyback converter is defined by the primary fly-
desired, N can be optimized: back voltage and the peak allowed switch current and is
limited to:
VOUT + Vf
N(OPT ) =
(V ) ( VPRI ) ⎡ ⎛ ΔI ⎞ 2 ⎤
VIN ⎜ IP ± ⎟ ± (Ip) R ⎥ E
M – VIN(MAX ) – VSNUB POUT(MAX) = ⎢
( VPRI + VIN ) ⎣ ⎝ 2 ⎠ ⎦
where
where
Vf = Forward voltage of the output diode
R = Total “switch” on resistance
VM = Maximum switch voltage
IP = Maximum switch current
VSNUB = Snubber clamp level – primary flyback voltage.
E = Overall efficiency ≈ 75%
In the isolated flyback mode, the LT1103/LT1105 sense
Peak primary current is used to determine core size for
and regulate the transformer primary voltage VPRI during
the transformer and is found from:
“switch off” time. The secondary output voltage will be
regulated if VPRI is regulated. VPRI is related to VOUT by:
IPR I =
( VOUT )(IOUT )( VPR I + VIN ) + ∆I
( VOUT + Vf) E ( VPR I ) ( VIN ) 2
VPR I =
N A second consideration on primary inductance is the
This allows duty cycle for an isolated flyback converter transition point from continuous mode to discontinuous
to be rewritten as: mode. At light loads, the flyback pulse across the primary
will drop to zero before the end of “switch off” time. The
VPR I
DC = Duty Cycle= load current at which this starts to occur can be calculated
( VPR I + VIN ) from:
An important transformer parameter to be determined is
IOUT( TR ANSITION) =
( VPR I • VIN )
2
the primary inductance LPRI. The value of this inductance
is a trade-off between core size, regulation requirements, ( VPR I + VIN )2 (2VOUT )( f)(LPR I )
leakage inductance effects and magnetizing current ∆I.
The forward converter as shown below is another trans-
Magnetizing current is the difference between the primary
former-based topology that converts one voltage to either
current at the start of “switch on” time and the current at
a higher or a lower voltage.
the end of “switch on” time. If maximum output power is

Rev. F

24 For more information LT1103/LT1105

 LT1103/LT1105
APPLICATIONS INFORMATION
VOUT in continuous mode is defined as: when S1 is off. This “reset” winding limits the maximum
duty cycle allowed for the switch. This topology trades
VOUT = VIN • N • DC
off reduced transformer size for increased complexity and
The secondary voltage charges up L1 through D1 when parts count. A separate isolated feedback path is required
S1 is on. When S1 is off, energy in L1 is transferred for full isolation from input to output because voltages on
through free-wheeling diode D2 to C1. The extra trans- the primary are no longer related to the DC output voltage
former winding and diode D3 are needed in a single during switch off time.
switch forward converter to define the switch voltage
The isolated feedback path can take several forms. A
Simplified Forward Converter second transformer in a modulator/demodulator scheme
L1
provides the isolation, but with significant complexity. An
VIN
1:N VOUT optoisolator can be substituted for the transformer with a
D1
savings in volume to be traded off with component varia-
D2 C1
tions and possible aging problems with the optoisolator
COMMON transfer function. Finally, an extra winding closely coupled
D3 S1 to the output inductor L1 can sense the flux in this ele-
ment and give a representation of the output voltage when
LT1103 AI02 S1 is off.

TYPICAL APPLICATIONS
LT1103 FET Connection

15V

LT1103

VSW

LT1103 TA03

LT1105 FET Connection

15V

LT1105 VSW

ILIM

LT1103 TA04

Rev. F

For more information LT1103/LT1105 25

LT1103/LT1105
TYPICAL APPLICATIONS
Setting Oscillator Frequency Setting Overvoltage Lockout

OVLOTH

R2
LT1105
LT1103/LT1105 OVLO

R1
OSC

COSC LT1103 TA09

LT1103 TA05
CHOOSE OVLOTH
CHOOSE 20kHz ≤ fOSC ≤ 200kHz LET R1 = 5k
COSC = SF =
fOSC
I
∆V fOSC
=
100µA
( )(
2.5V fOSC ) ( )( ) R2 = ( OVLOTH
2.5V )
–1 R1

DC ≅ 0.66 ⇒ 66%

Decreasing Oscillator Increasing Oscillator Synchronizing Oscillator Frequency

Maximum Duty Cycle Maximum Duty Cycle to an External Clock

5V
LT1105 LT1103/LT1105 LT1103/LT1105
500ns

OSC OSC 5V OSC

1µF
1:0.5 COSC
COSC R I1 0V
COSC R I1
LT1103 TA07
LT1103 TA08

LT1103 TA06

CHOOSE 0 ≤ DC ≤ 0.66
CHOOSE 0.66 ≤ DC ≤ 1.0
(6 – 9DC)
SOLVE FOR X ⇒ X = (9DC – 6)
2 SOLVE FOR X ⇒ X = ISOLATION
2
0≤X≤3 BOUNDARY
0 ≤ X ≤ 1.5

⇒ I1 = X • I = X • 100µA
⇒ I1 = X • I = X • 100µA

⇒ R = 1.75V 3.25V
I1 ⇒R=
I1
COSC = 100µA • 1+ (
3X – 2X
2
) 100µA (
3X + 2X
2
)
COSC = • 1–
( )(
2.5V fOSC ) 9
( )(
2.5V fOSC ) 9

Rev. F

26 For more information LT1103/LT1105

 LT1103/LT1105
TYPICAL APPLICATIONS
LT1103 Ground Connections

15V
VIN SWITCH CURRENT PATH
KEEP RESISTANCE LOW
OSC
GND
VC
FB
VSW

LT1103 TA11a

TO BIAS
WINDING OUTPUT GND

SEPARATE
GROUND PATH

SWITCH CURRENT PATH

KEEP RESISTANCE LOW
15V
VIN
OSC
GND
VC
FB
VSW

LT1103 TA11b

TO BIAS GND
WINDING OUTPUT

LT1105 Ground Connections

HIGH CURRENT
GROUND PATH
GND VSW
ILIM

FB VIN

VC

TO BIAS
LT1103 TA12a
WINDING
OUTPUT

Rev. F

For more information LT1103/LT1105 27

LT1103/LT1105
PACKAGE DESCRIPTION
N Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510 Rev I)

.400*
(10.160)
MAX

8 7 6 5

.255 ±.015*
(6.477 ±0.381)

1 2 3 4

.300 – .325 .045 – .065 .130 ±.005

(7.620 – 8.255) (1.143 – 1.651) (3.302 ±0.127)

.065
(1.651)
.008 – .015 TYP
(0.203 – 0.381) .120
(3.048) .020
+.035 MIN (0.508)
.325 –.015
MIN

( )
.100 .018 ±.003
+0.889 (2.54)
8.255 (0.457 ±0.076) N8 REV I 0711
–0.381
BSC
NOTE:
INCHES
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

Rev. F

28 For more information LT1103/LT1105

 LT1103/LT1105
PACKAGE DESCRIPTION
N Package
14-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510 Rev I)

.770*
(19.558)
MAX
14 13 12 11 10 9 8

.255 ±.015*
(6.477 ±0.381)

1 2 3 4 5 6 7

.300 – .325 .130 ±.005 .045 – .065

(7.620 – 8.255) (3.302 ±0.127) (1.143 – 1.651)

.020
(0.508)
MIN .065
.008 – .015 (1.651)
(0.203 – 0.381) TYP

+.035
.325 –.015 .005
.120 .018 ±.003

(8.255
+0.889
–0.381 ) (3.048)
MIN
(0.127) .100
MIN (2.54)
BSC
(0.457 ±0.076)
N14 REV I 0711

NOTE:
INCHES
1. DIMENSIONS ARE
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

Rev. F

For more information LT1103/LT1105 29

LT1103/LT1105
PACKAGE DESCRIPTION

T7 Package
7-Lead Plastic TO-220 (Standard)
(Reference LTC DWG # 05-08-1422)

.147 – .155 .165 – .180

.390 – .415 (3.734 – 3.937) (4.191 – 4.572) .045 – .055
(9.906 – 10.541) DIA (1.143 – 1.397)

.230 – .270
(5.842 – 6.858)
.570 – .620
.620
.460 – .500 (14.478 – 15.748)
(15.75)
(11.684 – 12.700) TYP
.330 – .370
.700 – .728
(8.382 – 9.398)
(17.780 – 18.491)

SEATING PLANE .095 – .115

(2.413 – 2.921)
.152 – .202
.155 – .195*
.260 – .320 (3.860 – 5.130) (3.937 – 4.953)
(6.604 – 8.128)

.050 .026 – .036 .013 – .023

BSC (0.330 – 0.584)
(1.27) (0.660 – 0.914) .135 – .165
(3.429 – 4.191) *MEASURED AT THE SEATING PLANE
T7 (TO-220) 0801

OBSOLETE PACKAGE

Rev. F

30 For more information LT1103/LT1105

 LT1103/LT1105
REVISION HISTORY (Revision history begins at Rev E)

REV DATE DESCRIPTION PAGE NUMBER

E 12/18 Reflects LT1103 being obsolete and the LT1105 being available. All
F 11/22 Updated Order Information table. 3

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license isFor morebyinformation
granted implication orLT1103/LT1105
otherwise under any patent or patent rights of Analog Devices. 31
LT1103/LT1105
TYPICAL APPLICATION
Minimum Parts Count Fully-Isolated Flyback 100kHz 50W Converter
OPTIONAL OUTPUT FILTER
85VAC TO 270VAC MBR2045 10µH
5V
1.5KE300A 10A
!! + +
+
GER GE!!
5W

+
220k
D A N A
35V 50V

OLT
1W MUR150 3600µF 470µF
220µF
H V
385V
499Ω HIG
*OUTPUT CAPACITOR IS THREE 1200µF,
– 50V CAPACITORS IN PARALLEL TO
1000pF 1N4148 ACHIEVE REQUIRED RIPPLE CURRENT
100Ω RATING AND LOW ESR.
BRIDGE
RECTIFIER
+ BAV21 WINDINGS FOR
LINE BUK426-800A OPTIONAL
FILTER BAV21 VIN VSW ±12VDC OUTPUTS

39µF
+
16.2k LT1103
1% 25V 10Ω
TRANSFORMER DATA:
FB 15V COILTRONICS - CTX110228-3
+ L(PRI) = 1.6mH
5.36k GND VC OSC 1µF NPRI:NSEC = 1:0.05
1% 25V NBIAS:NSEC = 1:0.27
390pF
330Ω

0.047µF 0.1µF
LT1103 TA01

Danger!! Lethal Voltages Present – See Text

Load Regulation
5.25
5.20
5.15
5.10 270VAC
5.05 220VAC
VOUT (V)

5.00
4.95 110VAC
4.90
85VAC
4.85
4.80
4.75
0 1 2 3 4 5 6 7 8 9 10
IOUT (A)
LT1103 TA14

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Rev. F

32
11/22
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