BCA II/B.Sc.

(IT) II
Digital Electronics
TBC 204/TBI 202

Jaishankar Bhatt
Assistant Professor
Graphic Era Deemed to be University

Dehradun
Graphic Era Deemed to be University
1
Dehradun
 Unit 3
Topic Name – Combinational Circuits
Table of Contents
• Adders
• Subtractors
• Decoders
• Encoders
• Multiplexer and Demultiplexer
• Binary Adder/Subtractor
• References

Graphic Era Deemed to be University

2
Dehradun
Digital Circuit and its type: A digital circuit is a type of circuit that operates on
different logic gates. A digital circuit comprises various components each of which
is used to perform a specific task. In a digital circuit the signal must be one of two
discrete levels. Each level is interpreted as one of two different states (for example,
on/off, 0/1, true/false).
A digital circuit is designed by using a number of logic gates on a single Integrated
Circuit – IC. The input to any digital circuit is in the binary form “0’s” and “1’s”. The
output obtained on processing raw digital data is of a precise value. These circuits
can be represented in two ways which are as follows.
1. Combinational Circuits
2. Sequential Circuits

Graphic Era Deemed to be University

3
Dehradun
1. Combinational Circuit: - The combinational circuit is made up of logic gates
whose output is determined by the present input only. It is realized by various
logic gates like AND, OR, NOT, NAND, NOR etc. Various types of combinational
circuits are as follows.
1. Adders
1.1 Half Adders
1.2 Full Adders
2. Subtractors
2.1 Half Subtractors
2.2 Full Subtractors
3. Decoders
4. Encoders
5. Multiplexers
6. Demultiplexers
Graphic Era Deemed to be University
4
Dehradun
Graphic Era Deemed to be University
5
Dehradun
1. Adders : An adder is a digital logic circuit which is extensively used for the
addition of binary numbers.
1.1 Half Adders : - Half adder is a combinational circuit , which is used to add
two binary bits. It requires two binary inputs and two binary outputs sum and
carry respectively.
Where, Sum = x’y + xy’ and Carry = xy

Graphic Era Deemed to be University

6
Dehradun
Graphic Era Deemed to be University
7
Dehradun
Graphic Era Deemed to be University
8
Dehradun
1. Adders
1.2 Full Adders: - Full adder is a combinational circuit , which is used to add
three binary bits. It requires three binary inputs and two binary outputs sum and
carry respectively.
Truth table for full adder is as follow

Graphic Era Deemed to be University

9
Dehradun
Graphic Era Deemed to be University
10
Dehradun
Graphic Era Deemed to be University
11
Dehradun
2. Subtractors: - Subtractor is used to subtract two or more binary bits.
2.1 Half Subtractors: - The half-subtractor is a combinational circuit which is used
to perform subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend)
and two outputs D (difference) and Bout (borrow out).
Where, Difference (D) = x’y + xy’ and Borrow (B) = x’y
Truth table of half subtractor is as follows.

Graphic Era Deemed to be University

12
Dehradun
Boolean expressions for difference (D) and Borrow out (B) can be written as follows:
D = X’Y + XY’ or D = X Y
B = X’Y
The logic diagram of half adders is given below.

Graphic Era Deemed to be University

13
Dehradun
2.2 Full Subtractor: - Full subtractor is a combinational circuit that performs
subtraction of three binary bits. The truth table of the full adders is as follows.

Graphic Era Deemed to be University

14
Dehradun
Graphic Era Deemed to be University
15
Dehradun
Logic Diagram of Full Subtractor

Graphic Era Deemed to be University

16
Dehradun
Decoder: - Discrete quantities of information are represented in digital systems
by binary codes. A binary code of n bits is capable of representing up to 2n
distinct elements of coded information. A decoder is a combinational circuit that
converts binary information from n input lines to a maximum of 2n unique
output lines. If the n -bit coded information has unused combinations, the
decoder may have fewer than 2n outputs.

Graphic Era Deemed to be University

17
Dehradun
Graphic Era Deemed to be University
18
Dehradun
Graphic Era Deemed to be University
19
Dehradun
3X8 Decoder using two 2X4 Decoders: - Decoders with enable inputs can be
connected together to form a larger decoder. shows two 3-to-8-line decoders with
enable inputs connected to form a 4-to-16-line decoder. When E = 0, the top decoder
is enabled and the other is disabled. The bottom decoder outputs are all 0’s, and the
top four outputs generate minterms 000 to 011. When E = 1, the enable conditions are
reversed: The bottom decoder outputs generate minterms 100 to 111, while the
outputs of the top decoder are all 0’s.

Graphic Era Deemed to be University

20
Dehradun
Graphic Era Deemed to be University
21
Dehradun
Encoder:- An encoder is a digital circuit that performs the inverse operation of a
decoder. An encoder has 2n input lines and n output lines. The output lines, as an
aggregate, generate the binary code corresponding to the input value.
An example of an encoder is the octal-to-binary encoder. It has eight inputs (one for
each of the octal digits) and three outputs that generate the corresponding binary
number. It is assumed that only one input has a value of 1 at any given time.

Graphic Era Deemed to be University

22
Dehradun
The encoder can be implemented with OR gates whose inputs are determined directly
from the truth table. Output z is equal to 1 when the input octal digit is 1, 3, 5, or 7.
Output y is 1 for octal digits 2, 3, 6, or 7, and output x is 1 for digits 4, 5, 6, or 7. These
conditions can be expressed by the following Boolean output functions:
X = D4 +D5 + D6 + D7
Y = D2 + D3 + D6 + D7
Z = D1 + D3 + D5 + D
The encoder can be implemented with three OR gates.

Graphic Era Deemed to be University

23
Dehradun
Graphic Era Deemed to be University
24
Dehradun
Multiplexer: - A multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it to a
single output line. In other words it receives 2n input lines and
produces only one output line. The selection of a particular input
line is controlled by a set of selection lines. Normally, there are 2n
input lines and n selection lines whose bit combinations determine
which input is selected.
Multiplexers are also known as “Data selector, or many to one
device. Multiplexers are mainly used to increase amount of the data
that can be sent over the network within certain amount of time and
bandwidth.
 Fig. Block Diagram of a 4X1 multiplexer
I0, I1, I2 and I3 are inputs and Y is output. S0 and S1 are selection lines.
Output may be I0, I1, I2 or I3, it depends on the combination of selection
lines S0 and S1
 Truth Table of a 4X1 multiplexer

When the selection lines S0 and S1 are 0,0 the multiplexer will produce
I0 as output and when selection lines are (0,1) , (1,0) or (1,1) it will
produce output I1 , I2 or I3 respectively.
Logic diagram of 4X1 multiplexer
 Cascading of multiplexers
Cascading refers a process where a large multiplexer can be designed or
implemented using smaller multiplexers.
In this section, let us implement 8x1 Multiplexer using two 4x1
Multiplexers and one 2x1 Multiplexer. We know that 4x1 Multiplexer has
4 data inputs, 2 selection lines and one output. Whereas, 8x1
Multiplexer has 8 data inputs, 3 selection lines and one output.
So, we require two 4x1 Multiplexers in first stage in order to get the 8
data inputs. Since, each 4x1 Multiplexer produces one output, we
require a 2x1 Multiplexer in second stage by considering the outputs of
first stage as inputs and to produce the final output.
Designing of a 8X1 multiplexer using two 4X1 and one 2X1 multiplexer
Description of the diagram
The same selection lines, s1 & s0 are applied to both 4x1 Multiplexers. The data
inputs of upper 4x1 Multiplexer are I0 to I3 and the data inputs of lower 4x1
Multiplexer are I4 to I7. Therefore, each 4x1 Multiplexer produces an output
based on the values of selection lines, s1 & s0.
The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1
Multiplexer that is present in second stage. The other selection line, s2 is applied
to 2x1 Multiplexer.
• If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs
I3 to I0 based on the values of selection lines s1 & s0.
• If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I7 to
I4 based on the values of selection lines s1 & s0.
Therefore, the overall combination of two 4x1 Multiplexers and one 2x1
Multiplexer performs as one 8x1 Multiplexer.
Truth Table of a 4X1 multiplexer
Demultiplexer: - Demultiplexer is a combinational circuit. These are
also called data distributors or ‘one to many’ device. A
demultiplexer (abbreviated as DMUX) performs the reverse or
opposite operation of a multiplexer. That is, it takes a single input
and distributes it over several outputs.
In a multiplexer there are 2n output lines, n selection lines and only
one input line. The role of selection lines is to select one output
line from the 2n output lines. Demultiplexer provides its input data
a specific direction to flow through.

Graphic Era Deemed to be University

34
Dehradun
Types of Demultiplexer: - Common types of demultiplexers are as
follows.
• 1X2 Demultiplexer (1 Selection Line)
• 1X4 Demultiplexer (2 Selection Lines)
• 1X8 Demultiplexer (3 Selection Lines)
• 1X16 Demultiplexer (4 Selection Lines)
• 1X32 Demultiplexer (5 Selection Lines)

Graphic Era Deemed to be University

35
Dehradun
Applications of Demultiplexer: -
• Demultiplexer is used to connect a single source to multiple
destinations.
• Communication systems – Generally multiplexer and demultiplexer are
used together, because communicational systems are bi directional.
Communication system use multiplexer to carry multiple data like audio,
video and other form of data using a single line for transmission, on the
other hand demultiplexer is used to distribute the single data line into
multiple data lines.
• Security monitoring Systems
• Synchronous data transmission

Graphic Era Deemed to be University

36
Dehradun
Block Diagram of a Demultiplexer

Graphic Era Deemed to be University

37
Dehradun
Block Diagram of a 1X4 Demultiplexer

Graphic Era Deemed to be University

Dehradun
Truth Table of a 1X4 Demultiplexer

Graphic Era Deemed to be University

39
Dehradun
Logic Diagram of a 1X4 Demultiplexer

Graphic Era Deemed to be University

40
Dehradun
Example of Demultiplexing Process

Graphic Era Deemed to be University

41
Dehradun
Binary Adder-Subtractor: -
The addition and subtraction operations can be combined into one common
circuit by including an exclusive-OR gate with each full-adder.
Following logic operation is applied in binary adder subtractor
Exclusive - OR (XOR): - The 'Exclusive-OR' gate is a circuit which will give a high
output if either, but not both, of its two inputs are high. An encircled plus sign ()
is used to show the EOR operation.
Algebraic function of XOR gate is X= A’ B + AB’

Graphic Era Deemed to be University

42
Dehradun
Binary Adder-Subtractor

Graphic Era Deemed to be University

43
Dehradun
Description of binary adder subtractor: - When M = 0 the circuit is an adder and
when M = 1 the circuit becomes a subtractor. Each exclusive-OR gate receives input
M and one of the inputs of B. When M = 0, we have B EXOR 0 = B. The full-adders
receive the value of B, the input carry is O, and the circuit performs A plus B . When
M = 1, we have B EXOR 1 = B' and C0 = 1. The B inputs are all complemented and a
1 is added through the input carry. The circuit performs the operation A plus the
2's complement of B.

Graphic Era Deemed to be University

44
Dehradun
References
1. Digital Design: Mano M, Pearson Education.
2. Digital principle and applications: Leach Malvino, McGraw Hill
Company.
3. Modern digital Electronics: R.P. Jain, McGraw Hill Higher education
4. Digital Circuit and Design: S. Salivahanan, Oxford Publications

Graphic Era Deemed to be University

45
Dehradun