SPC560B54x, SPC560B60x,

SPC560B64x
32-bit MCU family built on the Power Architecture® for automotive
body electronics applications
Datasheet - production data

 Dedicated diagnostic module for lighting

– Advanced PWM generation
– Time-triggered diagnostics
LQFP100 LQFP144 LQFP176 – PWM-synchronized ADC measurements
(14 x 14 x 1.4 mm) (20 x 20 x 1.4 mm) (24 x 24 x 1.4 mm)  On-chip CAN/UART bootstrap loader
 Communications interfaces
Features – Up to 6 FlexCAN (2.0B active) with 64
message buffers each
 High performance 64 MHz e200z0h CPU – Up to 10 LINFlex/UART channels
– 32-bit Power Architecture® technology – Up to 6 buffered DSPI channels
CPU – I2C interface
– Up to 60 DMIPs operation  Clock generation
– Variable length encoding (VLE)
–4 to 16 MHz fast external crystal oscillator
 Memory
–32 kHz slow external crystal oscillator
– Up to 1.5 MB on-chip Code Flash with ECC –16 MHz fast internal RC oscillator
– 64 KB on-chip Data Flash with ECC –128 kHz slow internal RC oscillator for low-
– Up to 96 KB on-chip SRAM with ECC power modes
– 8-entry MPU – Software-controlled FMPLL
 Interrupts – Clock monitoring unit
– 16 priority levels  Low-power capabilities
– Non-maskable interrupt (NMI) – Several low-power mode configurations
– Up to 51 external interrupts lines including – Ultra-low-power standby with RTC and
27 wake-up lines communication
 16-channel eDMA (linked to PITs, DSPI, – Fast wakeup schemes
ADCs, eMIOS, LINFlex and I2C)  Exhaustive debugging capability
 GPIOs: 77 (LQFP100), 121 (LQFP144) and – Nexus 2+ interface on LBGA208 package
149 (LQFP176) – Nexus 1 on all packages
 Timer units  Voltage supply
– 8-channel 32-bit periodic interrupt timer – Single 5 V or 3.3 V supply
– 4-channel 32-bit system timer – On-chip voltage regulator
– System watchdog timer – External ballast resistor support
– Real-time clock timer  LQFP100, LQFP144, and LQFP176 packages;
 eMIOS, 16-bit counter timed I/O units LBGA208 package for Nexus2+
– Up to 64 channels with PWM/MC/IC/OC  Operating temperature range -40 to 125 °C
– Up to 10 counter basis
– ADC diagnostic trigger via CTU Table 1. Device summary
 One 10-bit and one 12-bit ADC with up to 53 768 KByte 1 MByte 1.5 MByte
channels Package
Code Flash Code Flash Code Flash
– Extendable to 81 channels LQFP176 — SPC560B60L7 SPC560B64L7
– Individual conversion registers LQFP144 SPC560B54L5 SPC560B60L5 SPC560B64L5
 Cross triggering unit (CTU) LQFP100 SPC560B54L3 SPC560B60L3 SPC560B64L3

January 2016 DocID15131 Rev 9 1/133

This is information on a product in full production. www.st.com
Contents SPC560B54x/6x

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Pad configuration during reset phases . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Pad configuration during standby mode exit . . . . . . . . . . . . . . . . . . . . . . 17
3.4 Voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7 Functional port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.8 Nexus 2+ pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.1 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.1 NVUSRO[PAD3V5V] field description . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2.2 NVUSRO[OSCILLATOR_MARGIN] field description . . . . . . . . . . . . . . . 57
4.2.3 NVUSRO[WATCHDOG_EN] field description . . . . . . . . . . . . . . . . . . . . 57
4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.4 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.5.1 External ballast resistor recommendations . . . . . . . . . . . . . . . . . . . . . . 61
4.5.2 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.5.3 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.6 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.6.1 I/O pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.6.2 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.6.3 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.6.4 Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

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SPC560B54x/6x Contents

4.6.5 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.7 RESET electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.8 Power management electrical characteristics . . . . . . . . . . . . . . . . . . . . . 79
4.8.1 Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 79
4.8.2 Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . 81
4.9 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.10 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.10.1 Program/erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.10.2 Flash power supply DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.10.3 Start-up/Switch-off timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.11 Electromagnetic compatibility (EMC) characteristics . . . . . . . . . . . . . . . . 86
4.11.1 Designing hardened software to avoid noise problems . . . . . . . . . . . . . 86
4.11.2 Electromagnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.11.3 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 87
4.12 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . 88
4.13 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . 91
4.14 FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.15 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . 94
4.16 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . 95
4.17 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.17.2 Input impedance and ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.17.3 ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.18 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.18.1 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.18.2 DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.18.3 Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.18.4 JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

5 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

5.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
5.2.1 LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
5.2.2 LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
5.2.3 LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

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Contents SPC560B54x/6x

5.2.4 LBGA208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Appendix A Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

4/133 DocID15131 Rev 9

SPC560B54x/6x List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. SPC560B54/6x family comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. SPC560B54/6x series block summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Voltage supply pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. System pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Functional port pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Nexus 2+ pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 8. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 9. PAD3V5V field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 10. OSCILLATOR_MARGIN field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 11. WATCHDOG_EN field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 12. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 13. Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 14. Recommended operating conditions (5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 15. LQFP thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 16. I/O input DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 17. I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 18. SLOW configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 19. MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 66
Table 20. FAST configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 21. Output pin transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 22. I/O supply segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 23. I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 24. I/O weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 25. Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 26. Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 27. Low voltage detector electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 28. Power consumption on VDD_BV and VDD_HV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 29. Program and erase specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 30. Flash module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 31. Flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 32. Flash power supply DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 33. Start-up time/Switch-off time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 34. EMI radiated emission measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 35. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 36. Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 37. Crystal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 38. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics. . . . . . . . . . . . . . . . 90
Table 39. Crystal motional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 40. Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . 93
Table 41. FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 42. Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 94
Table 43. Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . 95
Table 44. ADC input leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 45. ADC_0 conversion characteristics (10-bit ADC_0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 46. ADC_1 conversion characteristics (12-bit ADC_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 47. On-chip peripherals current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 48. DSPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

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List of tables SPC560B54x/6x

Table 49. Nexus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 50. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 51. LQFP176 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 52. LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 53. LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 54. LBGA208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 55. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 56. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

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SPC560B54x/6x List of figures

List of figures

Figure 1. SPC560B54/6x block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2. LQFP176 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. LQFP144 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. LQFP100 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. LBGA208 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 7. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 8. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 9. Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 10. Low voltage detector vs reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 11. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 12. Fast external crystal oscillator (4 to 16 MHz) timing diagram . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 13. Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 14. Equivalent circuit of a quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 15. Slow external crystal oscillator (32 kHz) timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 16. ADC_0 characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 17. Input equivalent circuit (precise channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 18. Input equivalent circuit (extended channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 19. Transient behavior during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 20. Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 21. ADC_1 characteristic and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 22. DSPI classic SPI timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 23. DSPI classic SPI timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 24. DSPI classic SPI timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 25. DSPI classic SPI timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 26. DSPI modified transfer format timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 27. DSPI modified transfer format timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 28. DSPI modified transfer format timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 29. DSPI modified transfer format timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 30. DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 31. Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 32. Timing diagram — JTAG boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 33. LQFP176 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 34. LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 35. LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 36. LBGA208 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 37. Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

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7
Introduction SPC560B54x/6x

1 Introduction

1.1 Document overview

This document describes the features of the family and options available within the family
members, and highlights important electrical and physical characteristics of the device.

1.2 Description
This family of 32-bit system-on-chip (SoC) microcontrollers is the latest achievement in
integrated automotive application controllers. It belongs to an expanding family of
automotive-focused products designed to address the next wave of body electronics
applications within the vehicle.
The advanced and cost-efficient e200z0h host processor core of this automotive controller
family complies with the Power Architecture technology and only implements the VLE
(variable-length encoding) APU (Auxiliary Processor Unit), providing improved code density.
It operates at speeds of up to 64 MHz and offers high performance processing optimized for
low power consumption. It capitalizes on the available development infrastructure of current
Power Architecture devices and is supported with software drivers, operating systems and
configuration code to assist with users implementations.

Table 2. SPC560B54/6x family comparison(1)

Feature SPC560B54 SPC560B60 SPC560B64

CPU e200z0h
Execution speed(2) Up to 64 MHz
Code flash memory 768 KB 1 MB 1.5 MB
Data flash memory 64 (4  16) KB
SRAM 64 KB 80 KB 96 KB
MPU 8-entry
eDMA 16 ch
10-bit ADC Yes
(3)
dedicated 7 ch 15 ch 7 ch 15 ch 29 ch 7 ch 15 ch 29 ch 29 ch
shared with 12-bit ADC 19 ch
12-bit ADC Yes
(4)
dedicated 5 ch
shared with 10-bit ADC 19 ch
37 ch, 64 ch, 37 ch, 64 ch, 64 ch, 37 ch, 64 ch,1 64 ch, 64 ch,
Total timer I/O(5) eMIOS
16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 6-bit 16-bit 16-bit
Counter / OPWM / ICOC(6) 10 ch
O(I)PWM / OPWFMB /
7 ch
OPWMCB / ICOC(7)
O(I)PWM / ICOC(8) 7 ch 14 ch 7 ch 14 ch 14 ch 7 ch 14 ch 14 ch 14 ch

8/133 DocID15131 Rev 9

SPC560B54x/6x Introduction

Table 2. SPC560B54/6x family comparison(1) (continued)

Feature SPC560B54 SPC560B60 SPC560B64
(9)
OPWM / ICOC 13 ch 33 ch 13 ch 33 ch 33 ch 13 ch 33 ch 33 ch 33 ch
SCI (LINFlex) 4 8 4 8 10 4 8 10 10
SPI (DSPI) 3 5 3 5 6 3 5 6 6
CAN (FlexCAN) 6
I2C 1
32 KHz oscillator Yes
(10)
GPIO 77 121 77 121 149 77 121 149 149
Debug JTAG N2+
LQFP LQFP LQFP LQFP LQFP LQFP LQFP LQFP
Package LBGA208(11)
100 144 100 144 176 100 144 176
1. Feature set dependent on selected peripheral multiplexing; table shows example.
2. Based on 125 C ambient operating temperature.
3. Not shared with 12-bit ADC, but possibly shared with other alternate functions.
4. Not shared with 10-bit ADC, but possibly shared with other alternate functions.
5. See the eMIOS section of the chip reference manual for information on the channel configuration and functions.
6. Each channel supports a range of modes including Modulus counters, PWM generation, Input Capture, Output Compare.
7. Each channel supports a range of modes including PWM generation with dead time, Input Capture, Output Compare.
8. Each channel supports a range of modes including PWM generation, Input Capture, Output Compare, Period and Pulse
width measurement.
9. Each channel supports a range of modes including PWM generation, Input Capture, and Output Compare.
10. Maximum I/O count based on multiplexing with peripherals.
11. LBGA208 available only as development package for Nexus2+.

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132
Block diagram SPC560B54x/6x

2 Block diagram

Figure 1 shows a top-level block diagram of the SPC560B54/6x.

Figure 1. SPC560B54/6x block diagram

eDMA SRAM Code Flash Data Flash

JTAG
96 KB 1.5 MB 64 KB
JTAG Port (Master)

Instructions

64-bit 2  3 Crossbar Switch

Nexus Port SRAM
e200z0h (Master) Flash
Nexus Controller Controller

Data
NMI

MPU
Nexus 2+ (Slave)
(Master) (Slave)
SIUL
Voltage
Regulator Interrupt
Interrupt requests request with
NMI from peripheral (Slave) wakeup
blocks functionality
MPU
INTC Registers WKPU
Clocks CMU
FMPLL

RTC STM SWT ECSM PIT MC_RGM MC_CGM MC_ME MC_PCU BAM SSCM

Peripheral Bridge

SIUL 19 ch 10-bit/12-bit 29 ch 10-bit 64 ch 10  6 6

Reset Control ADC ADC
CTU eMIOS LINFlex DSPI I2C FlexCAN
Interrupt
Request External
Interrupt
Request
5 ch 12-bit
IMUX ADC
GPIO &
Pad Control

... ... ... ... ...

I/O
Legend: LINFlex Serial Communication Interface (LIN support)

ADC Analog-to-Digital Converter MC_CGM Clock Generation Module
BAM Boot Assist Module MC_ME Mode Entry Module
CMU Clock Monitor Unit MC_PCU Power Control Unit
CTU Cross Triggering Unit MC_RGM Reset Generation Module
DSPIDeserial Serial Peripheral Interface MPU Memory Protection Unit
ECSM Error Correction Status Module NMI Non-Maskable Interrupt
eDMA Enhanced Direct Memory Access PIT Periodic Interrupt Timer
eMIOS Enhanced Modular Input Output System RTC Real-Time Clock
Flash Flash memory SIUL System Integration Unit Lite
FlexCAN Controller Area Network SRAM Static Random-Access Memory
FMPLL Frequency-Modulated Phase-Locked Loop SSCM System Status Configuration Module
GPIO General-purpose input/output STM System Timer Module
I2C Inter-Integrated Circuit bus SWT Software Watchdog Timer
IMUX Internal Multiplexer VREG Voltage regulator
INTC Interrupt Controller WKPU Wakeup Unit
JTAG JTAG controller XBAR Crossbar switch

10/133 DocID15131 Rev 9

SPC560B54x/6x Block diagram

Table 3 summarizes the functions of the blocks present on the SPC560B54/6x.

Table 3. SPC560B54/6x series block summary

Block Function

Analog-to-digital converter
Converts analog voltages to digital values
(ADC)
A block of read-only memory containing VLE code which is executed according
Boot assist module (BAM)
to the boot mode of the device
Clock generation module Provides logic and control required for the generation of system and peripheral
(MC_CGM) clocks
Clock monitor unit (CMU) Monitors clock source (internal and external) integrity
Enables synchronization of ADC conversions with a timer event from the eMIOS
Cross triggering unit (CTU)
or from the PIT
Supports simultaneous connections between two master ports and three slave
Crossbar switch (XBAR) ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width.
Deserial serial peripheral
Provides a synchronous serial interface for communication with external devices
interface (DSPI)
Enhanced direct memory Performs complex data transfers with minimal intervention from a host processor
access (eDMA) via “n” programmable channels
Enhanced modular input output
Provides the functionality to generate or measure events
system (eMIOS)
Provides a myriad of miscellaneous control functions for the device including
Error correction status module program-visible information about configuration and revision levels, a reset status
(ECSM) register, wakeup control for exiting sleep modes, and optional features such as
information on memory errors reported by error-correcting codes
Flash memory Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area
Supports the standard CAN communications protocol
network)
Frequency-modulated phase- Generates high-speed system clocks and supports programmable frequency
locked loop (FMPLL) modulation
Two-wire bidirectional serial bus that provides a simple and efficient method of
Inter-integrated circuit (I2C) bus
data exchange between devices
Internal multiplexer (IMUX) SIU
Allows flexible mapping of peripheral interface on the different pins of the device
subblock
Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests
Provides the means to test chip functionality and connectivity while remaining
JTAG controller (JTAGC)
transparent to system logic when not in test mode
Manages a high number of LIN (Local Interconnect Network protocol) messages
LINFlex controller
efficiently with a minimum of CPU load
Provides hardware access control for all memory references generated in a
Memory protection unit (MPU)
device

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132
Block diagram SPC560B54x/6x

Table 3. SPC560B54/6x series block summary (continued)

Block Function

Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control unit,
Mode entry module (MC_ME)
reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Handles external events that must produce an immediate response, such as
Non-maskable interrupt (NMI)
power down detection
Periodic interrupt timer (PIT) Produces periodic interrupts and triggers
Reduces the overall power consumption by disconnecting parts of the device
Power control unit (MC_PCU) from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
A free running counter used for time keeping applications, the RTC can be
Real-time counter (RTC) configured to generate an interrupt at a predefined interval independent of the
mode of operation (run mode or low-power mode)
Reset generation module
Centralizes reset sources and manages the device reset sequence of the device
(MC_RGM)
Static random-access memory
Provides storage for program code, constants, and variables
(SRAM)
Provides control over all the electrical pad controls and up 32 ports with 16 bits of
System integration unit lite
bidirectional, general-purpose input and output signals and supports up to 32
(SIUL)
external interrupts with trigger event configuration
Provides system configuration and status data (such as memory size and status,
System status and configuration
device mode and security status), device identification data, debug status port
module (SSCM)
enable and selection, and bus and peripheral abort enable/disable
Provides a set of output compare events to support AUTOSAR (Automotive
System timer module (STM)
Open System Architecture) and operating system tasks
Software watchdog timer (SWT) Provides protection from runaway code
The wakeup unit supports up to 27 external sources that can generate interrupts
Wakeup unit (WKPU) or wakeup events, of which 1 can cause non-maskable interrupt requests or
wakeup events.

12/133 DocID15131 Rev 9

SPC560B54x/6x Package pinouts and signal descriptions

3 Package pinouts and signal descriptions

3.1 Package pinouts

The available LQFP pinouts and the ballmap are provided in the following figures. For pin
signal descriptions, please see Table 6.

Figure 2 shows the SPC560B54/6x in the LQFP176 package.

Figure 2. LQFP176 pin configuration

VDD_HV
VSS_HV
VDD_LV
VSS_LV

PG[10]

PG[15]
PG[14]
PC[13]
PC[12]

PH[10]

PH[12]
PG[11]

PE[15]
PE[14]

PE[12]
PH[11]
PC[8]

PH[8]
PH[7]
PH[6]
PH[5]
PH[4]

PC[4]
PC[5]

PH[9]
PC[0]

PC[1]

PC[2]
PC[3]
PB[2]

PE[7]
PE[6]

PE[5]
PE[4]

PE[3]
PE[2]

PA[6]
PA[5]
PI[0]
PI[1]
PI[2]
PI[3]

PI[4]
PI[5]
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
PB[3] 1
PC[9] 2 132 PA[11]
PC[14] 3 131 PA[10]
PC[15] 4 130 PA[9]
PJ[4] 5 129 PA[8]
VDD_HV 6 128 PA[7]
VSS_HV 7 127 PE[13]
PH[15] 8 126 PF[14]
PH[13] 9 125 PF[15]
PH[14] 10 124 VDD_HV
PI[6] 11 123 VSS_HV
PI[7] 12 122 PG[0]
PG[5] 13 121 PG[1]
PG[4] 14 120 PH[3]
PG[3] 15 119 PH[2]
PG[2] 16 118 PH[1]
PA[2] 17 117 PH[0]
PE[0] 18 116 PG[12]
PA[1] 19 115 PG[13]
PE[1] 20 114 PA[3]
PE[8] 21 113 PI[13]
PE[9] 22 112 PI[12]
PE[10] 23
LQFP176 111 PI[11]
PA[0] 24 110 PI[10]
PE[11] 25 Top view 109 PI[9]
VSS_HV 26 108 PI[8]
VDD_HV 27 107 PB[15]
VSS_HV 28 106 PD[15]
RESET 29 105 PB[14]
VSS_LV 30 104 PD[14]
VDD_LV 31 103 PB[13]
VDD_BV 32 102 PD[13]
PG[9] 33 101 PB[12]
PG[8] 34 100 PD[12]
PC[11] 35 99 VDD_HV_ADC1
PC[10] 36 98 VSS_HV_ADC1
PG[7] 37 97 PB[11]
PG[6] 38 96 PD[11]
PB[0] 39 95 PD[10]
PB[1] 40 94 PD[9]
PF[9] 41 93 PB[7]
PF[8] 42 92 PB[6]
PF[12] 43 91 PB[5]
PC[6] 44 90 VDD_HV_ADC0
89 VSS_HV_ADC0
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VDD_LV
PF[10]

PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PJ[3]
PJ[2]
PJ[1]
PJ[0]
PI[15]
PI[14]

PB[4]
PC[7]

PF[11]
PA[15]
PF[13]
PA[14]
PA[4]
PA[13]
PA[12]
VSS_LV

PB[9]
PB[8]
PB[10]
PF[0]
XTAL
EXTAL

PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]

PD[8]
VSS_HV

VDD_HV

VDD_HV
VSS_HV

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132
Package pinouts and signal descriptions SPC560B54x/6x

Figure 3 shows the SPC560B54/6x in the LQFP144 package.

Figure 3. LQFP144 pin configuration

VDD_HV
VSS_HV
VDD_LV
VSS_LV

PG[10]

PG[15]
PG[14]
PC[13]
PC[12]

PH[10]

PG[11]

PE[15]
PE[14]

PE[12]
PC[8]

PH[8]
PH[7]
PH[6]
PH[5]
PH[4]

PC[4]
PC[5]

PH[9]
PC[0]

PC[1]

PC[2]
PC[3]
PB[2]

PE[7]
PE[6]

PE[5]
PE[4]

PE[3]
PE[2]

PA[6]
PA[5]
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PB[3] 1 108 PA[11]
PC[9] 2 107 PA[10]
PC[14] 3 106 PA[9]
PC[15] 4 105 PA[8]
PG[5] 5 104 PA[7]
PG[4] 6 103 PE[13]
PG[3] 7 102 PF[14]
PG[2] 8 101 PF[15]
PA[2] 9 100 VDD_HV
PE[0] 10 99 VSS_HV
PA[1] 11 98 PG[0]
PE[1] 12 97 PG[1]
PE[8] 13 96 PH[3]
PE[9] 14 95 PH[2]
PE[10] 15 94 PH[1]
PA[0] 16 93 PH[0]
PE[11] 17 92 PG[12]
VSS_HV 18 LQFP144 91 PG[13]
VDD_HV 19 90 PA[3]
VSS_HV 20 89 PB[15]
RESET 21 Top view 88 PD[15]
VSS_LV 22 87 PB[14]
VDD_LV 23 86 PD[14]
VDD_BV 24 85 PB[13]
PG[9] 25 84 PD[13]
PG[8] 26 83 PB[12]
PC[11] 27 82 VDD_HV_ADC1
PC[10] 28 81 VSS_HV_ADC1
PG[7] 29 80 PD[11]
PG[6] 30 79 PD[10]
PB[0] 31 78 PD[9]
PB[1] 32 77 PB[7]
PF[9] 33 76 PB[6]
PF[8] 34 75 PB[5]
PF[12] 35 74 VDD_HV_ADC0
PC[6] 36 73 VSS_HV_ADC0
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PC[7]
PF[10]
PF[11]
PA[15]
PF[13]
PA[14]
PA[4]
PA[13]
PA[12]

PB[9]
PB[8]
PB[10]

PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PB[4]
VDD_LV
VSS_LV

VSS_HV

VDD_HV

PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
XTAL

EXTAL

Figure 4 shows the SPC560B54/6x in the LQFP100 package.

14/133 DocID15131 Rev 9

SPC560B54x/6x Package pinouts and signal descriptions

Figure 4. LQFP100 pin configuration

VDD_HV
VSS_HV
VDD_LV
VSS_LV
PC[13]
PC[12]

PH[10]

PE[12]
PC[8]

PC[4]
PC[5]

PH[9]
PC[0]

PC[1]

PC[2]
PC[3]
PB[2]

PE[7]
PE[6]
PE[5]
PE[4]

PE[3]
PE[2]

PA[6]
PA[5]
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PB[3] 1 75 PA[11]
PC[9] 2 74 PA[10]
PC[14] 3 73 PA[9]
PC[15] 4 72 PA[8]
PA[2] 5 71 PA[7]
PE[0] 6 70 VDD_HV
PA[1] 7 69 VSS_HV
PE[1] 8 68 PA[3]
PE[8] 9 67 PB[15]
PE[9] 10 66 PD[15]
PE[10] 11 LQFP100 65 PB[14]
PA[0] 12 64 PD[14]
PE[11] 13 63 PB[13]
VSS_HV 14 62 PD[13]
VDD_HV 15 Top view 61 PB[12]
VSS_HV 16 60 VDD_HV_ADC1
RESET 17 59 VSS_HV_ADC1
VSS_LV 18 58 PD[11]
VDD_LV 19 57 PD[10]
VDD_BV 20 56 PD[9]
PC[11] 21 55 PB[7]
PC[10] 22 54 PB[6]
PB[0] 23 53 PB[5]
PB[1] 24 52 VDD_HV_ADC0
PC[6] 25 51 VSS_HV_ADC0
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PC[7]
PA[15]
PA[14]
PA[4]
PA[13]
PA[12]

PB[9]
PB[8]
PB[10]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PB[4]
XTAL

EXTAL
VDD_LV
VSS_LV

VSS_HV

VDD_HV

Figure 5 shows the SPC560B54/6x in the LBGA208 package.

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132
Package pinouts and signal descriptions SPC560B54x/6x

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A PC[8] PC[13] PH[15] PJ[4] PH[8] PH[4] PC[5] PC[0] PI[0] PI[1] PC[2] PI[4] PE[15] PH[11] NC NC A

B PC[9] PB[2] PH[13] PC[12] PE[6] PH[5] PC[4] PH[9] PH[10] PI[2] PC[3] PG[11] PG[15] PG[14] PA[11] PA[10] B

VDD_H
C PC[14]
V
PB[3] PE[7] PH[7] PE[5] PE[3] VSS_LV PC[1] PI[3] PA[5] PI[5] PE[14] PE[12] PA[9] PA[8] C

VDD_L VDD_H
D PH[14] PI[6] PC[15] PI[7] PH[6] PE[4] PE[2]
V V
NC PA[6] PH[12] PG[10] PF[14] PE[13] PA[7] D

VDD_H
E PG[4] PG[5] PG[3] PG[2] PG[1] PG[0] PF[15]
V
E

F PE[0] PA[2] PA[1] PE[1] PH[0] PH[1] PH[3] PH[2] F

VSS_H VSS_H VSS_H VSS_H VDD_H

G PE[9] PE[8] PE[10] PA[0]
V V V V V
PI[12] PI[13] MSEO G

VDD_H VSS_H VSS_H VSS_H VSS_H

H VSS_HV PE[11]
V
NC
V V V V
MDO3 MDO2 MDO0 MDO1 H

VSS_H VSS_H VSS_H VSS_H

J RESET VSS_LV NC NC
V V V V
PI[8] PI[9] PI[10] PI[11] J

VDD_H
VDD_B VDD_L VSS_H VSS_H VSS_H VSS_H
K EVTI NC
V V V V V V
V_ADC PG[12] PA[3] PG[13] K
1

L PG[9] PG[8] NC EVTO PB[15] PD[15] PD[14] PB[14] L

M PG[7] PG[6] PC[10] PC[11] PB[13] PD[13] PD[12] PB[12] M

VSS_H
VDD_H VDD_H
N PB[1] PF[9] PB[0]
V
PJ[0] PA[4] VSS_LV EXTAL
V
PF[0] PF[4] V_ADC PB[11] PD[10] PD[9] PD[11] N
1

VDD_H
VDD_L
P PF[8] PJ[3] PC[7] PJ[2] PJ[1] PA[14]
V
XTAL PB[10] PF[1] PF[5] PD[0] PD[3] V_ADC PB[6] PB[7] P
0

VSS_H
VDD_H
R PF[12] PC[6] PF[10] PF[11]
V
PA[15] PA[13] PI[14] XTAL32 PF[3] PF[7] PD[2] PD[4] PD[7] V_ADC PB[5] R
0

EXTAL
T NC NC NC MCKO NC PF[13] PA[12] PI[15]
32
PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4] T

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

NOTE: The LBGA208 is available only as development package for Nexus 2+. NC = Not connected
Figure 5. LBGA208 configuration

3.2 Pad configuration during reset phases

All pads have a fixed configuration under reset.
During the power-up phase, all pads are forced to tristate.
After power-up phase, all pads are tristate with the following exceptions:
 PA[9] (FAB) is pull-down. Without external strong pull-up the device starts fetching from
flash.
 PA[8], PC[0] and PH[9:10] are in input weak pull-up when out of reset.
 RESET pad is driven low by the device till 40 FIRC clock cycles after phase2
completion. Minimum phase3 duration is 40 FIRC cycles.
 Nexus output pads (MDO[n], MCKO, EVTO, MSEO) are forced to output.

16/133 DocID15131 Rev 9

SPC560B54x/6x Package pinouts and signal descriptions

3.3 Pad configuration during standby mode exit

Pad configuration (input buffer enable, pull enable) for low-power wakeup pads is controlled
by both the SIUL and WKPU modules. During standby exit, all low power pads
PA[0,1,2,4,15], PB[1,3,8,9,10](a), PC[7,9,11], PD[0,1], PE[0,9,11], PF[9,11,13](b),
PG[3,5,7,9](b), PI[1,3](c) are configured according to their respective configuration done in
the WKPU module. All other pads will have the same configuration as expected after a
reset.
The TDO pad has been moved into the STANDBY domain in order to allow low-power
debug handshaking in STANDBY mode. However, no pull-resistor is active on the TDO pad
while in STANDBY mode. At this time the pad is configured as an input. When no debugger
is connected the TDO pad is floating causing additional current consumption.
To avoid the extra consumption TDO must be connected. An external pull-up resistor in the
range of 47–100 kOhms should be added between the TDO pin and VDD. Only if the TDO
pin is used as an application pin and a pull-up cannot be used should a pull-down resistor
with the same value be used instead between the TDO pin and GND.

3.4 Voltage supply pins

Voltage supply pins are used to provide power to the device. Three dedicated
VDD_LV/VSS_LV supply pairs are used for 1.2 V regulator stabilization.

Table 4. Voltage supply pin descriptions

Pin number
Port pin Function
LQFP100 LQFP144 LQFP176 LBGA208

C2, D9, E16,

19, 51, 100, 6, 27, 59, 85,
VDD_HV Digital supply voltage 15, 37, 70, 84 G13, H3, N4,
123 124, 151
N9, R5
G7, G8, G9,
G10, H7, H8,
14, 16, 35, 18, 20, 49, 7, 26, 28, 57, H9, H10, J7,
VSS_HV Digital ground
69, 83 99, 122 86, 123, 150 J8, J9, J10,
K7, K8, K9,
K10
1.2 V decoupling pins. Decoupling
capacitor must be connected
VDD_LV 19, 32, 85 23, 46, 124 31, 54, 152 D8, K4, P7
between these pins and the
nearest VSS_LV pin.(1)
1.2 V decoupling pins. Decoupling
capacitor must be connected
VSS_LV 18, 33, 86 22, 47, 125 30, 55, 153 C8, J2, N7
between these pins and the
nearest VDD_LV pin.(1)

a. PB[8, 9] ports have wakeup functionality in all modes except STANDBY.

b. PF[9,11,13], PG[3,5,7,9], PI[1,3] are not available in the 100-pin LQFP.
c. PI[1,3] are not available in the 144-pin LQFP.

DocID15131 Rev 9 17/133

132
Package pinouts and signal descriptions SPC560B54x/6x

Table 4. Voltage supply pin descriptions (continued)

Pin number
Port pin Function
LQFP100 LQFP144 LQFP176 LBGA208

VDD_BV Internal regulator supply voltage 20 24 32 K3

Reference ground and analog
VSS_HV_ADC0 ground for the A/D converter 0 (10- 51 73 89 R15
bit)
Reference voltage and analog
VDD_HV_ADC0 supply for the A/D converter 0 (10- 52 74 90 P14
bit)
Reference ground and analog
VSS_HV_ADC1 ground for the A/D converter 1 (12- 59 81 98 N12
bit)
Reference voltage and analog
VDD_HV_ADC1 supply for the A/D converter 1 (12- 60 82 99 K13
bit)
1. A decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage
(see the recommended operating conditions in the device datasheet).

3.5 Pad types

In the device the following types of pads are available for system pins and functional port
pins:
S = Slow(d)
M = Medium(d) (e)
F = Fast(d) (e)
I = Input only with analog feature(d)
J = Input/Output (‘S’ pad) with analog feature
X = Oscillator

3.6 System pins

The system pins are listed in Table 5.

d. See the I/O pad electrical characteristics in the chip datasheet for details.
e. All medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium.
The only exception is PC[1] which is in medium configuration by default (see the PCR.SRC description in the
chip reference manual, Pad Configuration Registers (PCR0–PCR148)).

18/133 DocID15131 Rev 9

SPC560B54x/6x Package pinouts and signal descriptions

Table 5. System pin descriptions

I/O direction
Pin number

Pad type
RESET
Port pin Function
configuration LQFP LQFP LQFP LBGA
100 144 176 208(1)

Input weak
Bidirectional reset with Schmitt- pull-up after
RESET Trigger characteristics and noise I/O M RGM PHASE2 17 21 29 J1
filter. and 40 FIRC
cycles
Analog output of the oscillator
amplifier circuit, when the oscillator is
not in bypass mode. 
EXTAL I/O X Tristate 36 50 58 N8
Analog input for the clock generator
when the oscillator is in bypass
mode.
Analog input of the oscillator amplifier
XTAL circuit. Needs to be grounded if I X Tristate 34 48 56 P8
oscillator bypass mode is used.
1. LBGA208 available only as development package for Nexus2+.

3.7 Functional port pins

The functional port pins are listed in Table 6.

DocID15131 Rev 9 19/133

132
20/133

Package pinouts and signal descriptions

Table 6. Functional port pin descriptions

Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

Port A
AF0 GPIO[0] SIUL I/O
AF1 E0UC[0] eMIOS_0 I/O
PA[0] PCR[0] AF2 CLKOUT MC_CGM O M Tristate 12 16 24 G4
AF3 E0UC[13] eMIOS_0 I/O
— WKPU[19](5) WKPU I
DocID15131 Rev 9

AF0 GPIO[1] SIUL I/O

AF1 E0UC[1] eMIOS_0 I/O
PA[1] PCR[1] AF2 NMI(6) WKPU I S Tristate 7 11 19 F3
AF3 — — —
— WKPU[2](5) WKPU I
AF0 GPIO[2] SIUL I/O
AF1 E0UC[2] eMIOS_0 I/O
PA[2] PCR[2] AF2 — — — S Tristate 5 9 17 F2
AF3 MA[2] ADC_0 O
— WKPU[3](5) WKPU I
AF0 GPIO[3] SIUL I/O
AF1 E0UC[3] eMIOS_0 I/O
AF2 LIN5TX LINFlex_5 O
PA[3] PCR[3] J Tristate 68 90 114 K15
AF3 CS4_1 DSPI_1 O

SPC560B54x/6x
— EIRQ[0] SIUL I
— ADC1_S[0] ADC_1 I
 Table 6. Functional port pin descriptions (continued)

SPC560B54x/6x
Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[4] SIUL I/O

AF1 E0UC[4] eMIOS_0 I/O
AF2 — — —
PA[4] PCR[4] S Tristate 29 43 51 N6
AF3 CS0_1 DSPI_1 I/O
— LIN5RX LINFlex_5 I
— WKPU[9](5) WKPU I
AF0 GPIO[5] SIUL I/O
DocID15131 Rev 9

AF1 E0UC[5] eMIOS_0 I/O

PA[5] PCR[5] M Tristate 79 118 146 C11
AF2 LIN4TX LINFlex_4 O
AF3 — — —
AF0 GPIO[6] SIUL I/O
AF1 E0UC[6] eMIOS_0 I/O

Package pinouts and signal descriptions

AF2 — — —
PA[6] PCR[6] S Tristate 80 119 147 D11
AF3 CS1_1 DSPI_1 O
— EIRQ[1] SIUL I
— LIN4RX LINFlex_4 I
AF0 GPIO[7] SIUL I/O
AF1 E0UC[7] eMIOS_0 I/O
AF2 LIN3TX LINFlex_3 O
PA[7] PCR[7] J Tristate 71 104 128 D16
AF3 — — —
— EIRQ[2] SIUL I
— ADC1_S[1] ADC_1 I
21/133
 Table 6. Functional port pin descriptions (continued)
22/133

Package pinouts and signal descriptions

Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[8] SIUL I/O

AF1 E0UC[8] eMIOS_0 I/O
AF2 E0UC[14] eMIOS_0 I/O Input,
PA[8] PCR[8] AF3 — — — S weak pull- 72 105 129 C16
— EIRQ[3] SIUL I up
N/A(7) ABS[0] BAM I
— LIN3RX LINFlex_3 I
DocID15131 Rev 9

AF0 GPIO[9] SIUL I/O

AF1 E0UC[9] eMIOS_0 I/O
Pull-
PA[9] PCR[9] AF2 — — — S 73 106 130 C15
down
AF3 CS2_1 DSPI_1 O
N/A(7) FAB BAM I
AF0 GPIO[10] SIUL I/O
AF1 E0UC[10] eMIOS_0 I/O
PA[10] PCR[10] AF2 SDA I2C_0 I/O J Tristate 74 107 131 B16
AF3 LIN2TX LINFlex_2 O
— ADC1_S[2] ADC_1 I
AF0 GPIO[11] SIUL I/O
AF1 E0UC[11] eMIOS_0 I/O
AF2 SCL I2C_0 I/O
PA[11] PCR[11] AF3 — — — J Tristate 75 108 132 B15

SPC560B54x/6x
— EIRQ[16] SIUL I
— LIN2RX LINFlex_2 I
— ADC1_S[3] ADC_1 I
 Table 6. Functional port pin descriptions (continued)

SPC560B54x/6x
Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[12] SIUL I/O

AF1 — — —
AF2 E0UC[28] eMIOS_0 I/O
PA[12] PCR[12] S Tristate 31 45 53 T7
AF3 CS3_1 DSPI_1 O
— EIRQ[17] SIUL I
— SIN_0 DSPI_0 I
AF0 GPIO[13] SIUL I/O
DocID15131 Rev 9

AF1 SOUT_0 DSPI_0 O

PA[13] PCR[13] M Tristate 30 44 52 R7
AF2 E0UC[29] eMIOS_0 I/O
AF3 — — —
AF0 GPIO[14] SIUL I/O
AF1 SCK_0 DSPI_0 I/O

Package pinouts and signal descriptions

PA[14] PCR[14] AF2 CS0_0 DSPI_0 I/O M Tristate 28 42 50 P6
AF3 E0UC[0] eMIOS_0 I/O
— EIRQ[4] SIUL I
AF0 GPIO[15] SIUL I/O
AF1 CS0_0 DSPI_0 I/O
PA[15] PCR[15] AF2 SCK_0 DSPI_0 I/O M Tristate 27 40 48 R6
AF3 E0UC[1] eMIOS_0 I/O
— WKPU[10](5) WKPU I
Port B
AF0 GPIO[16] SIUL I/O
AF1 CAN0TX FlexCAN_0 O
PB[0] PCR[16] M Tristate 23 31 39 N3
AF2 E0UC[30] eMIOS_0 I/O
23/133

AF3 LIN0TX LINFlex_0 O

 Table 6. Functional port pin descriptions (continued)
24/133

Package pinouts and signal descriptions

Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[17] SIUL I/O

AF1 — — —
AF2 E0UC[31] eMIOS_0 I/O
PB[1] PCR[17] AF3 — — — S Tristate 24 32 40 N1
— WKPU[4](5) WKPU I
— CAN0RX FlexCAN_0 I
— LIN0RX LINFlex_0 I
DocID15131 Rev 9

AF0 GPIO[18] SIUL I/O

AF1 LIN0TX LINFlex_0 O
PB[2] PCR[18] M Tristate 100 144 176 B2
AF2 SDA I2C_0 I/O
AF3 E0UC[30] eMIOS_0 I/O
AF0 GPIO[19] SIUL I/O
AF1 E0UC[31] eMIOS_0 I/O
AF2 SCL I2C_0 I/O
PB[3] PCR[19] S Tristate 1 1 1 C3
AF3 — — —
— WKPU[11](5) WKPU I
— LIN0RX LINFlex_0 I
AF0 — — —
AF1 — — —
AF2 — — —
PB[4] PCR[20] AF3 — — — I Tristate 50 72 88 T16

SPC560B54x/6x
— ADC0_P[0] ADC_0 I
— ADC1_P[0] ADC_1 I
— GPIO[20] SIUL I
 Table 6. Functional port pin descriptions (continued)

SPC560B54x/6x
Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 — — —
AF1 — — —
AF2 — — —
PB[5] PCR[21] AF3 — — — I Tristate 53 75 91 R16
— ADC0_P[1] ADC_0 I
— ADC1_P[1] ADC_1 I
— GPIO[21] SIUL I
DocID15131 Rev 9

AF0 — — —
AF1 — — —
AF2 — — —
PB[6] PCR[22] AF3 — — — I Tristate 54 76 92 P15
— ADC0_P[2] ADC_0 I

Package pinouts and signal descriptions

— ADC1_P[2] ADC_1 I
— GPIO[22] SIUL I
AF0 — — —
AF1 — — —
AF2 — — —
PB[7] PCR[23] AF3 — — — I Tristate 55 77 93 P16
— ADC0_P[3] ADC_0 I
— ADC1_P[3] ADC_1 I
— GPIO[23] SIUL I
25/133
 Table 6. Functional port pin descriptions (continued)
26/133

Package pinouts and signal descriptions

Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[24] SIUL I

AF1 — — —
AF2 — — —
AF3 — — —
PB[8] PCR[24] I — 39 53 61 R9
— OSC32K_XTAL(8) OSC32K —
— WKPU[25](5) WKPU I(9)
— ADC0_S[0] ADC_0 I
DocID15131 Rev 9

— ADC1_S[4] ADC_1 I
AF0 GPIO[25] SIUL I
AF1 — — —
AF2 — — —
AF3 — — —
PB[9] PCR[25] I — 38 52 60 T9
— OSC32K_EXTAL(8) OSC32K —
— WKPU[26](5) WKPU I(9)
— ADC0_S[1] ADC_0 I
— ADC1_S[5] ADC_1 I
AF0 GPIO[26] SIUL I/O
AF1 — — —
AF2 — — —
PB[10] PCR[26] AF3 — — — J Tristate 40 54 62 P9
— WKPU[8](5) WKPU I

SPC560B54x/6x
— ADC0_S[2] ADC_0 I
— ADC1_S[6] ADC_1 I
 Table 6. Functional port pin descriptions (continued)

SPC560B54x/6x
Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[27] SIUL I/O

AF1 E0UC[3] eMIOS_0 I/O
PB[11] PCR[27] AF2 — — — J Tristate — — 97 N13
AF3 CS0_0 DSPI_0 I/O
— ADC0_S[3] ADC_0 I
AF0 GPIO[28] SIUL I/O
AF1 E0UC[4] eMIOS_0 I/O
DocID15131 Rev 9

PB[12] PCR[28] AF2 — — — J Tristate 61 83 101 M16

AF3 CS1_0 DSPI_0 O
— ADC0_X[0] ADC_0 I
AF0 GPIO[29] SIUL I/O
AF1 E0UC[5] eMIOS_0 I/O

Package pinouts and signal descriptions

PB[13] PCR[29] AF2 — — — J Tristate 63 85 103 M13
AF3 CS2_0 DSPI_0 O
— ADC0_X[1] ADC_0 I
AF0 GPIO[30] SIUL I/O
AF1 E0UC[6] eMIOS_0 I/O
PB[14] PCR[30] AF2 — — — J Tristate 65 87 105 L16
AF3 CS3_0 DSPI_0 O
— ADC0_X[2] ADC_0 I
AF0 GPIO[31] SIUL I/O
AF1 E0UC[7] eMIOS_0 I/O
PB[15] PCR[31] AF2 — — — J Tristate 67 89 107 L13
AF3 CS4_0 DSPI_0 O
27/133

— ADC0_X[3] ADC_0 I
 Table 6. Functional port pin descriptions (continued)
28/133

Package pinouts and signal descriptions

Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

Port C
AF0 GPIO[32] SIUL I/O
AF1 — — Input,
—
PC[0](10) PCR[32] M weak pull- 87 126 154 A8
AF2 TDI JTAGC I up
AF3 — — —
AF0 GPIO[33] SIUL I/O
DocID15131 Rev 9

AF1 — — —
PC[1](10) PCR[33] F(11) Tristate 82 121 149 C9
AF2 TDO JTAGC O
AF3 — — —
AF0 GPIO[34] SIUL I/O
AF1 SCK_1 DSPI_1 I/O
PC[2] PCR[34] AF2 CAN4TX FlexCAN_4 O M Tristate 78 117 145 A11
AF3 DEBUG[0] SSCM O
— EIRQ[5] SIUL I
AF0 GPIO[35] SIUL I/O
AF1 CS0_1 DSPI_1 I/O
AF2 MA[0] ADC_0 O
PC[3] PCR[35] AF3 DEBUG[1] SSCM O S Tristate 77 116 144 B11
— EIRQ[6] SIUL I
— CAN1RX FlexCAN_1 I
— CAN4RX FlexCAN_4 I

SPC560B54x/6x
 Table 6. Functional port pin descriptions (continued)

SPC560B54x/6x
Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[36] SIUL I/O

AF1 E1UC[31] eMIOS_1 I/O
AF2 — — —
PC[4] PCR[36] AF3 DEBUG[2] SSCM O M Tristate 92 131 159 B7
— EIRQ[18] SIUL I
— SIN_1 DSPI_1 I
— CAN3RX FlexCAN_3 I
DocID15131 Rev 9

AF0 GPIO[37] SIUL I/O

AF1 SOUT_1 DSPI_1 O
PC[5] PCR[37] AF2 CAN3TX FlexCAN_3 O M Tristate 91 130 158 A7
AF3 DEBUG[3] SSCM O
— EIRQ[7] SIUL I

Package pinouts and signal descriptions

AF0 GPIO[38] SIUL I/O
AF1 LIN1TX LINFlex_1 O
PC[6] PCR[38] S Tristate 25 36 44 R2
AF2 E1UC[28] eMIOS_1 I/O
AF3 DEBUG[4] SSCM O
AF0 GPIO[39] SIUL I/O
AF1 — — —
AF2 E1UC[29] eMIOS_1 I/O
PC[7] PCR[39] S Tristate 26 37 45 P3
AF3 DEBUG[5] SSCM O
— LIN1RX LINFlex_1 I
— WKPU[12](5) WKPU I
29/133
 Table 6. Functional port pin descriptions (continued)
30/133

Package pinouts and signal descriptions

Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[40] SIUL I/O

AF1 LIN2TX LINFlex_2 O
PC[8] PCR[40] S Tristate 99 143 175 A1
AF2 E0UC[3] eMIOS_0 I/O
AF3 DEBUG[6] SSCM O
AF0 GPIO[41] SIUL I/O
AF1 — — —
AF2 E0UC[7] eMIOS_0 I/O
DocID15131 Rev 9

PC[9] PCR[41] S Tristate 2 2 2 B1

AF3 DEBUG[7] SSCM O
— WKPU[13](5) WKPU I
— LIN2RX LINFlex_2 I
AF0 GPIO[42] SIUL I/O
AF1 CAN1TX FlexCAN_1 O
PC[10] PCR[42] M Tristate 22 28 36 M3
AF2 CAN4TX FlexCAN_4 O
AF3 MA[1] ADC_0 O
AF0 GPIO[43] SIUL I/O
AF1 — — —
AF2 — — —
PC[11] PCR[43] AF3 MA[2] ADC_0 O S Tristate 21 27 35 M4
— WKPU[5](5) WKPU I
— CAN1RX FlexCAN_1 I
— CAN4RX FlexCAN_4 I

SPC560B54x/6x
 Table 6. Functional port pin descriptions (continued)

SPC560B54x/6x
Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[44] SIUL I/O

AF1 E0UC[12] eMIOS_0 I/O
AF2 — — —
PC[12] PCR[44] M Tristate 97 141 173 B4
AF3 — — —
— EIRQ[19] SIUL I
— SIN_2 DSPI_2 I
AF0 GPIO[45] SIUL I/O
DocID15131 Rev 9

AF1 E0UC[13] eMIOS_0 I/O

PC[13] PCR[45] S Tristate 98 142 174 A2
AF2 SOUT_2 DSPI_2 O
AF3 — — —
AF0 GPIO[46] SIUL I/O
AF1 E0UC[14] eMIOS_0 I/O

Package pinouts and signal descriptions

PC[14] PCR[46] AF2 SCK_2 DSPI_2 I/O S Tristate 3 3 3 C1
AF3 — — —
— EIRQ[8] SIUL I
AF0 GPIO[47] SIUL I/O
AF1 E0UC[15] eMIOS_0 I/O
PC[15] PCR[47] AF2 CS0_2 DSPI_2 I/O M Tristate 4 4 4 D3
AF3 — — —
— EIRQ[20] SIUL I
Port D
31/133
 Table 6. Functional port pin descriptions (continued)
32/133

Package pinouts and signal descriptions

Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[48] SIUL I

AF1 — — —
AF2 — — —
PD[0] PCR[48] AF3 — — — I Tristate 41 63 77 P12
— WKPU[27](5) WKPU I
— ADC0_P[4] ADC_0 I
— ADC1_P[4] ADC_1 I
DocID15131 Rev 9

AF0 GPIO[49] SIUL I

AF1 — — —
AF2 — — —
PD[1] PCR[49] AF3 — — — I Tristate 42 64 78 T12
— WKPU[28](5) WKPU I
— ADC0_P[5] ADC_0 I
— ADC1_P[5] ADC_1 I
AF0 GPIO[50] SIUL I
AF1 — — —
AF2 — — —
PD[2] PCR[50] I Tristate 43 65 79 R12
AF3 — — —
— ADC0_P[6] ADC_0 I
— ADC1_P[6] ADC_1 I
AF0 GPIO[51] SIUL I

SPC560B54x/6x
AF1 — — —
AF2 — — —
PD[3] PCR[51] I Tristate 44 66 80 P13
AF3 — — —
— ADC0_P[7] ADC_0 I
— ADC1_P[7] ADC_1 I
 Table 6. Functional port pin descriptions (continued)

SPC560B54x/6x
Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[52] SIUL I

AF1 — — —
AF2 — — —
PD[4] PCR[52] I Tristate 45 67 81 R13
AF3 — — —
— ADC0_P[8] ADC_0 I
— ADC1_P[8] ADC_1 I
AF0 GPIO[53] SIUL I
DocID15131 Rev 9

AF1 — — —
AF2 — — —
PD[5] PCR[53] I Tristate 46 68 82 T13
AF3 — — —
— ADC0_P[9] ADC_0 I
— ADC1_P[9] ADC_1 I

Package pinouts and signal descriptions

AF0 GPIO[54] SIUL I
AF1 — — —
AF2 — — —
PD[6] PCR[54] I Tristate 47 69 83 T14
AF3 — — —
— ADC0_P[10] ADC_0 I
— ADC1_P[10] ADC_1 I
AF0 GPIO[55] SIUL I
AF1 — — —
AF2 — — —
PD[7] PCR[55] I Tristate 48 70 84 R14
AF3 — — —
— ADC0_P[11] ADC_0 I
— ADC1_P[11] ADC_1 I
33/133
 Table 6. Functional port pin descriptions (continued)
34/133

Package pinouts and signal descriptions

Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[56] SIUL I

AF1 — — —
AF2 — — —
PD[8] PCR[56] I Tristate 49 71 87 T15
AF3 — — —
— ADC0_P[12] ADC_0 I
— ADC1_P[12] ADC_1 I
AF0 GPIO[57] SIUL I
DocID15131 Rev 9

AF1 — — —
AF2 — — —
PD[9] PCR[57] I Tristate 56 78 94 N15
AF3 — — —
— ADC0_P[13] ADC_0 I
— ADC1_P[13] ADC_1 I
AF0 GPIO[58] SIUL I
AF1 — — —
AF2 — — —
PD[10] PCR[58] I Tristate 57 79 95 N14
AF3 — — —
— ADC0_P[14] ADC_0 I
— ADC1_P[14] ADC_1 I
AF0 GPIO[59] SIUL I
AF1 — — —
AF2 — — —

SPC560B54x/6x
PD[11] PCR[59] I Tristate 58 80 96 N16
AF3 — — —
— ADC0_P[15] ADC_0 I
— ADC1_P[15] ADC_1 I
 Table 6. Functional port pin descriptions (continued)

SPC560B54x/6x
Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[60] SIUL I/O

AF1 CS5_0 DSPI_0 O
PD[12] PCR[60] AF2 E0UC[24] eMIOS_0 I/O J Tristate — — 100 M15
AF3 — — —
— ADC0_S[4] ADC_0 I
AF0 GPIO[61] SIUL I/O
AF1 CS0_1 DSPI_1 I/O
DocID15131 Rev 9

PD[13] PCR[61] AF2 E0UC[25] eMIOS_0 I/O J Tristate 62 84 102 M14

AF3 — — —
— ADC0_S[5] ADC_0 I
AF0 GPIO[62] SIUL I/O
AF1 CS1_1 DSPI_1 O

Package pinouts and signal descriptions

PD[14] PCR[62] AF2 E0UC[26] eMIOS_0 I/O J Tristate 64 86 104 L15
AF3 — — —
— ADC0_S[6] ADC_0 I
AF0 GPIO[63] SIUL I/O
AF1 CS2_1 DSPI_1 O
PD[15] PCR[63] AF2 E0UC[27] eMIOS_0 I/O J Tristate 66 88 106 L14
AF3 — — —
— ADC0_S[7] ADC_0 I
Port E
35/133
 Table 6. Functional port pin descriptions (continued)
36/133

Package pinouts and signal descriptions

Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[64] SIUL I/O

AF1 E0UC[16] eMIOS_0 I/O
AF2 — — —
PE[0] PCR[64] S Tristate 6 10 18 F1
AF3 — — —
— WKPU[6](5) WKPU I
— CAN5RX FlexCAN_5 I
AF0 GPIO[65] SIUL I/O
DocID15131 Rev 9

AF1 E0UC[17] eMIOS_0 I/O

PE[1] PCR[65] M Tristate 8 12 20 F4
AF2 CAN5TX FlexCAN_5 O
AF3 — — —
AF0 GPIO[66] SIUL I/O
AF1 E0UC[18] eMIOS_0 I/O
AF2 — — —
PE[2] PCR[66] M Tristate 89 128 156 D7
AF3 — — —
— EIRQ[21] SIUL I
— SIN_1 DSPI_1 I
AF0 GPIO[67] SIUL I/O
AF1 E0UC[19] eMIOS_0 I/O
PE[3] PCR[67] M Tristate 90 129 157 C7
AF2 SOUT_1 DSPI_1 O
AF3 — — —
AF0 GPIO[68] SIUL I/O

SPC560B54x/6x
AF1 E0UC[20] eMIOS_0 I/O
PE[4] PCR[68] AF2 SCK_1 DSPI_1 I/O M Tristate 93 132 160 D6
AF3 — — —
— EIRQ[9] SIUL I
 Table 6. Functional port pin descriptions (continued)

SPC560B54x/6x
Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[69] SIUL I/O

AF1 E0UC[21] eMIOS_0 I/O
PE[5] PCR[69] M Tristate 94 133 161 C6
AF2 CS0_1 DSPI_1 I/O
AF3 MA[2] ADC_0 O
AF0 GPIO[70] SIUL I/O
AF1 E0UC[22] eMIOS_0 I/O
PE[6] PCR[70] AF2 CS3_0 DSPI_0 O M Tristate 95 139 167 B5
DocID15131 Rev 9

AF3 MA[1] ADC_0 O

— EIRQ[22] SIUL I
AF0 GPIO[71] SIUL I/O
AF1 E0UC[23] eMIOS_0 I/O
PE[7] PCR[71] AF2 CS2_0 DSPI_0 O M Tristate 96 140 168 C4

Package pinouts and signal descriptions

AF3 MA[0] ADC_0 O
— EIRQ[23] SIUL I
AF0 GPIO[72] SIUL I/O
AF1 CAN2TX FlexCAN_2 O
PE[8] PCR[72] M Tristate 9 13 21 G2
AF2 E0UC[22] eMIOS_0 I/O
AF3 CAN3TX FlexCAN_3 O
AF0 GPIO[73] SIUL I/O
AF1 — — —
AF2 E0UC[23] eMIOS_0 I/O
PE[9] PCR[73] AF3 — — — S Tristate 10 14 22 G1
— WKPU[7](5) WKPU I
— CAN2RX FlexCAN_2 I
37/133

— CAN3RX FlexCAN_3 I
 Table 6. Functional port pin descriptions (continued)
38/133

Package pinouts and signal descriptions

Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[74] SIUL I/O

AF1 LIN3TX LINFlex_3 O
PE[10] PCR[74] AF2 CS3_1 DSPI_1 O S Tristate 11 15 23 G3
AF3 E1UC[30] eMIOS_1 I/O
— EIRQ[10] SIUL I
AF0 GPIO[75] SIUL I/O
AF1 E0UC[24] eMIOS_0 I/O
DocID15131 Rev 9

AF2 CS4_1 DSPI_1 O

PE[11] PCR[75] S Tristate 13 17 25 H2
AF3 — — —
— LIN3RX LINFlex_3 I
— WKPU[14](5) WKPU I
AF0 GPIO[76] SIUL I/O
AF1 — — —
AF2 E1UC[19](12) eMIOS_1 I/O
PE[12] PCR[76] AF3 — — — J Tristate 76 109 133 C14
— EIRQ[11] SIUL I
— SIN_2 DSPI_2 I
— ADC1_S[7] ADC_1 I
AF0 GPIO[77] SIUL I/O
AF1 SOUT_2 DSPI_2 O
PE[13] PCR[77] S Tristate — 103 127 D15
AF2 E1UC[20] eMIOS_1 I/O

SPC560B54x/6x
AF3 — — —
 Table 6. Functional port pin descriptions (continued)

SPC560B54x/6x
Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[78] SIUL I/O

AF1 SCK_2 DSPI_2 I/O
PE[14] PCR[78] AF2 E1UC[21] eMIOS_1 I/O S Tristate — 112 136 C13
AF3 — — —
— EIRQ[12] SIUL I
AF0 GPIO[79] SIUL I/O
AF1 CS0_2 DSPI_2 I/O
DocID15131 Rev 9

PE[15] PCR[79] M Tristate — 113 137 A13

AF2 E1UC[22] eMIOS_1 I/O
AF3 — — —
Port F
AF0 GPIO[80] SIUL I/O
AF1 E0UC[10] eMIOS_0 I/O

Package pinouts and signal descriptions

PF[0] PCR[80] AF2 CS3_1 DSPI_1 O J Tristate — 55 63 N10
AF3 — — —
— ADC0_S[8] ADC_0 I
AF0 GPIO[81] SIUL I/O
AF1 E0UC[11] eMIOS_0 I/O
PF[1] PCR[81] AF2 CS4_1 DSPI_1 O J Tristate — 56 64 P10
AF3 — — —
— ADC0_S[9] ADC_0 I
AF0 GPIO[82] SIUL I/O
AF1 E0UC[12] eMIOS_0 I/O
PF[2] PCR[82] AF2 CS0_2 DSPI_2 I/O J Tristate — 57 65 T10
AF3 — — —
39/133

— ADC0_S[10] ADC_0 I
 Table 6. Functional port pin descriptions (continued)
40/133

Package pinouts and signal descriptions

Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[83] SIUL I/O

AF1 E0UC[13] eMIOS_0 I/O
PF[3] PCR[83] AF2 CS1_2 DSPI_2 O J Tristate — 58 66 R10
AF3 — — —
— ADC0_S[11] ADC_0 I
AF0 GPIO[84] SIUL I/O
AF1 E0UC[14] eMIOS_0 I/O
DocID15131 Rev 9

PF[4] PCR[84] AF2 CS2_2 DSPI_2 O J Tristate — 59 67 N11

AF3 — — —
— ADC0_S[12] ADC_0 I
AF0 GPIO[85] SIUL I/O
AF1 E0UC[22] eMIOS_0 I/O
PF[5] PCR[85] AF2 CS3_2 DSPI_2 O J Tristate — 60 68 P11
AF3 — — —
— ADC0_S[13] ADC_0 I
AF0 GPIO[86] SIUL I/O
AF1 E0UC[23] eMIOS_0 I/O
PF[6] PCR[86] AF2 CS1_1 DSPI_1 O J Tristate — 61 69 T11
AF3 — — —
— ADC0_S[14] ADC_0 I
AF0 GPIO[87] SIUL I/O

SPC560B54x/6x
AF1 — — —
PF[7] PCR[87] AF2 CS2_1 DSPI_1 O J Tristate — 62 70 R11
AF3 — — —
— ADC0_S[15] ADC_0 I
 Table 6. Functional port pin descriptions (continued)

SPC560B54x/6x
Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[88] SIUL I/O

AF1 CAN3TX FlexCAN_3 O
PF[8] PCR[88] M Tristate — 34 42 P1
AF2 CS4_0 DSPI_0 O
AF3 CAN2TX FlexCAN_2 O
AF0 GPIO[89] SIUL I/O
AF1 E1UC[1] eMIOS_1 I/O
AF2 CS5_0 DSPI_0 O
DocID15131 Rev 9

PF[9] PCR[89] AF3 — — — S Tristate — 33 41 N2

— WKPU[22](5) WKPU I
— CAN2RX FlexCAN_2 I
— CAN3RX FlexCAN_3 I
AF0 GPIO[90] SIUL I/O

Package pinouts and signal descriptions

AF1 CS1_0 DSPI_0 O
PF[10] PCR[90] M Tristate — 38 46 R3
AF2 LIN4TX LINFlex_4 O
AF3 E1UC[2] eMIOS_1 I/O
AF0 GPIO[91] SIUL I/O
AF1 CS2_0 DSPI_0 O
AF2 E1UC[3] eMIOS_1 I/O
PF[11] PCR[91] S Tristate — 39 47 R4
AF3 — — —
— WKPU[15](5) WKPU I
— LIN4RX LINFlex_4 I
AF0 GPIO[92] SIUL I/O
AF1 E1UC[25] eMIOS_1 I/O
PF[12] PCR[92] M Tristate — 35 43 R1
AF2 LIN5TX LINFlex_5 O
41/133

AF3 — — —
 Table 6. Functional port pin descriptions (continued)
42/133

Package pinouts and signal descriptions

Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[93] SIUL I/O

AF1 E1UC[26] eMIOS_1 I/O
AF2 — — —
PF[13] PCR[93] S Tristate — 41 49 T6
AF3 — — —
— WKPU[16](5) WKPU I
— LIN5RX LINFlex_5 I
AF0 GPIO[94] SIUL I/O
DocID15131 Rev 9

AF1 CAN4TX FlexCAN_4 O

PF[14] PCR[94] M Tristate — 102 126 D14
AF2 E1UC[27] eMIOS_1 I/O
AF3 CAN1TX FlexCAN_1 O
AF0 GPIO[95] SIUL I/O
AF1 E1UC[4] eMIOS_1 I/O
AF2 — — —
PF[15] PCR[95] AF3 — — — S Tristate — 101 125 E15
— EIRQ[13] SIUL I
— CAN1RX FlexCAN_1 I
— CAN4RX FlexCAN_4 I
Port G
AF0 GPIO[96] SIUL I/O
AF1 CAN5TX FlexCAN_5 O
PG[0] PCR[96] M Tristate — 98 122 E14
AF2 E1UC[23] eMIOS_1 I/O

SPC560B54x/6x
AF3 — — —
 Table 6. Functional port pin descriptions (continued)

SPC560B54x/6x
Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[97] SIUL I/O

AF1 — — —
AF2 E1UC[24] eMIOS_1 I/O
PG[1] PCR[97] S Tristate — 97 121 E13
AF3 — — —
— EIRQ[14] SIUL I
— CAN5RX FlexCAN_5 I
AF0 GPIO[98] SIUL I/O
DocID15131 Rev 9

AF1 E1UC[11] eMIOS_1 I/O

PG[2] PCR[98] M Tristate — 8 16 E4
AF2 SOUT_3 DSPI_3 O
AF3 — — —
AF0 GPIO[99] SIUL I/O
AF1 E1UC[12] eMIOS_1 I/O

Package pinouts and signal descriptions

PG[3] PCR[99] AF2 CS0_3 DSPI_3 I/O S Tristate — 7 15 E3
AF3 — — —
— WKPU[17](5) WKPU I
AF0 GPIO[100] SIUL I/O
AF1 E1UC[13] eMIOS_1 I/O
PG[4] PCR[100] M Tristate — 6 14 E1
AF2 SCK_3 DSPI_3 I/O
AF3 — — —
AF0 GPIO[101] SIUL I/O
AF1 E1UC[14] eMIOS_1 I/O
AF2 — — —
PG[5] PCR[101] S Tristate — 5 13 E2
AF3 — — —
— WKPU[18](5) WKPU I
43/133

— SIN_3 DSPI_3 I
 Table 6. Functional port pin descriptions (continued)
44/133

Package pinouts and signal descriptions

Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[102] SIUL I/O

AF1 E1UC[15] eMIOS_1 I/O
PG[6] PCR[102] M Tristate — 30 38 M2
AF2 LIN6TX LINFlex_6 O
AF3 — — —
AF0 GPIO[103] SIUL I/O
AF1 E1UC[16] eMIOS_1 I/O
AF2 E1UC[30] eMIOS_1 I/O
DocID15131 Rev 9

PG[7] PCR[103] S Tristate — 29 37 M1

AF3 — — —
— WKPU[20](5) WKPU I
— LIN6RX LINFlex_6 I
AF0 GPIO[104] SIUL I/O
AF1 E1UC[17] eMIOS_1 I/O
PG[8] PCR[104] AF2 LIN7TX LINFlex_7 O S Tristate — 26 34 L2
AF3 CS0_2 DSPI_2 I/O
— EIRQ[15] SIUL I
AF0 GPIO[105] SIUL I/O
AF1 E1UC[18] eMIOS_1 I/O
AF2 — — —
PG[9] PCR[105] S Tristate — 25 33 L1
AF3 SCK_2 DSPI_2 I/O
— WKPU[21](5) WKPU I
— LIN7RX LINFlex_7 I

SPC560B54x/6x
 Table 6. Functional port pin descriptions (continued)

SPC560B54x/6x
Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[106] SIUL I/O

AF1 E0UC[24] eMIOS_0 I/O
PG[10] PCR[106] AF2 E1UC[31] eMIOS_1 I/O S Tristate — 114 138 D13
AF3 — — —
— SIN_4 DSPI_4 I
AF0 GPIO[107] SIUL I/O
AF1 E0UC[25] eMIOS_0 I/O
DocID15131 Rev 9

PG[11] PCR[107] M Tristate — 115 139 B12

AF2 CS0_4 DSPI_4 I/O
AF3 — — —
AF0 GPIO[108] SIUL I/O
AF1 E0UC[26] eMIOS_0 I/O
PG[12] PCR[108] M Tristate — 92 116 K14
AF2 SOUT_4 DSPI_4 O

Package pinouts and signal descriptions

AF3 — — —
AF0 GPIO[109] SIUL I/O
AF1 E0UC[27] eMIOS_0 I/O
PG[13] PCR[109] M Tristate — 91 115 K16
AF2 SCK_4 DSPI_4 I/O
AF3 — — —
AF0 GPIO[110] SIUL I/O
AF1 E1UC[0] eMIOS_1 I/O
PG[14] PCR[110] S Tristate — 110 134 B14
AF2 LIN8TX LINFlex_8 O
AF3 — — —
45/133
 Table 6. Functional port pin descriptions (continued)
46/133

Package pinouts and signal descriptions

Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[111] SIUL I/O

AF1 E1UC[1] eMIOS_1 I/O
PG[15] PCR[111] AF2 — — — M Tristate — 111 135 B13
AF3 — — —
— LIN8RX LINFlex_8 I
Port H
DocID15131 Rev 9

AF0 GPIO[112] SIUL I/O

AF1 E1UC[2] eMIOS_1 I/O
PH[0] PCR[112] AF2 — — — M Tristate — 93 117 F13
AF3 — — —
— SIN_1 DSPI_1 I
AF0 GPIO[113] SIUL I/O
AF1 E1UC[3] eMIOS_1 I/O
PH[1] PCR[113] M Tristate — 94 118 F14
AF2 SOUT_1 DSPI_1 O
AF3 — — —
AF0 GPIO[114] SIUL I/O
AF1 E1UC[4] eMIOS_1 I/O
PH[2] PCR[114] M Tristate — 95 119 F16
AF2 SCK_1 DSPI_1 I/O
AF3 — — —
AF0 GPIO[115] SIUL I/O

SPC560B54x/6x
AF1 E1UC[5] eMIOS_1 I/O
PH[3] PCR[115] M Tristate — 96 120 F15
AF2 CS0_1 DSPI_1 I/O
AF3 — — —
 Table 6. Functional port pin descriptions (continued)

SPC560B54x/6x
Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[116] SIUL I/O

AF1 E1UC[6] eMIOS_1 I/O
PH[4] PCR[116] M Tristate — 134 162 A6
AF2 — — —
AF3 — — —
AF0 GPIO[117] SIUL I/O
AF1 E1UC[7] eMIOS_1 I/O
PH[5] PCR[117] S Tristate — 135 163 B6
AF2 — — —
DocID15131 Rev 9

AF3 — — —
AF0 GPIO[118] SIUL I/O
AF1 E1UC[8] eMIOS_1 I/O
PH[6] PCR[118] M Tristate — 136 164 D5
AF2 — — —
AF3 MA[2] ADC_0 O

Package pinouts and signal descriptions

AF0 GPIO[119] SIUL I/O
AF1 E1UC[9] eMIOS_1 I/O
PH[7] PCR[119] M Tristate — 137 165 C5
AF2 CS3_2 DSPI_2 O
AF3 MA[1] ADC_0 O
AF0 GPIO[120] SIUL I/O
AF1 E1UC[10] eMIOS_1 I/O
PH[8] PCR[120] M Tristate — 138 166 A5
AF2 CS2_2 DSPI_2 O
AF3 MA[0] ADC_0 O
AF0 GPIO[121] SIUL I/O
AF1 — — Input,
—
PH[9](10) PCR[121] S weak pull- 88 127 155 B8
AF2 TCK JTAGC I up
AF3 — — —
47/133
 Table 6. Functional port pin descriptions (continued)
48/133

Package pinouts and signal descriptions

Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[122] SIUL I/O

AF1 — — Input,
—
PH[10](10) PCR[122] M weak pull- 81 120 148 B9
AF2 TMS JTAGC I up
AF3 — — —
AF0 GPIO[123] SIUL I/O
AF1 SOUT_3 DSPI_3 O
PH[11] PCR[123] M Tristate — — 140 A14
AF2 CS0_4 DSPI_4 I/O
DocID15131 Rev 9

AF3 E1UC[5] eMIOS_1 I/O

AF0 GPIO[124] SIUL I/O
AF1 SCK_3 DSPI_3 I/O
PH[12] PCR[124] M Tristate — — 141 D12
AF2 CS1_4 DSPI_4 O
AF3 E1UC[25] eMIOS_1 I/O
AF0 GPIO[125] SIUL I/O
AF1 SOUT_4 DSPI_4 O
PH[13] PCR[125] M Tristate — — 9 B3
AF2 CS0_3 DSPI_3 I/O
AF3 E1UC[26] eMIOS_1 I/O
AF0 GPIO[126] SIUL I/O
AF1 SCK_4 DSPI_4 I/O
PH[14] PCR[126] M Tristate — — 10 D1
AF2 CS1_3 DSPI_3 O
AF3 E1UC[27] eMIOS_1 I/O

SPC560B54x/6x
AF0 GPIO[127] SIUL I/O
AF1 SOUT_5 DSPI_5 O
PH[15] PCR[127] M Tristate — — 8 A3
AF2 — — —
AF3 E1UC[17] eMIOS_1 I/O
Port I
 Table 6. Functional port pin descriptions (continued)

SPC560B54x/6x
Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[128] SIUL I/O

AF1 E0UC[28] eMIOS_0 I/O
PI[0] PCR[128] S Tristate — — 172 A9
AF2 LIN8TX LINFlex_8 O
AF3 — — —
AF0 GPIO[129] SIUL I/O
AF1 E0UC[29] eMIOS_0 I/O
AF2 — — —
DocID15131 Rev 9

PI[1] PCR[129] S Tristate — — 171 A10

AF3 — — —
— WKPU[24](5) WKPU I
— LIN8RX LINFlex_8 I
AF0 GPIO[130] SIUL I/O
AF1 E0UC[30] eMIOS_0 I/O
PI[2] PCR[130] S Tristate — — 170 B10

Package pinouts and signal descriptions

AF2 LIN9TX LINFlex_9 O
AF3 — — —
AF0 GPIO[131] SIUL I/O
AF1 E0UC[31] eMIOS_0 I/O
AF2 — — —
PI[3] PCR[131] S Tristate — — 169 C10
AF3 — — —
— WKPU[23](5) WKPU I
— LIN9RX LINFlex_9 I
AF0 GPIO[132] SIUL I/O
AF1 E1UC[28] eMIOS_1 I/O
PI[4] PCR[132] S Tristate — — 143 A12
AF2 SOUT_4 DSPI_4 O
AF3 — — —
49/133
 Table 6. Functional port pin descriptions (continued)
50/133

Package pinouts and signal descriptions

Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[133] SIUL I/O

AF1 E1UC[29] eMIOS_1 I/O
PI[5] PCR[133] S Tristate — — 142 C12
AF2 SCK_4 DSPI_4 I/O
AF3 — — —
AF0 GPIO[134] SIUL I/O
AF1 E1UC[30] eMIOS_1 I/O
PI[6] PCR[134] S Tristate — — 11 D2
AF2 CS0_4 DSPI_4 I/O
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AF3 — — —
AF0 GPIO[135] SIUL I/O
AF1 E1UC[31] eMIOS_1 I/O
PI[7] PCR[135] S Tristate — — 12 D3
AF2 CS1_4 DSPI_4 O
AF3 — — —
AF0 GPIO[136] SIUL I/O
AF1 — — —
PI[8] PCR[136] AF2 — — — J Tristate — — 108 J13
AF3 — — —
— ADC0_S[16] ADC_0 I
AF0 GPIO[137] SIUL I/O
AF1 — — —
PI[9] PCR[137] AF2 — — — J Tristate — — 109 J14
AF3 — — —

SPC560B54x/6x
— ADC0_S[17] ADC_0 I
 Table 6. Functional port pin descriptions (continued)

SPC560B54x/6x
Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[138] SIUL I/O

AF1 — — —
PI[10] PCR[138] AF2 — — — J Tristate — — 110 J15
AF3 — — —
— ADC0_S[18] ADC_0 I
AF0 GPIO[139] SIUL I/O
AF1 — — —
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AF2 — — —
PI[11] PCR[139] J Tristate — — 111 J16
AF3 — — —
— ADC0_S[19] ADC_0 I
— SIN_3 DSPI_3 I
AF0 GPIO[140] SIUL I/O

Package pinouts and signal descriptions

AF1 CS0_3 DSPI_3 I/O
PI[12] PCR[140] AF2 — — — J Tristate — — 112 G14
AF3 — — —
— ADC0_S[20] ADC_0 I
AF0 GPIO[141] SIUL I/O
AF1 CS1_3 DSPI_3 O
PI[13] PCR[141] AF2 — — — J Tristate — — 113 G15
AF3 — — —
— ADC0_S[21] ADC_0 I
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 Table 6. Functional port pin descriptions (continued)
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Package pinouts and signal descriptions

Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[142] SIUL I/O

AF1 — — —
AF2 — — —
PI[14] PCR[142] J Tristate — — 76 R8
AF3 — — —
— ADC0_S[22] ADC_0 I
— SIN_4 DSPI_4 I
AF0 GPIO[143] SIUL I/O
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AF1 CS0_4 DSPI_4 I/O

PI[15] PCR[143] AF2 — — — J Tristate — — 75 T8
AF3 — — —
— ADC0_S[23] ADC_0 I
Port J
AF0 GPIO[144] SIUL I/O
AF1 CS1_4 DSPI_4 O
PJ[0] PCR[144] AF2 — — — J Tristate — — 74 N5
AF3 — — —
— ADC0_S[24] ADC_0 I
AF0 GPIO[145] SIUL I/O
AF1 — — —
AF2 — — —
PJ[1] PCR[145] J Tristate — — 73 P5
AF3 — —— —

SPC560B54x/6x
— ADC0_S[25] ADC_0 I
— SIN_5 DSPI_5 I
 Table 6. Functional port pin descriptions (continued)

SPC560B54x/6x
Alternate function(1)
Pin number

configuration(3)
I/O direction(2)

Pad type

RESET
Port pin PCR Function Peripheral
LQFP LQFP LQFP LBGA
100 144 176 208(4)

AF0 GPIO[146] SIUL I/O

AF1 CS0_5 DSPI_5 I/O
PJ[2] PCR[146] AF2 — — — J Tristate — — 72 P4
AF3 — — —
— ADC0_S[26] ADC_0 I
AF0 GPIO[147] SIUL I/O
AF1 CS1_5 DSPI_5 O
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PJ[3] PCR[147] AF2 — — — J Tristate — — 71 P2

AF3 — — —
— ADC0_S[27] ADC_0 I
AF0 GPIO[148] SIUL I/O
AF1 SCK_5 DSPI_5 I/O
PJ[4] PCR[148] M Tristate — — 5 A4

Package pinouts and signal descriptions

AF2 E1UC[18] eMIOS_1 I/O
AF3 — — —
1. Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00  AF0; PCR.PA = 01  AF1; PCR.PA = 10  AF2;
PCR.PA = 11  AF2. This is intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to ‘1’, regardless of the values
selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as “—”.
2. Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMIO.PADSELx bitfields inside
the SIUL module.
3. The RESET configuration applies during and after reset.
4. LBGA208 available only as development package for Nexus2+
5. All WKPU pins also support external interrupt capability. See the WKPU chapter for further details.
6. NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.
7. “Not applicable” because these functions are available only while the device is booting. Refer to the BAM information for details.
8. Value of PCR.IBE bit must be 0.
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9. This wakeup input cannot be used to exit STANDBY mode.

54/133

Package pinouts and signal descriptions

10. Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.
PC[0:1] are available as JTAG pins (TDI and TDO respectively).
PH[9:10] are available as JTAG pins (TCK and TMS respectively).
It is up to the user to configure these pins as GPIO when needed.
11. PC[1] is a fast/medium pad but is in medium configuration by default. This pad is in Alternate Function 2 mode after reset which has TDO functionality. The reset value of
PCR.OBE is ‘1’, but this setting has no impact as long as this pad stays in AF2 mode. After configuring this pad as GPIO (PCR.PA = 0), output buffer is enabled as reset
value of PCR.OBE = 1.
12. Not available in LQFP100 package.
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SPC560B54x/6x Package pinouts and signal descriptions

3.8 Nexus 2+ pins

In the LBGA208 package, eight additional debug pins are available (see Table 7).

Table 7. Nexus 2+ pin descriptions

Pin number
I/O Function
Port pin Function Pad type
direction after reset LQFP LQFP LBGA
100 144 208(1)

MCKO Message clock out O F — — — T4

MDO0 Message data out 0 O M — — — H15
MDO1 Message data out 1 O M — — — H16
MDO2 Message data out 2 O M — — — H14
MDO3 Message data out 3 O M — — — H13
EVTI Event in I M Pull-up — — K1
EVTO Event out O M — — — L4
MSEO Message start/end out O M — — — G16
1. LBGA208 available only as development package for Nexus2+.

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4 Electrical characteristics

This section contains electrical characteristics of the device as well as temperature and
power considerations.
This product contains devices to protect the inputs against damage due to high static
voltages. However, it is advisable to take precautions to avoid application of any voltage
higher than the specified maximum rated voltages.
To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD
or VSS). This could be done by the internal pull-up and pull-down, which is provided by the
product for most general purpose pins.
The parameters listed in the following tables represent the characteristics of the device and
its demands on the system.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” for System Requirement is included in the
Symbol column.

4.1 Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in Table 8 are used and
the parameters are tagged accordingly in the tables where appropriate.

Table 8. Parameter classifications

Classification tag Tag description

P Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically
C
relevant sample size across process variations.
Those parameters are achieved by design characterization on a small sample size from
T typical devices under typical conditions unless otherwise noted. All values shown in the typical
column are within this category.
D Those parameters are derived mainly from simulations.

Note: The classification is shown in the column labeled “C” in the parameter tables where
appropriate.

4.2 NVUSRO register

Bit values in the Non-Volatile User Options (NVUSRO) Register control portions of the
device configuration, namely electrical parameters such as high voltage supply and
oscillator margin, as well as digital functionality (watchdog enable/disable after reset).

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For a detailed description of the NVUSRO register, please refer to the device reference
manual.

4.2.1 NVUSRO[PAD3V5V] field description

The DC electrical characteristics are dependent on the PAD3V5V bit value. Table 9 shows
how NVUSRO[PAD3V5V] controls the device configuration.

Table 9. PAD3V5V field description(1)

Value(2) Description

0 High voltage supply is 5.0 V

1 High voltage supply is 3.3 V
1. See the device reference manual for more information on the NVUSRO register.
2. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.

4.2.2 NVUSRO[OSCILLATOR_MARGIN] field description

The fast external crystal oscillator consumption is dependent on the
OSCILLATOR_MARGIN bit value. Table 10 shows how NVUSRO[OSCILLATOR_MARGIN]
controls the device configuration.

Table 10. OSCILLATOR_MARGIN field description(1)

Value(2) Description

0 Low consumption configuration (4 MHz/8 MHz)

1 High margin configuration (4 MHz/16 MHz)
1. See the device reference manual for more information on the NVUSRO register.
2. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.

4.2.3 NVUSRO[WATCHDOG_EN] field description

The watchdog enable/disable configuration after reset is dependent on the
WATCHDOG_EN bit value. Table 11 shows how NVUSRO[WATCHDOG_EN] controls the
device configuration.

Table 11. WATCHDOG_EN field description

Value(1) Description

0 Disable after reset

1 Enable after reset
1. Default manufacturing value is ‘1’. Value can be programmed by customer in Shadow Flash.

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4.3 Absolute maximum ratings

Table 12. Absolute maximum ratings
Value
Symbol Parameter Conditions Unit
Min Max

VSS SR Digital ground on VSS_HV pins — 0 0 V

Voltage on VDD_HV pins with respect to
VDD SR — –0.3 6.0 V
ground (VSS)
Voltage on VSS_LV (low voltage digital supply)
VSS_LV SR — VSS – 0.1 VSS + 0.1 V
pins with respect to ground (VSS)

Voltage on VDD_BV (regulator supply) pin with — –0.3 6.0

VDD_BV SR V
respect to ground (VSS) Relative to VDD –0.3 VDD + 0.3
Voltage on VSS_HV_ADC0, VSS_HV_ADC1
VSS_ADC SR (ADC reference) pins with respect to ground — VSS – 0.1 VSS + 0.1 V
(VSS)
Voltage on VDD_HV_ADC0, VDD_HV_ADC1 — –0.3 6.0
VDD_ADC SR (ADC reference) pins with respect to ground V
(VSS) Relative to VDD VDD0.3 VDD + 0.3

Voltage on any GPIO pin with respect to — –0.3 6.0

VIN SR V
ground (VSS) Relative to VDD — VDD + 0.3
Injected input current on any pin during
IINJPAD SR — –10 10
overload condition
mA
Absolute sum of all injected input currents
IINJSUM SR — –50 50
during overload condition
VDD = 5.0 V ± 10%,
— 70
Sum of all the static I/O current within a supply PAD3V5V = 0
IAVGSEG SR mA
segment V = 3.3 V ± 10%,
DD — 64
PAD3V5V = 1
TSTORAGE SR Storage temperature — –55 150 °C

Note: Stresses exceeding the recommended absolute maximum ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification are not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS),
the voltage on pins with respect to ground (VSS) must not exceed the recommended values.

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4.4 Recommended operating conditions

Table 13. Recommended operating conditions (3.3 V)
Value
Symbol Parameter Conditions Unit
Min Max

VSS SR Digital ground on VSS_HV pins — 0 0 V

Voltage on VDD_HV pins with respect to
VDD(1) SR — 3.0 3.6 V
ground (VSS)
Voltage on VSS_LV (low voltage digital
VSS_LV(2) SR — VSS 0.1 VSS + 0.1 V
supply) pins with respect to ground (VSS)

Voltage on VDD_BV pin (regulator supply) — 3.0 3.6

VDD_BV(3) SR V
with respect to ground (VSS) Relative to VDD VDD 0.1 VDD + 0.1
Voltage on VSS_HV_ADC0,
VSS_ADC SR VSS_HV_ADC1 (ADC reference) pin with — VSS 0.1 VSS + 0.1 V
respect to ground (VSS)
Voltage on VDD_HV_ADC0, — 3.0(5) 3.6
VDD_ADC (4) SR VDD_HV_ADC1 (ADC reference) with V
respect to ground (VSS) Relative to VDD VDD 0.1 VDD + 0.1

Voltage on any GPIO pin with respect to — VSS 0.1 —

VIN SR V
ground (VSS) Relative to VDD — VDD + 0.1
Injected input current on any pin during
IINJPAD SR — 5 5
overload condition
mA
Absolute sum of all injected input currents
IINJSUM SR — 50 50
during overload condition
250 x 103
V/s
TVDD SR VDD slope to ensure correct power up(6) — 3.0(7) (0.25
[V/µs])
1. 100 nF capacitance needs to be provided between each VDD/VSS pair.
2. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
3. 470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics). Supply ramp slope on VDD_BV should always be faster or equal to slope
of VDD_HV. Otherwise, device may enter regulator bypass mode if slope on VDD_BV is slower.
4. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
5. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical
characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is
reset.
6. Guaranteed by device validation.
7. Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH).

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Table 14. Recommended operating conditions (5.0 V)

Value
Symbol Parameter Conditions Unit
Min Max

S
VSS Digital ground on VSS_HV pins — 0 0 V
R

S Voltage on VDD_HV pins with respect to ground — 4.5 5.5

VDD(1) V
R (VSS) Voltage drop(2) 3.0 5.5
S Voltage on VSS_LV (low voltage digital supply)
VSS_LV(3) — VSS  0.1 VSS + 0.1 V
R pins with respect to ground (VSS)
— 4.5 5.5
S Voltage on VDD_BV pin (regulator supply) with
VDD_BV(4) Voltage drop(2) 3.0 5.5 V
R respect to ground (VSS)
Relative to VDD 3.0 VDD + 0.1
Voltage on VSS_HV_ADC0, VSS_HV_ADC1
S
VSS_ADC (ADC reference) pin with respect to ground — VSS  0.1 VSS + 0.1 V
R
(VSS)
— 4.5 5.5
(5) S Voltage on VDD_HV_ADC0, VDD_HV_ADC1 (2)
VDD_ADC Voltage drop 3.0 5.5 V
R (ADC reference) with respect to ground (VSS)
Relative to VDD VDD  0.1 VDD + 0.1

S Voltage on any GPIO pin with respect to ground — VSS  0.1 —

VIN V
R (VSS) Relative to VDD — VDD + 0.1
S Injected input current on any pin during
IINJPAD — 5 5
R overload condition
mA
S Absolute sum of all injected input currents
IINJSUM — 50 50
R during overload condition
250 x 103
S V/s
TVDD VDD slope to ensure correct power up(6) — 3.0(7) (0.25
R
[V/µs])
1. 100 nF capacitance needs to be provided between each VDD/VSS pair.
2. Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain analog
electrical characteristics will not be guaranteed to stay within the stated limits.
3. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
4. 470 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics). While the supply voltage ramps up, the slope on VDD_BV should be less
than 0.9VDD_HV in order to ensure the device does not enter regulator bypass mode.
5. 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
6. Guaranteed by device validation.
7. Minimum value of TVDD must be guaranteed until VDD reaches 2.6 V (maximum value of VPORH).

Note: RAM data retention is guaranteed with VDD_LV not below 1.08 V.

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4.5 Thermal characteristics

4.5.1 External ballast resistor recommendations

External ballast resistor on VDD_BV pin helps in reducing the overall power dissipation inside
the device. This resistor is required only when maximum power consumption exceeds the
limit imposed by package thermal characteristics.
As stated in Table 15 LQFP thermal characteristics, considering a thermal resistance of
LQFP144 as 48.3 °C/W, at ambient temperature TA = 125 °C, the junction temperature Tj
will cross 150 °C if the total power dissipation is greater than (150 – 125)/48.3 = 517 mW.
Therefore, the total device current IDDMAX at 125 °C/5.5 V must not exceed 94.1 mA (i.e.,
PD/VDD). Assuming an average IDD(VDD_HV) of 15–20 mA consumption typically during
device RUN mode, the LV domain consumption IDD(VDD_BV) is thus limited to IDDMAX –
IDD(VDD_HV), i.e., 80 mA.
Therefore, respecting the maximum power allowed as explained in Section 4.5.2: Package
thermal characteristics, it is recommended to use this resistor only in the 125 °C/5.5 V
operating corner as per the following guidelines:
 If IDD(VDD_BV) < 80 mA, then no resistor is required.
 If 80 mA < IDD(VDD_BV) < 90 mA, then 4  resistor can be used.
 If IDD(VDD_BV) > 90 mA, then 8  resistor can be used.
Using resistance in the range of 4–8 , the gain will be around 10–20% of total consumption
on VDD_BV. For example, if 8  resistor is used, then power consumption when IDD(VDD_BV)
is 110 mA is equivalent to power consumption when IDD(VDD_BV) is 90 mA (approximately)
when resistor not used.
In order to ensure correct power up, the minimum VDD_BV to be guaranteed is 30 ms/V. If
the supply ramp is slower than this value, then LVDHV3B monitoring ballast supply VDD_BV
pin gets triggered leading to device reset. Until the supply reaches certain threshold, this low
voltage detector (LVD) generates destructive reset event in the system. This threshold
depends on the maximum IDD(VDD_BV) possible across the external resistor.

4.5.2 Package thermal characteristics

Table 15. LQFP thermal characteristics(1)

Value
Symbol C Parameter Conditions(2) Pin count Unit
Min Typ Max

100 — — 64
Single-layer board — 1s 144 — — 64

Thermal resistance, junction-to- 176 — — 64

RJA CC D °C/W
ambient natural convection(3) 100 — — 49.7
Four-layer board — 2s2p 144 — — 48.3
176 — — 47.3

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Table 15. LQFP thermal characteristics(1) (continued)

Value
Symbol C Parameter Conditions(2) Pin count Unit
Min Typ Max

100 — — 36
Single-layer board — 1s 144 — — 38

Thermal resistance, junction-to- 176 — — 38

RJB CC °C/W
board(4) 100 — — 33.6
Four-layer board — 2s2p 144 — — 33.4
176 — — 33.4
100 — — 23
Single-layer board — 1s 144 — — 23

Thermal resistance, junction-to- 176 — — 23

RJC CC °C/W
case(5) 100 — — 19.8
Four-layer board — 2s2p 144 — — 19.2
176 — — 18.8
1. Thermal characteristics are targets based on simulation.
2. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C.
3. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA.
4. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
the specified package. When Greek letters are not available, the symbols are typed as RthJB.
5. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer. When Greek letters
are not available, the symbols are typed as RthJC.

4.5.3 Power considerations

The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using
Equation 1:

Equation 1 TJ = TA + (PD x RJA)

Where:
TA is the ambient temperature in °C.
RJA is the package junction-to-ambient thermal resistance, in °C/W.
PD is the sum of PINT and PI/O (PD = PINT + PI/O).
PINT is the product of IDD and VDD, expressed in watts. This is the chip internal
power.
PI/O represents the power dissipation on input and output pins; user determined.
Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand,
PI/O may be significant, if the device is configured to continuously drive external modules
and/or memories.
An approximate relationship between PD and TJ (if PI/O is neglected) is given by:

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Equation 2 PD = K / (TJ + 273 °C)

Therefore, solving equations <Cross Refs>1 and <Cross Refs>2:

Equation 3 K = PD x (TA + 273 °C) + RJA x PD2

Where:
K is a constant for the particular part, which may be determined from Equation 3
by measuring PD (at equilibrium) for a known TA. Using this value of K, the values
of PD and TJ may be obtained by solving equations Equation 1 and Equation 2
iteratively for any value of TA.

4.6 I/O pad electrical characteristics

4.6.1 I/O pad types

The device provides four main I/O pad types depending on the associated alternate
functions:
 Slow pads—are the most common pads, providing a good compromise between
transition time and low electromagnetic emission.
 Medium pads—provide transition fast enough for the serial communication channels
with controlled current to reduce electromagnetic emission.
 Fast pads—provide maximum speed. These are used for improved Nexus debugging
capability.
 Input only pads—are associated with ADC channels and 32 kHz low power external
crystal oscillator providing low input leakage.
Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at
the cost of reducing AC performance.

4.6.2 I/O input DC characteristics

Table 16 provides input DC electrical characteristics as described in Figure 6.

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Figure 6. I/O input DC electrical characteristics definition

VIN
VDD

VIH

VHYS

VIL

PDIx = ‘1
(GPDI register of SIUL)

PDIx = ‘0’

Table 16. I/O input DC electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Input high level CMOS (Schmitt

VIH SR P — 0.65VDD — VDD + 0.4
Trigger)
Input low level CMOS (Schmitt
VIL SR P — 0.4 — 0.35VDD V
Trigger)
Input hysteresis CMOS (Schmitt
VHYS CC C — 0.1VDD — —
Trigger)
D TA = 40 °C — 2 200
D TA = 25 °C — 2 200
No injection on
ILKG CC D Digital input leakage TA = 85 °C — 5 300 nA
adjacent pin
D TA = 105 °C — 12 500
P TA = 125 °C — 70 1000
(2)
WFI SR P Wakeup input filtered pulse — — — 40 ns
WNFI(2
) SR P Wakeup input not filtered pulse — 1000 — — ns

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage.

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4.6.3 I/O output DC characteristics

The following tables provide DC characteristics for bidirectional pads:
 Table 17 provides weak pull figures. Both pull-up and pull-down resistances are
supported.
 Table 18 provides output driver characteristics for I/O pads when in SLOW
configuration.
 Table 19 provides output driver characteristics for I/O pads when in MEDIUM
configuration.
 Table 20 provides output driver characteristics for I/O pads when in FAST
configuration.

Table 17. I/O pull-up/pull-down DC electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

P PAD3V5V = 0 10 — 150
Weak pull-up current VIN = VIL, VDD = 5.0 V ± 10% PAD3V5V =
|IWPU| CC C 10 — 250 µA
absolute value 1(2)
P VIN = VIL, VDD = 3.3 V ± 10% PAD3V5V = 1 10 — 150
P PAD3V5V = 0 10 — 150
Weak pull-down current VIN = VIH, VDD = 5.0 V ± 10%
|IWPD| CC C PAD3V5V = 1 10 — 250 µA
absolute value
P VIN = VIH, VDD = 3.3 V ± 10% PAD3V5V = 1 10 — 150
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 18. SLOW configuration output buffer electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

IOH = 2 mA,
VDD = 5.0 V ± 10%,
P 0.8VDD — —
PAD3V5V = 0
(recommended)
IOH = 2 mA,
C Output high level
VOH C Push Pull VDD = 5.0 V ± 10%, 0.8VDD — — V
C SLOW configuration
PAD3V5V = 1(2)
IOH = 1 mA,
VDD = 3.3 V ± 10%,
C VDD0.8 — —
PAD3V5V = 1
(recommended)

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Table 18. SLOW configuration output buffer electrical characteristics (continued)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

IOL = 2 mA,
VDD = 5.0 V ± 10%,
P — — 0.1VDD
PAD3V5V = 0
(recommended)
IOL = 2 mA,
C Output low level
VOL C Push Pull VDD = 5.0 V ± 10%, — — 0.1VDD V
C SLOW configuration
PAD3V5V = 1(2)
IOL = 1 mA,
VDD = 3.3 V ± 10%,
C — — 0.5
PAD3V5V = 1
(recommended)
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 19. MEDIUM configuration output buffer electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

IOH = 3.8 mA,

C 0.8VDD — —
VDD = 5.0 V ± 10%, PAD3V5V = 0
IOH = 2 mA,
P VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD — —
(recommended)
Output high level I = 1 mA,
VOH CC C Push Pull OH 0.8VDD — — V
MEDIUM configuration VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
IOH = 1 mA,
C VDD = 3.3 V ± 10%, PAD3V5V = 1 VDD 0.8 — —
(recommended)
IOH = 100 µA,
C 0.8VDD — —
VDD = 5.0 V ± 10%, PAD3V5V = 0
IOL = 3.8 mA,
C — — 0.2VDD
VDD = 5.0 V ± 10%, PAD3V5V = 0
IOL = 2 mA,
P VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.1VDD
(recommended)
Output low level I = 1 mA,
VOL CC C Push Pull OL — — 0.1VDD V
MEDIUM configuration VDD = 5.0 V ± 10%, PAD3V5V = 1(2)
IOL = 1 mA,
C VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 0.5
(recommended)
IOL = 100 µA,
C — — 0.1VDD
VDD = 5.0 V ± 10%, PAD3V5V = 0

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1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 20. FAST configuration output buffer electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

IOH = 14 mA,

VDD = 5.0 V ± 10%,
P 0.8VDD — —
PAD3V5V = 0
(recommended)
Output high level IOH = 7 mA,
C
VOH C FAST Push Pull VDD = 5.0 V ± 10%, 0.8VDD — — V
C
configuration PAD3V5V = 1(2)
IOH = 11 mA,
VDD = 3.3 V ± 10%, VDD 
C — —
PAD3V5V = 1 0.8
(recommended)
IOL = 14 mA,
VDD = 5.0 V ± 10%,
P — — 0.1VDD
PAD3V5V = 0
(recommended)
Output low level IOL = 7 mA,
C
VOL C FAST Push Pull VDD = 5.0 V ± 10%, — — 0.1VDD V
C
configuration PAD3V5V = 1(2)
IOL = 11 mA,
VDD = 3.3 V ± 10%,
C — — 0.5
PAD3V5V = 1
(recommended)
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

4.6.4 Output pin transition times

Table 21. Output pin transition times

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

D CL = 25 pF — — 50
VDD = 5.0 V ± 10%,
T CL = 50 pF — — 100
PAD3V5V = 0
D Output transition time output pin(2) CL = 100 pF — — 125
ttr CC  ns
D SLOW configuration C = 25 pF
L — — 50
VDD = 3.3 V ± 10%,
T CL = 50 pF — — 100
PAD3V5V = 1
D CL = 100 pF — — 125

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Table 21. Output pin transition times (continued)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

D CL = 25 pF — — 10
VDD = 5.0 V ± 10%,
T CL = 50 pF PAD3V5V = 0 — — 20
SIUL.PCRx.SRC = 1
D Output transition time output pin(2)CL = 100 pF — — 40
ttr CC ns
D MEDIUM configuration C = 25 pF
L — — 12
VDD = 3.3 V ± 10%,
T CL = 50 pF PAD3V5V = 1 — — 25
SIUL.PCRx.SRC = 1
D CL = 100 pF — — 40
CL = 25 pF — — 4
VDD = 5.0 V ± 10%,
CL = 50 pF — — 6
PAD3V5V = 0
Output transition time output pin(2)CL = 100 pF — — 12
ttr CC D ns
FAST configuration C = 25 pF — — 4
L
VDD = 3.3 V ± 10%,
CL = 50 pF — — 7
PAD3V5V = 1
CL = 100 pF — — 12
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. CL includes device and package capacitances (CPKG < 5 pF).

4.6.5 I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is
associated to a VDD/VSS supply pair as described in Table 22.
Table 23 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment
should remain below the IAVGSEG maximum value.

Table 22. I/O supply segments

Supply segment
Package
1 2 3 4 5 6 7 8

LBGA208 MDOn
(1) Equivalent to LQFP176 segment pad distribution MCKO
/MSEO
pin7 – pin28 – pin59 – pin86 – pin124 – pin151 –
LQFP176 — —
pin27 pin57 pin85 pin123 pin150 pin6
pin20 – pin51 – pin100 – pin 123 –
LQFP144 — — — —
pin49 pin99 pin122 pin19
pin16 – pin37 – pin70 – pin84 –
LQFP100 — — — —
pin35 pin69 pin83 pin15
1. LBGA208 available only as development package for Nexus2+.

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Table 23. I/O consumption

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

VDD = 5.0 V ± 10%,

— — 20
Dynamic I/O current for PAD3V5V = 0
ISWTSLW(2) CC D CL = 25 pF mA
SLOW configuration VDD = 3.3 V ± 10%,
— — 16
PAD3V5V = 1
VDD = 5.0 V ± 10%,
— — 29
Dynamic I/O current for PAD3V5V = 0
ISWTMED(2) CC D CL = 25 pF mA
MEDIUM configuration VDD = 3.3 V ± 10%,
— — 17
PAD3V5V = 1
VDD = 5.0 V ± 10%,
— — 110
Dynamic I/O current for PAD3V5V = 0
ISWTFST(2) CC D CL = 25 pF mA
FAST configuration VDD = 3.3 V ± 10%,
— — 50
PAD3V5V = 1
CL = 25 pF, 2 MHz — — 2.3
VDD = 5.0 V ± 10%,
CL = 25 pF, 4 MHz — — 3.2
PAD3V5V = 0
Root mean square I/O CL = 100 pF, 2 MHz — — 6.6
IRMSSLW CC D current for SLOW mA
configuration CL = 25 pF, 2 MHz — — 1.6
VDD = 3.3 V ± 10%,
CL = 25 pF, 4 MHz — — 2.3
PAD3V5V = 1
CL = 100 pF, 2 MHz — — 4.7
CL = 25 pF, 13 MHz — — 6.6
VDD = 5.0 V ± 10%,
CL = 25 pF, 40 MHz — — 13.4
PAD3V5V = 0
Root mean square I/O CL = 100 pF, 13 MHz — — 18.3
IRMSMED CC D current for MEDIUM mA
configuration CL = 25 pF, 13 MHz — — 5
VDD = 3.3 V ± 10%,
CL = 25 pF, 40 MHz — — 8.5
PAD3V5V = 1
CL = 100 pF, 13 MHz — — 11
CL = 25 pF, 40 MHz — — 22
VDD = 5.0 V ± 10%,
CL = 25 pF, 64 MHz — — 33
PAD3V5V = 0
Root mean square I/O CL = 100 pF, 40 MHz — — 56
IRMSFST CC D current for FAST mA
configuration CL = 25 pF, 40 MHz — — 14
VDD = 3.3 V ± 10%,
CL = 25 pF, 64 MHz — — 20
PAD3V5V = 1
CL = 100 pF, 40 MHz — — 35
Sum of all the static I/O VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 70
IAVGSEG SR D current within a supply mA
segment VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 65

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to125 °C, unless otherwise specified
2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.

Table 24 provides the weight of concurrent switching I/Os.

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Due to the dynamic current limitations, the sum of the weight of concurrent switching I/Os on
a single segment must not exceed 100% to ensure device functionality.

Table 24. I/O weight(1)

LQFP176 LQFP144/100
Supply segment
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
Pad
LQFP LQFP LQFP SRC(2) =
SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
176 144 100 0

PB[3] 5% — 6% — 13% — 15% —

PC[9] 4% — 5% — 13% — 15% —
4 4
6 PC[14] 4% — 4% — 13% — 15% —
PC[15] 3% 4% 4% 4% 12% 18% 15% 16%
— — PJ[4] 3% 4% 3% 3% — — — —
— — PH[15] 2% 3% 3% 3% — — — —
— — PH[13] 3% 4% 3% 4% — — — —
— — PH[14] 3% 4% 4% 4% — — — —
— — PI[6] 4% — 4% — — — — —
— — PI[7] 4% — 4% — — — — —
— PG[5] 4% — 5% — 10% — 12% —
— PG[4] 4% 6% 5% 5% 9% 13% 11% 12%
— PG[3] 4% — 5% — 9% — 11% —
— PG[2] 4% 6% 5% 5% 9% 12% 10% 11%
1
PA[2] 4% — 5% — 8% — 10% —
PE[0] 4% — 5% — 8% — 9% —
4 PA[1] 4% — 5% — 8% — 9% —
PE[1] 4% 6% 5% 6% 7% 10% 9% 9%
4 PE[8] 4% 6% 5% 6% 7% 10% 8% 9%
PE[9] 4% — 5% — 6% — 8% —
PE[10] 4% — 5% — 6% — 7% —
PA[0] 4% 6% 5% 5% 6% 8% 7% 7%
PE[11] 4% — 5% — 5% — 6% —

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Table 24. I/O weight(1) (continued)

LQFP176 LQFP144/100
Supply segment
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
Pad
LQFP LQFP LQFP SRC(2) =
SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
176 144 100 0

— PG[9] 9% — 10% — 9% — 10% —

— PG[8] 9% — 11% — 9% — 11% —
PC[11] 9% — 11% — 9% — 11% —
1
PC[10] 9% 13% 11% 12% 9% 13% 11% 12%
— PG[7] 9% — 11% — 9% — 11% —
— PG[6] 10% 14% 11% 12% 10% 14% 11% 12%
PB[0] 10% 14% 12% 12% 10% 14% 12% 12%
1
PB[1] 10% — 12% — 10% — 12% —
— PF[9] 10% — 12% — 10% — 12% —
— PF[8] 10% 14% 12% 13% 10% 14% 12% 13%
2 1 — PF[12] 10% 15% 12% 13% 10% 15% 12% 13%
PC[6] 10% — 12% — 10% — 12% —
1
PC[7] 10% — 12% — 10% — 12% —
— PF[10] 10% 14% 11% 12% 10% 14% 11% 12%
— PF[11] 9% — 11% — 9% — 11% —
1 PA[15] 8% 12% 10% 10% 8% 12% 10% 10%
— PF[13] 8% — 10% — 8% — 10% —
PA[14] 8% 11% 9% 10% 8% 11% 9% 10%
PA[4] 7% — 9% — 7% — 9% —
1
PA[13] 7% 10% 8% 9% 7% 10% 8% 9%
PA[12] 7% — 8% — 7% — 8% —

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Table 24. I/O weight(1) (continued)

LQFP176 LQFP144/100
Supply segment
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
Pad
LQFP LQFP LQFP SRC(2) =
SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
176 144 100 0

PB[9] 1% — 1% — 1% — 1% —
2 PB[8] 1% — 1% — 1% — 1% —
PB[10] 5% — 6% — 6% — 7% —
— PF[0] 5% — 6% — 6% — 8% —
— PF[1] 5% — 6% — 7% — 8% —
2 — PF[2] 6% — 7% — 7% — 9% —
— PF[3] 6% — 7% — 8% — 9% —
— PF[4] 6% — 7% — 8% — 10% —
— PF[5] 6% — 7% — 9% — 10% —
— PF[6] 6% — 7% — 9% — 11% —
— PF[7] 6% — 7% — 9% — 11% —
— — PJ[3] 6% — 7% — — — — —
3 — — PJ[2] 6% — 7% — — — — —
— — PJ[1] 6% — 7% — — — — —
— — PJ[0] 6% — 7% — — — — —
— — PI[15] 6% — 7% — — — — —
— — PI[14] 6% — 7% — — — — —
PD[0] 1% — 1% — 1% — 1% —
PD[1] 1% — 1% — 1% — 1% —
PD[2] 1% — 1% — 1% — 1% —
PD[3] 1% — 1% — 1% — 1% —
2 2
PD[4] 1% — 1% — 1% — 1% —
PD[5] 1% — 1% — 1% — 1% —
PD[6] 1% — 1% — 1% — 2% —
PD[7] 1% — 1% — 1% — 2% —

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Table 24. I/O weight(1) (continued)

LQFP176 LQFP144/100
Supply segment
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
Pad
LQFP LQFP LQFP SRC(2) =
SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
176 144 100 0

PD[8] 1% — 1% — 1% — 2% —
PB[4] 1% — 1% — 1% — 2% —
PB[5] 1% — 1% — 1% — 2% —
PB[6] 1% — 1% — 1% — 2% —
4 2 2
PB[7] 1% — 1% — 1% — 2% —
PD[9] 1% — 1% — 1% — 2% —
PD[10] 1% — 1% — 1% — 2% —
PD[11] 1% — 1% — 1% — 2% —

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Table 24. I/O weight(1) (continued)

LQFP176 LQFP144/100
Supply segment
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
Pad
LQFP LQFP LQFP SRC(2) =
SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
176 144 100 0

— — PB[11] 1% — 1% — — — — —
— — PD[12] 11% — 13% — — — — —
PB[12] 11% — 13% — 15% — 17% —
PD[13] 11% — 13% — 14% — 17% —
PB[13] 11% — 13% — 14% — 17% —
2 2 PD[14] 11% — 13% — 14% — 17% —
PB[14] 11% — 13% — 14% — 16% —
PD[15] 11% — 13% — 13% — 16% —
PB[15] 11% — 13% — 13% — 15% —
— — PI[8] 10% — 12% — — — — —
— — PI[9] 10% — 12% — — — — —
— — PI[10] 10% — 12% — — — — —
4
— — PI[11] 10% — 12% — — — — —
— — PI[12] 10% — 12% — — — — —
— — PI[13] 10% — 11% — — — — —
2 PA[3] 9% — 11% — 11% — 13% —
— PG[13] 9% 13% 11% 11% 10% 14% 12% 13%
— PG[12] 9% 13% 10% 11% 10% 14% 12% 12%
— PH[0] 6% 8% 7% 7% 6% 9% 7% 8%
2 — PH[1] 6% 8% 7% 7% 6% 8% 7% 7%
— PH[2] 5% 7% 6% 6% 5% 7% 6% 7%
— PH[3] 5% 7% 5% 6% 5% 7% 6% 6%
— PG[1] 4% — 5% — 4% — 5% —
— PG[0] 4% 5% 4% 5% 4% 5% 4% 5%

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Table 24. I/O weight(1) (continued)

LQFP176 LQFP144/100
Supply segment
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
Pad
LQFP LQFP LQFP SRC(2) =
SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
176 144 100 0

— PF[15] 4% — 4% — 4% — 4% —
— PF[14] 4% 6% 5% 5% 4% 6% 5% 5%
— PE[13] 4% — 5% — 4% — 5% —
PA[7] 5% — 6% — 5% — 6% —
PA[8] 5% — 6% — 5% — 6% —
PA[9] 6% — 7% — 6% — 7% —
3
PA[10] 6% — 8% — 6% — 8% —
3 PA[11] 8% — 9% — 8% — 9% —
PE[12] 8% — 9% — 8% — 9% —
— PG[14] 8% — 9% — 8% — 9% —
— PG[15] 8% 11% 9% 10% 8% 11% 9% 10%
— PE[14] 8% — 9% — 8% — 9% —
5 — PE[15] 8% 11% 9% 10% 8% 11% 9% 10%
— PG[10] 8% — 9% — 8% — 9% —
— PG[11] 7% 11% 9% 9% 7% 11% 9% 9%
— — PH[11] 7% 10% 9% 9% — — — —
— — PH[12] 7% 10% 8% 9% — — — —
— — PI[5] 7% — 8% — — — — —
— — PI[4] 7% — 8% — — — — —
PC[3] 6% — 8% — 6% — 8% —
PC[2] 6% 8% 7% 7% 6% 8% 7% 7%
PA[5] 6% 8% 7% 7% 6% 8% 7% 7%
3 3
PA[6] 5% — 6% — 5% — 6% —
PH[10] 5% 7% 6% 6% 5% 7% 6% 6%
PC[1] 5% 19% 5% 13% 5% 19% 5% 13%

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Table 24. I/O weight(1) (continued)

LQFP176 LQFP144/100
Supply segment
Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V
Pad
LQFP LQFP LQFP SRC(2) =
SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
176 144 100 0

PC[0] 6% 9% 7% 8% 7% 10% 8% 8%
PH[9] 7% — 8% — 7% — 9% —
PE[2] 7% 10% 8% 9% 8% 11% 9% 10%
PE[3] 7% 10% 9% 9% 8% 12% 10% 10%
4
PC[5] 7% 11% 9% 9% 8% 12% 10% 11%
PC[4] 8% 11% 9% 10% 9% 13% 10% 11%
PE[4] 8% 11% 9% 10% 9% 13% 11% 12%
4 PE[5] 8% 11% 10% 10% 9% 14% 11% 12%
— PH[4] 8% 12% 10% 10% 10% 14% 12% 12%
— PH[5] 8% — 10% — 10% — 12% —
— PH[6] 8% 12% 10% 11% 10% 15% 12% 13%
6 — PH[7] 9% 12% 10% 11% 11% 15% 13% 13%
— PH[8] 9% 12% 10% 11% 11% 16% 13% 14%
PE[6] 9% 12% 10% 11% 11% 16% 13% 14%
4
PE[7] 9% 12% 10% 11% 11% 16% 14% 14%
— — PI[3] 9% — 10% — — — — —
— — PI[2] 9% — 10% — — — — —
— — PI[1] 9% — 10% — — — — —
— — PI[0] 9% — 10% — — — — —
PC[12] 8% 12% 10% 11% 12% 18% 15% 16%
PC[13] 8% — 10% — 13% — 15% —
4 4
PC[8] 8% — 10% — 13% — 15% —
PB[2] 8% 11% 9% 10% 13% 18% 15% 16%
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. SRC: “Slew Rate Control” bit in SIU_PCRx.

4.7 RESET electrical characteristics

The device implements a dedicated bidirectional RESET pin.

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Figure 7. Start-up reset requirements

VDD

VDDMIN

RESET

VIH

VIL

device reset forced by RESET device start-up phase

Figure 8. Noise filtering on reset signal

VRESET

hw_rst
VDD
‘1’

VIH

VIL

‘0’
filtered by filtered by filtered by unknown reset
hysteresis lowpass filter lowpass filter state device under hardware reset

WFRST WFRST
WNFRST

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Table 25. Reset electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Input High Level CMOS

VIH SR P — 0.65VDD — VDD + 0.4 V
(Schmitt Trigger)
Input low Level CMOS
VIL SR P — 0.4 — 0.35VDD V
(Schmitt Trigger)
Input hysteresis CMOS 
VHYS CC C — 0.1VDD — — V
(Schmitt Trigger)
Push Pull, IOL = 2 mA,
VDD = 5.0 V ± 10%, PAD3V5V = 0 — — 0.1VDD
(recommended)
Push Pull, IOL = 1 mA,
VOL CC P Output low level VDD = 5.0 V ± 10%, PAD3V5V = — — 0.1VDD V
1(2)
Push Pull, IOL = 1 mA,
VDD = 3.3 V ± 10%, PAD3V5V = 1 — — 0.5
(recommended)
CL = 25 pF,
— — 10
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL = 50 pF,
— — 20
VDD = 5.0 V ± 10%, PAD3V5V = 0
CL = 100 pF,
— — 40
Output transition time output VDD = 5.0 V ± 10%, PAD3V5V = 0
ttr CC D ns
pin(3) MEDIUM configuration CL = 25 pF,
— — 12
VDD = 3.3 V ± 10%, PAD3V5V = 1
CL = 50 pF,
— — 25
VDD = 3.3 V ± 10%, PAD3V5V = 1
CL = 100 pF,
— — 40
VDD = 3.3 V ± 10%, PAD3V5V = 1
WFRST SR P RESET input filtered pulse — — — 40 ns
WNFRST SR P RESET input not filtered pulse — 1000 — — ns
P VDD = 3.3 V ± 10%, PAD3V5V = 1 10 — 150
D Weak pull-up current absolute VDD = 5.0 V ± 10%, PAD3V5V = 0 10 — 150
|IWPU| CC µA
value
VDD = 5.0 V ± 10%, PAD3V5V =
P 10 — 250
1(4)
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of the
device reference manual).
3. CL includes device and package capacitance (CPKG < 5 pF).
4. The configuration PAD3V5 = 1 when VDD = 5 V is only transient configuration during power-up. All pads but RESET and
Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

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4.8 Power management electrical characteristics

4.8.1 Voltage regulator electrical characteristics

The device implements an internal voltage regulator to generate the low voltage core supply
VDD_LV from the high voltage ballast supply VDD_BV. The regulator itself is supplied by the
common I/O supply VDD. The following supplies are involved:
 HV: High voltage external power supply for voltage regulator module. This must be
provided externally through VDD power pin.
 BV: High voltage external power supply for internal ballast module. This must be
provided externally through VDD_BV power pin. Voltage values should be aligned with
VDD.
 LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is
generated by the internal voltage regulator but provided outside to connect stability
capacitor. It is further split into four main domains to ensure noise isolation between
critical LV modules within the device:
– LV_COR: Low voltage supply for the core. It is also used to provide supply for
FMPLL through double bonding.
– LV_CFLA: Low voltage supply for code flash module. It is supplied with dedicated
ballast and shorted to LV_COR through double bonding.
– LV_DFLA: Low voltage supply for data flash module. It is supplied with dedicated
ballast and shorted to LV_COR through double bonding.
– LV_PLL: Low voltage supply for FMPLL. It is shorted to LV_COR through double
bonding.

Figure 9. Voltage regulator capacitance connection

CREG2 (LV_COR/LV_CFLA)

VDD

VSS_LV VDD_LV
VDD_BV

VREF
VDD_BV
CDEC1 (Ballast decoupling)

CREG1 (LV_COR/LV_DFLA)

VDD_LV
VDD_LVn
DEVICE

Voltage Regulator

I
VSS_LV

VSS_LVn
VSS_LV VDD_LV VSS VDD
DEVICE

CREG3 CDEC2
(LV_COR/LV_PLL) (supply/IO decoupling)

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The internal voltage regulator requires external capacitance (CREGn) to be connected to the
device in order to provide a stable low voltage digital supply to the device. Capacitances
should be placed on the board as near as possible to the associated pins. Care should also
be taken to limit the serial inductance of the board to less than 5 nH.
Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply
pairs to ensure stable voltage (see Section 4.4: Recommended operating conditions).

Table 26. Voltage regulator electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Internal voltage regulator external

CREGn SR — — 200 — 500 nF
capacitance
Stability capacitor equivalent serial Range:
RREG SR — — — 0.2 W
resistance 10 kHz to 20 MHz
VDD_BV/VSS_LV pair:
100(3) —
VDD_BV = 4.5 V to 5.5 V
CDEC1 SR — Decoupling capacitance(2) ballast 470(4) nF
VDD_BV/VSS_LV pair:
400 —
VDD_BV = 3 V to 3.6 V
Decoupling capacitance regulator
CDEC2 SR — VDD/VSS pair 10 100 — nF
supply
T Before exiting from reset — 1.32 —
VMREG CC Main regulator output voltage V
P After trimming 1.16 1.28 —
Main regulator current provided to
IMREG SR — — — — 150 mA
VDD_LV domain

Main regulator module current IMREG = 200 mA — — 2

IMREGINT CC D mA
consumption IMREG = 0 mA — — 1
VLPREG CC P Low-power regulator output voltage After trimming 1.16 1.28 — V
Low-power regulator current
ILPREG SR — — — — 15 mA
provided to VDD_LV domain
ILPREG = 15 mA;
D — — 600
Low-power regulator module current TA = 55 °C
ILPREGINT CC µA
consumption ILPREG = 0 mA;
— — 5 —
TA = 55 °C
Ultra low power regulator output
VULPREG CC P After trimming 1.16 1.28 — V
voltage
Ultra low power regulator current
IULPREG SR — — — — 5 mA
provided to VDD_LV domain
IULPREG = 5 mA;
— — 100
Ultra low power regulator module TA = 55 °C
IULPREGINT CC D µA
current consumption IULPREG = 0 mA;
— 2 —
TA = 55 °C
In-rush average current on VDD_BV
IDD_BV CC D — — — 300(6) mA
during power-up(5)

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1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical
value is in the range of 470 nF.
3. This value is acceptable to guarantee operation from 4.5 V to 5.5 V.
4. External regulator and capacitance circuitry must be capable of providing IDD_BV while maintaining supply VDD_BV in
operating range.
5. In-rush average current is seen only for short time during power-up and on standby exit (maximum 20 µs, depending on
external capacitances to be loaded).
6. The duration of the in-rush current depends on the capacitance placed on LV pins. BV decoupling capacitors must be sized
accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.

4.8.2 Low voltage detector electrical characteristics

The device implements a power-on reset (POR) module to ensure correct power-up
initialization, as well as five low voltage detectors (LVDs) to monitor the VDD and the VDD_LV
voltage while device is supplied:
 POR monitors VDD during the power-up phase to ensure device is maintained in a safe
reset state (refer to RGM Destructive Event Status (RGM_DES) Register flag F_POR
in device reference manual)
 LVDHV3 monitors VDD to ensure device reset below minimum functional supply (refer
to RGM Destructive Event Status (RGM_DES) Register flag F_LVD27 in device
reference manual)
 LVDHV3B monitors VDD_BV to ensure device reset below minimum functional supply
(refer to RGM Destructive Event Status (RGM_DES) Register flag F_LVD27_VREG in
device reference manual)
 LVDHV5 monitors VDD when application uses device in the 5.0 V ± 10% range (refer to
RGM Functional Event Status (RGM_FES) Register flag F_LVD45 in device reference
manual)
 LVDLVCOR monitors power domain No. 1 (refer to RGM Destructive Event Status
(RGM_DES) Register flag F_LVD12_PD1 in device reference manual)
 LVDLVBKP monitors power domain No. 0 (refer to RGM Destructive Event Status
(RGM_DES) Register flag F_LVD12_PD0 in device reference manual)
Note: When enabled, power domain No. 2 is monitored through LVDLVBKP.

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Figure 10. Low voltage detector vs reset

VDD

VLVDHVxH
VLVDHVxL

RESET

Table 27. Low voltage detector electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

VPORUP SR P Supply for functional POR module 1.0 — 5.5

VPORH CC P Power-on reset threshold 1.5 — 2.6
VLVDHV3H CC T LVDHV3 low voltage detector high threshold — — 2.95
VLVDHV3L CC P LVDHV3 low voltage detector low threshold 2.6 — 2.9
VLVDHV3BH CC P LVDHV3B low voltage detector high threshold TA = 25 °C, — — 2.95
V
VLVDHV3BL CC P LVDHV3B low voltage detector low threshold after trimming 2.6 — 2.9
VLVDHV5H CC T LVDHV5 low voltage detector high threshold — — 4.5
VLVDHV5L CC P LVDHV5 low voltage detector low threshold 3.8 — 4.4
VLVDLVCORL CC P LVDLVCOR low voltage detector low threshold 1.08 — 1.16
VLVDLVBKPL CC P LVDLVBKP low voltage detector low threshold 1.08 — 1.16
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.

4.9 Power consumption

Table 28 provides DC electrical characteristics for significant application modes. These
values are indicative values; actual consumption depends on the application.

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Table 28. Power consumption on VDD_BV and VDD_HV

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

RUN mode maximum average

IDDMAX(2) CC D — — 115 140(3) mA
current
T fCPU = 8 MHz — 12 —
T fCPU = 16 MHz — 27 —
RUN mode typical average
IDDRUN(4) CC T fCPU = 32 MHz — 43 — mA
current(5)
P fCPU = 48 MHz — 56 100
P fCPU = 64 MHz — 70 125
C Slow internal RC TA = 25 °C — 10 18
IDDHALT CC HALT mode current(6) oscillator (128 kHz) mA
P running TA = 125 °C — 17 28

P TA = 25 °C — 350 900(8)
µA
D TA = 55 °C — 750 —
Slow internal RC
IDDSTOP CC D STOP mode current(7) oscillator (128 kHz) TA = 85 °C — 2 7
running
D TA = 105 °C — 4 10 mA
P TA = 125 °C — 7 14
P TA = 25 °C — 30 100
D TA = 55 °C — 75 —
Slow internal RC
IDDSTDBY2 CC D STANDBY2 mode current(9) oscillator (128 kHz) TA = 85 °C — 180 700 µA
running
D TA = 105 °C — 315 1000
P TA = 125 °C — 560 1700
T TA = 25 °C — 20 60
D TA = 55 °C — 45 —
Slow internal RC
IDDSTDBY1 CC D STANDBY1 mode current(10) oscillator (128 kHz) TA = 85 °C — 100 350 µA
running
D TA = 105 °C — 165 500
D TA = 125 °C — 280 900
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. IDDMAX is drawn only from the VDD_BV pin. Running consumption does not include I/Os toggling which is highly
dependent on the application. The given value is thought to be a worst case value with all peripherals running, and code
fetched from code flash while modify operation ongoing on data flash. Notice that this value can be significantly reduced by
application: switch off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from
RAM most used functions, use low power mode when possible.
3. Higher current may be sunk by device during power-up and standby exit. Please refer to in-rush average current in
Table 26.
4. IDDRUN is drawn only from the VDD_BV pin. RUN current measured with typical application with accesses on both Flash
and RAM.
5. Only for the “P” classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and LIN in
loop back mode, DSPI as Master, PLL as system clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and running at
max frequency, periodic SW/WDG timer reset enabled.

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6. Data Flash Power Down. Code Flash in Low Power. SIRC 128 kHz and FIRC 16 MHz on. 10 MHz XTAL clock. FlexCAN:
instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clocks gated. LINFlex: instances: 0, 1,
2 ON (clocked but not reception or transmission), instance: 3 to 9 clocks gated. eMIOS: instance: 0 ON (16 channels on
PA[0]–PA[11] and PC[12]–PC[15]) with PWM 20 kHz, instance: 1 clock gated. DSPI: instance: 0 (clocked but no
communication), instance: 1 to 5 clocks gated. RTC/API ON. PIT ON. STM ON. ADC1 OFF. ADC0 ON but no conversion
except two analog watchdogs.
7. Only for the “P” classification: No clock, FIRC 16 MHz off, SIRC 128 kHz on, PLL off, HPVreg off, ULPVreg/LPVreg on. All
possible peripherals off and clock gated. Flash in power down mode.
8. When going from RUN to STOP mode and the core consumption is > 6 mA, it is normal operation for the main regulator
module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction temperatures
exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the maximum STOP
specification by up to 2 mA. After entering stop, the application junction temperature will reduce to the ambient level and
the main regulator will be automatically switched off when the load current is below 6 mA.
9. Only for the “P” classification: ULPreg on, HP/LPVreg off, 32 KB RAM on, device configured for minimum consumption, all
possible modules switched off.
10. ULPreg on, HP/LPVreg off, 8 KB RAM on, device configured for minimum consumption, all possible modules switched off.

4.10 Flash memory electrical characteristics

4.10.1 Program/erase characteristics

Table 29 shows the program and erase characteristics.

Table 29. Program and erase specifications

Value

Symbol C Parameter Conditions Initial Unit

Typ Max
Min (1) max (3)
(2)

Code Flash 18
tdwprogram Double word (64 bits) program time(4) — 50 500 µs
Data Flash 22
Code Flash 200
t16Kpperase 16 KB block preprogram and erase time — 500 5000 ms
Data Flash 300
C
Code Flash 300
t32Kpperase C 32 KB block preprogram and erase time — 600 5000 ms
Data Flash 400
C
Code Flash 600
t128Kpperase 128 KB block preprogram and erase time — 1300 7500 ms
Data Flash 800
tesus D Erase Suspend Latency — — — 30 30 µs
Code Flash 20 — — —
tESRT C Erase Suspend Request Rate(5) ms
Data Flash 10 — — —
1. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
2. Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.
3. The maximum program and erase times occur after the specified number of program/erase cycles. These maximum values
are characterized but not guaranteed.
4. Actual hardware programming times. This does not include software overhead.
5. Time between erase suspend resume and the next erase suspend request.

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Table 30. Flash module life

Value
Symbol C Parameter Conditions Unit
Min Typ Max

Number of program/erase
cycles per block for 16 KB
P/E CC C — 100000 — — cycles
blocks over the operating
temperature range (TJ)
Number of program/erase
cycles per block for 32 KB
P/E CC C — 10000 100000 — cycles
blocks over the operating
temperature range (TJ)
Number of program/erase
cycles per block for 128 KB
P/E CC C — 1000 100000 — cycles
blocks over the operating
temperature range (TJ)
Blocks with
20 — — years
0–1000 P/E cycles
Blocks with
Minimum data retention at
1001–10000 P/E 10 — — years
Retention CC C 85 °C average ambient
cycles
temperature(1)
Blocks with
10001–100000 P/E 5 — — years
cycles
1. Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature
range.

ECC circuitry provides correction of single bit faults and is used to improve further
automotive reliability results. Some units will experience single bit corrections throughout
the life of the product with no impact to product reliability.

Table 31. Flash read access timing

Symbol C Parameter Conditions(1) Max Unit

P 2 wait states 64
fREAD CC C Maximum frequency for Flash reading 1 wait state 40 MHz
C 0 wait states 20
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.

4.10.2 Flash power supply DC characteristics

Table 32 shows the power supply DC characteristics on external supply.

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Table 32. Flash power supply DC electrical characteristics

Value
Symbol Parameter Conditions(1) Unit
Min Typ Max

ICFREAD Sum of the current consumption on Flash module read Code Flash — — 33
CC mA
IDFREAD VDD_HV and VDD_BV on read access fCPU = 64 MHz Data Flash — — 33
ICFMOD Program/Erase Code Flash — — 52
Sum of the current consumption on
on-going while reading
CC VDD_HV and VDD_BV on matrix mA
IDFMOD modification (program/erase) Flash registers Data Flash — — 33
fCPU = 64 MHz
ICFLPW Sum of the current consumption on Code Flash — — 1.1 mA
CC VDD_HV and VDD_BV during Flash low —
IDFLPW power mode Data Flash — — 900 µA

ICFPWD Sum of the current consumption on Code Flash — — 150

CC VDD_HV and VDD_BV during Flash — µA
IDFPWD power down mode Data Flash — — 150

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified.

4.10.3 Start-up/Switch-off timings

Table 33. Start-up time/Switch-off time

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

tFLARSTEXIT CC T Delay for Flash module to exit reset mode — — — 125

tFLALPEXIT CC T Delay for Flash module to exit low-power mode — — — 0.5
tFLAPDEXIT CC T Delay for Flash module to exit power-down mode — — — 30 µs
tFLALPENTRY CC T Delay for Flash module to enter low-power mode — — — 0.5
tFLAPDENTRY CC T Delay for Flash module to enter power-down mode — — — 1.5
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.

4.11 Electromagnetic compatibility (EMC) characteristics

Susceptibility tests are performed on a sample basis during product characterization.

4.11.1 Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.

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Therefore it is recommended that the user apply EMC software optimization and
prequalification tests in relation with the EMC level requested for the application.
 Software recommendations The software flowchart must include the management of
runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical data corruption (control registers...)
 Prequalification trials Most of the common failures (unexpected reset and program
counter corruption) can be reproduced by manually forcing a low state on the reset pin
or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device. When
unexpected behavior is detected, the software can be hardened to prevent
unrecoverable errors occurring (see application note Software Techniques For
Improving Microcontroller EMC Performance (AN1015)).

4.11.2 Electromagnetic interference (EMI)

The product is monitored in terms of emission based on a typical application. This emission
test conforms to the IEC61967-1 standard, which specifies the general conditions for EMI
measurements.

Table 34. EMI radiated emission measurement(1)(2)

Value
Symbol C Parameter Conditions Unit
Min Typ Max

0.15
— SR — Scan range — 1000 MHz
0
fCPU SR — Operating frequency — — 64 — MHz
LV operating
VDD_LV SR — — — 1.28 — V
voltages
VDD = 5 V, No PLL frequency dBµ
— — 18
TA = 25 °C, modulation V
LQFP144 package
SEMI CC T Peak level Test conforming to
IEC 61967-2, ± 2% PLL frequency dBµ
— — 14
modulation V
fOSC = 8 MHz/fCPU =
64 MHz
1. EMI testing and I/O port waveforms per IEC 61967-1, -2, -4.
2. For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your local
marketing representative.

4.11.3 Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.

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4.11.3.1 Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts(n + 1) supply pin). This test
conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the
application note Electrostatic Discharge Sensitivity Measurement (AN1181).

Table 35. ESD absolute maximum ratings(1)(2)

Symbol Ratings Conditions Class Max value(3) Unit

Electrostatic discharge voltage TA = 25 °C

VESD(HBM) H1C 2000
(Human Body Model) conforming to AEC-Q100-002
Electrostatic discharge voltage TA = 25 °C
VESD(MM) M2 200 V
(Machine Model) conforming to AEC-Q100-003

Electrostatic discharge voltage TA = 25 °C 500

VESD(CDM) C3A
(Charged Device Model) conforming to AEC-Q100-011 750 (corners)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification.
3. Data based on characterization results, not tested in production

4.11.3.2 Static latch-up (LU)

Two complementary static tests are required on six parts to assess the latch-up
performance:
 A supply overvoltage is applied to each power supply pin.
 A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.

Table 36. Latch-up results

Symbol Parameter Conditions Class

TA = 125 °C
LU Static latch-up class II level A
conforming to JESD 78

4.12 Fast external crystal oscillator (4 to 16 MHz) electrical

characteristics
The device provides an oscillator/resonator driver. Figure 11 describes a simple model of
the internal oscillator driver and provides an example of a connection for an oscillator or a
resonator.
Table 37 provides the parameter description of 4 MHz to 16 MHz crystals used for the
design simulations.

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Figure 11. Crystal oscillator and resonator connection scheme

EXTAL
C1

EXTAL

Crystal
XTAL
C2
DEVICE
VDD
I

EXTAL
XTAL
DEVICE

Resonator
XTAL

DEVICE

Notes:
1. XTAL/EXTAL must not be directly used to drive external circuits
2. A series resistor may be required, according to crystal oscillator supplier recommendations.

Table 37. Crystal description

Shunt
Crystal
Crystal Crystal Load on capacitance
Nominal equivalent
NDK crystal motional motional xtalin/xtalout between
frequency series
reference capacitance inductance C1 = C2 xtalout
(MHz) resistance
(Cm) fF (Lm) mH (pF)(1) and xtalin
ESR 
C0(2) (pF)

4 NX8045GB 300 2.68 591.0 21 2.93

8 300 2.46 160.7 17 3.01
10 150 2.93 86.6 15 2.91
NX5032GA
12 120 3.11 56.5 15 2.93
16 120 3.90 25.3 10 3.00
1. The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing includes all
the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.
2. The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads, package,
etc.).

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Figure 12. Fast external crystal oscillator (4 to 16 MHz) timing diagram

S_MTRANS bit (ME_GS register)

VXTAL
1/fMXOSC

VMXOSC
90%

VMXOSCOP

10%

TMXOSCSU valid internal clock

Table 38. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

S Fast external crystal

fFXOSC — — 4.0 — 16.0 MHz
R oscillator frequency
VDD = 3.3 V ± 10%,
C PAD3V5V = 1
C 2.2 — 8.2
C OSCILLATOR_MARGIN =
0
VDD = 5.0 V ± 10%,
C PAD3V5V = 0
P 2.0 — 7.4
C OSCILLATOR_MARGIN =
Fast external crystal 0 mA/
gmFXOSC oscillator
VDD = 3.3 V ± 10%, V
transconductance
C PAD3V5V = 1
C 2.7 — 9.7
C OSCILLATOR_MARGIN =
1
VDD = 5.0 V ± 10%,
C PAD3V5V = 0
C 2.5 — 9.2
C OSCILLATOR_MARGIN =
1
fOSC = 4 MHz,
OSCILLATOR_MARGIN = 1.3 — —
C Oscillation amplitude at 0
VFXOSC T V
C EXTAL fOSC = 16 MHz,
OSCILLATOR_MARGIN = 1.3 — —
1
C Oscillation operating
VFXOSCOP C — — 0.95 — V
C point

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Table 38. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics (continued)
Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

C Fast external crystal

IFXOSC(2) T — — 2 3 mA
C oscillator consumption
fOSC = 4 MHz,
OSCILLATOR_MARGIN = — — 6
C Fast external crystal 0
tFXOSCSU T ms
C oscillator start-up time fOSC = 16 MHz,
OSCILLATOR_MARGIN = — — 1.8
1
S Input high level CMOS VDD + 0.
VIH P Oscillator bypass mode 0.65VDD — V
R (Schmitt Trigger) 4
S Input low level CMOS
VIL P Oscillator bypass mode 0.4 — 0.35VDD V
R (Schmitt Trigger)
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. Stated values take into account only analog module consumption but not the digital contributor (clock tree and enabled
peripherals).

4.13 Slow external crystal oscillator (32 kHz) electrical

characteristics
The device provides a low power oscillator/resonator driver.

Figure 13. Crystal oscillator and resonator connection scheme

OSC32K_EXTAL OSC32K_EXTAL

C1
Resonator
Crystal

RP

OSC32K_XTAL OSC32K_XTAL

DEVICE C2 DEVICE

Note: OSC32_XTAL/OSC32_EXTAL must not be directly used to drive external circuits

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Figure 14. Equivalent circuit of a quartz crystal

C0

Crystal Cm Rm Lm
C1 C2
C1 C2

Table 39. Crystal motional characteristics(1)

Value
Symbol Parameter Conditions Unit
Min Typ Max

Lm Motional inductance — — 11.796 — KH

Cm Motional capacitance — — 2 — fF
Load capacitance at OSC32K_XTAL and
C1/C2 — 18 — 28 pF
OSC32K_EXTAL with respect to ground(2)
AC coupled at C0 = 2.85 pF(4) — — 65
AC coupled at C0 = 4.9 pF(4) — — 50
Rm(3) Motional resistance kW
AC coupled at C0 = 7.0 pF(4) — — 35
AC coupled at C0 = 9.0 pF(4) — — 30
1. The crystal used is Epson Toyocom MC306.
2. This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to ground. It
includes all the parasitics due to board traces, crystal and package.
3. Maximum ESR (Rm) of the crystal is 50 k
4. C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins.

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Figure 15. Slow external crystal oscillator (32 kHz) timing diagram

OSCON bit (OSC_CTL register)

VOSC32K_XTAL 1/fLPXOSC32K

VLPXOSC32K
90%

10%

TLPXOSC32KSU valid internal clock

Table 40. Slow external crystal oscillator (32 kHz) electrical characteristics
Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

S Slow external crystal oscillator 32.76

fSXOSC — — 32 40 kHz
R frequency 8
C
VSXOSC T Oscillation amplitude — — 2.1 — V
C
C
ISXOSCBIAS T Oscillation bias current — 2.5 µA
C
C Slow external crystal oscillator
ISXOSC T — — — 8 µA
C consumption
C Slow external crystal oscillator
tSXOSCSU T — — — 2(2) s
C start-up time
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified. Values are specified for no neighbor
GPIO pin activity. If oscillator is enabled (OSC32K_XTAL and OSC32K_EXTAL pins), neighboring pins should not toggle.
2. Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal.

4.14 FMPLL electrical characteristics

The device provides a frequency modulated phase locked loop (FMPLL) module to
generate a fast system clock from the main oscillator driver.

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Table 41. FMPLL electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

fPLLIN SR — FMPLL reference clock(2) — 4 — 64 MHz

FMPLL reference clock duty
PLLIN SR — — 40 — 60 %
cycle(2)
fPLLOUT CC P FMPLL output clock frequency — 16 — 64 MHz
VCO frequency without
P — 256 — 512
frequency modulation
fVCO(3) CC MHz
VCO frequency with frequency
P — 245.76 — 532.48
modulation
fCPU SR — System clock frequency — — — 64 MHz
fFREE CC P Free-running frequency — 20 — 150 MHz
tLOCK CC P FMPLL lock time Stable oscillator (fPLLIN = 16 MHz) 40 100 µs
tSTJIT CC — FMPLL short term jitter(4) fsys maximum –4 — 4 %
tLTJIT CC — FMPLL long term jitter fPLLCLK at 64 MHz, 4000 cycles — — 10 ns
IPLL CC C FMPLL consumption TA = 25 °C — — 4 mA
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2. PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in functional
mode. When bypass mode is used, oscillator input clock should verify fPLLIN and PLLIN.
3. Frequency modulation is considered ± 4%.
4. Short term jitter is measured on the clock rising edge at cycle n and n+4.

4.15 Fast internal RC oscillator (16 MHz) electrical characteristics

The device provides a 16 MHz main internal RC oscillator. This is used as the default clock
at the power-up of the device.

Table 42. Fast internal RC oscillator (16 MHz) electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

CC P Fast internal RC oscillator high TA = 25 °C, trimmed — 16 —

fFIRC MHz
SR — frequency — 12 20
Fast internal RC oscillator high
IFIRCRUN(2) CC T frequency current in running TA = 25 °C, trimmed — — 200 µA
mode
Fast internal RC oscillator high
IFIRCPWD CC D frequency current in power TA = 25 °C — — 10 µA
down mode

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Table 42. Fast internal RC oscillator (16 MHz) electrical characteristics (continued)
Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

sysclk = off — 500 —

sysclk = 2 MHz — 600 —
Fast internal RC oscillator high
IFIRCSTOP CC T frequency and system clock TA = 25 °C sysclk = 4 MHz — 700 — µA
current in stop mode
sysclk = 8 MHz — 900 —
sysclk = 16 MHz — 1250 —
Fast internal RC oscillator start-
tFIRCSU CC C VDD = 5.0 V ± 10% — 1.1 2.0 µs
up time
Fast internal RC oscillator
FIRCPRE CC C precision after software TA = 25 °C 1 — 1 %
trimming of fFIRC
Fast internal RC oscillator
FIRCTRIM CC C TA = 25 °C — 1.6 %
trimming step
Fast internal RC oscillator
variation over temperature and
FIRCVAR CC C supply with respect to fFIRC at — 5 — 5 %
TA = 25 °C in high-frequency
configuration
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.

4.16 Slow internal RC oscillator (128 kHz) electrical

characteristics
The device provides a 128 kHz low power internal RC oscillator. This can be used as the
reference clock for the RTC module.

Table 43. Slow internal RC oscillator (128 kHz) electrical characteristics

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

CC P Slow internal RC oscillator low TA = 25 °C, trimmed — 128 —

fSIRC kHz
SR — frequency — 100 — 150
Slow internal RC oscillator low
ISIRC(2) CC C TA = 25 °C, trimmed — — 5 µA
frequency current
Slow internal RC oscillator start-up
tSIRCSU CC P TA = 25 °C, VDD = 5.0 V ± 10% — 8 12 µs
time

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Table 43. Slow internal RC oscillator (128 kHz) electrical characteristics (continued)
Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Slow internal RC oscillator precision

SIRCPRE CC C TA = 25 °C 2 — 2
after software trimming of fSIRC
%
Slow internal RC oscillator trimming
SIRCTRIM CC C — — 2.7 —
step
Slow internal RC oscillator variation
in temperature and supply with
SIRCVAR CC C High frequency configuration 10 — 10 %
respect to fSIRC at TA = 55 °C in high
frequency configuration
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is ON.

4.17 ADC electrical characteristics

4.17.1 Introduction
The device provides two Successive Approximation Register (SAR) analog-to-digital
converters (10-bit and 12-bit).

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Figure 16. ADC_0 characteristic and error definitions

Offset Error (EO) Gain Error (EG)

1023

1022

1021

1020

1019

1 LSB ideal = VDD_ADC / 1024

1018

(2)

code out
7
(1)
6

5
(5) (1) Example of an actual transfer curve
(2) The ideal transfer curve
4
(3) Differential non-linearity error (DNL)
(4)
(4) Integral non-linearity error (INL)
3
(5) Center of a step of the actual transfer curve

2 (3)

1
1 LSB (ideal)

0
1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023
Vin(A) (LSBideal)

Offset Error (EO)

4.17.2 Input impedance and ADC accuracy

In the following analysis, the input circuit corresponding to the precise channels is
considered.
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have
low AC impedance. Placing a capacitor with good high frequency characteristics at the input
pin of the device can be effective: the capacitor should be as large as possible, ideally
infinite. This capacitor contributes to attenuating the noise present on the input pin;
furthermore, it sources charge during the sampling phase, when the analog signal source is
a high-impedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC filter). The RC filtering may be limited according to the value of source

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impedance of the transducer or circuit supplying the analog signal to be measured. The filter
at the input pins must be designed taking into account the dynamic characteristics of the
input signal (bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the
sampling capacitance: being CS and Cp2 substantially two switched capacitances, with a
frequency equal to the conversion rate of the ADC, it can be seen as a resistive path to
ground. For instance, assuming a conversion rate of 1 MHz, with CS+Cp2 equal to 3 pF, a
resistance of 330 k is obtained (REQ = 1 / (fc × (CS+Cp2)), where fc represents the
conversion rate at the considered channel). To minimize the error induced by the voltage
partitioning between this resistance (sampled voltage on CS+Cp2) and the sum of RS + RF,
the external circuit must be designed to respect the Equation 4:

Equation 4
RS + RF
1
V A  ---------------------  --- LSB
R EQ 2

Equation 4 generates a constraint for external network design, in particular on a resistive

path.

Figure 17. Input equivalent circuit (precise channels)

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

VDD
Channel
Sampling
Selection
Source Filter Current Limiter

RS RF RL RSW1 RAD

VA CF CP1 CP2 CS

RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL Current Limiter Resistance
RSW1 Channel Selection Switch Impedance
RADSampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance

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Figure 18. Input equivalent circuit (extended channels)

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

VDD
Channel Extended
Sampling
Selection Switch
Source Filter Current Limiter

RS RF RL RSW1 RSW2 RAD

VA CF CP1 CP3 CP2 CS

RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
RL Current Limiter Resistance
RSW Channel Selection Switch Impedance (two contributions RSW1 and RSW2)
RADSampling Switch Impedance
CP Pin Capacitance (three contributions, CP1, CP2 and CP3)
CS Sampling Capacitance

A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the
equivalent circuit reported in Figure 17): A charge sharing phenomenon is installed when
the sampling phase is started (A/D switch close).

Figure 19. Transient behavior during sampling phase

VCS Voltage Transient on CS

VA
VA2 V <0.5 LSB

1 2
1 < (RSW + RAD) CS << tS

VA1 2 = RL (CS + CP1 + CP2)

TS t

In particular two different transient periods can be distinguished:

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1. A first and quick charge transfer from the internal capacitance CP1 and CP2 to the
sampling capacitance CS occurs (CS is supposed initially completely discharged):
considering a worst case (since the time constant in reality would be faster) in which
CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and
CS are in series, and the time constant is

Equation 5

CP  CS
 1 =  R SW + R AD   ---------------------
CP + CS

Equation 5 can again be simplified considering only CS as an additional worst

condition. In reality, the transient is faster, but the A/D converter circuitry has been
designed to be robust also in the very worst case: the sampling time tS is always much
longer than the internal time constant:

Equation 6
 1   R SW + R AD   C S « t s

The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the
voltage VA1 on the capacitance according to Equation 7:

Equation 7
V A1   C S + C P1 + C P2  = V A   C P1 + C P2 

2. A second charge transfer involves also CF (that is typically bigger than the on-chip
capacitance) through the resistance RL: again considering the worst case in which CP2
and CS were in parallel to CP1 (since the time constant in reality would be faster), the
time constant is:

Equation 8
 2  R L   C S + C P1 + C P2 

In this case, the time constant depends on the external circuit: in particular imposing
that the transient is completed well before the end of sampling time ts, a constraints on
RL sizing is obtained:

Equation 9 ADC_0 (10-bit)

8.5  
2 = 8.5  R L   C S + C P1 + C P2   t s

Equation 10 ADC_1 (12-bit)

10   2 = 10  R L   C S + C P1 + C P2   t s

Of course, RL shall be sized also according to the current limitation constraints, in

combination with RS (source impedance) and RF (filter resistance). Being CF
definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the
charge transfer transient) will be much higher than VA1. Equation 11 must be respected
(charge balance assuming now CS already charged at VA1):

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Equation 11
VA2   C S + C P1 + C P2 + C F  = V A  C F + V A1   C P1 + C P2 + C S 

The two transients above are not influenced by the voltage source that, due to the presence
of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on
CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with
respect to the sampling time (ts). The filter is typically designed to act as antialiasing.

Figure 20. Spectral representation of input signal

Analog source bandwidth (VA)

tc < 2 RFCF (Conversion rate vs. filter pole)

Noise fF = f0 (Anti-aliasing filtering condition)

2 f0 < fC (Nyquist)

f0 f
Anti-aliasing filter (fF = RC filter pole) Sampled signal spectrum (fC = Conversion rate)

fF f f0 fC f

Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of
the antialiasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at
least 2f0; it means that the constant time of the filter is greater than or at least equal to twice
the conversion period (tc). Again the conversion period tc is longer than the sampling time ts,
which is just a portion of it, even when fixed channel continuous conversion mode is
selected (fastest conversion rate at a specific channel): in conclusion it is evident that the
time constant of the filter RFCF is definitively much higher than the sampling time ts, so the
charge level on CS cannot be modified by the analog signal source during the time in which
the sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce
the accuracy error due to the voltage drop on CS; from the two charge balance equations
above, it is simple to derive Equation 12 between the ideal and real sampled voltage on CS:

Equation 12
V A2 C P1 + C P2 + C F
------------ = --------------------------------------------------------
VA C P1 + C P2 + C F + C S

From this formula, in the worst case (when VA is maximum, that is for instance 5 V),
assuming to accept a maximum error of half a count, a constraint is evident on CF value:

Equation 13 ADC_0 (10-bit)

C F  2048  C S

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Equation 14 ADC_1 (12-bit)

C F  8192  C S

4.17.3 ADC electrical characteristics

Table 44. ADC input leakage current

Value
Symbol C Parameter Conditions Unit
Min Typ Max

D TA = 40 °C — 1 70
D TA = 25 °C — 1 70
ILKG CC D Input leakage current TA = 85 °C No current injection on adjacent pin 3 100 nA
D TA = 105 °C — 8 200
P TA = 125 °C — 45 400

Table 45. ADC_0 conversion characteristics (10-bit ADC_0)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Voltage on VSS_HV_ADC0
VSS_ADC0 SR — (ADC_0 reference) pin with — 0.1 — 0.1 V
respect to ground (VSS)(2)
Voltage on VDD_HV_ADC pin
VDD_ADC0 SR — (ADC reference) with respect to — VDD 0.1 — VDD + 0.1 V
ground (VSS)
VSS_ADC0 VDD_ADC0
VAINx SR — Analog input voltage(3) — — V
0.1 + 0.1
ADC_0 consumption in power
IADC0pwd SR — — — — 50 µA
down mode
ADC_0 consumption in running
IADC0run SR — — — — 5 mA
mode
fADC0 SR — ADC_0 analog frequency — 6 — 32 + 4% MHz
ADC_0 digital clock duty cycle
ADC0_SYS SR — ADCLKSEL = 1(4) 45 — 55 %
(ipg_clk)
tADC0_PU SR — ADC_0 power up delay — — — 1.5 µs
fADC = 32 MHz,
0.5 —
INPSAMP = 17
tADC0_S CC T Sampling time(5) µs
fADC = 6 MHz,
— — 42
INPSAMP = 255
fADC = 32 MHz,
tADC0_C CC P Conversion time(6) 0.625 — — µs
INPCMP = 2
ADC_0 input sampling
CS CC D — — — 3 pF
capacitance

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Table 45. ADC_0 conversion characteristics (10-bit ADC_0) (continued)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

CP1 CC D ADC_0 input pin capacitance 1 — — — 3 pF

CP2 CC D ADC_0 input pin capacitance 2 — — — 1 pF
CP3 CC D ADC_0 input pin capacitance 3 — — — 1 pF
Internal resistance of analog
RSW1 CC D — — — 3 k
source
Internal resistance of analog
RSW2 CC D — — — 2 k
source
Internal resistance of analog
RAD CC D — — — 2 k
source
Current VDD = 
5 — 5
injection on 3.3 V ± 10%
one ADC_0
IINJ SR — Input current Injection mA
input, different VDD = 
from the 5 — 5
5.0 V ± 10%
converted one
| INL | CC T Absolute integral nonlinearity No overload — 0.5 1.5 LSB
Absolute differential
| DNL | CC T No overload — 0.5 1.0 LSB
nonlinearity
| EO | CC T Absolute offset error — — 0.5 — LSB
| EG | CC T Absolute gain error — — 0.6 — LSB
P Total unadjusted error(7)
for Without current injection 2 0.6 2
TUEP CC precise channels, input only LSB
T pins With current injection 3 — 3

T Total unadjusted error(7) for Without current injection 3 1 3

TUEX CC LSB
T extended channel With current injection 4 4
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified.
2. Analog and digital VSS must be common (to be tied together externally).
3. VAINx may exceed VSS_ADC0 and VDD_ADC0 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0x3FF.
4. Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal
divider by 2.
5. During the sampling time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC0_S. After the end of
the sampling time tADC0_S, changes of the analog input voltage have no effect on the conversion result. Values for the
sampling clock tADC0_S depend on programming.
6. This parameter does not include the sampling time tADC0_S, but only the time for determining the digital result and the time
to load the result’s register with the conversion result.
7. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.

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Figure 21. ADC_1 characteristic and error definitions

Offset Error (EO) Gain Error (EG)

4095

4094

4093

4092

4091

1 LSB ideal = VDD_ADC / 4096

4090

(2)

code out
7
(1)
6

5
(5) (1) Example of an actual transfer curve
(2) The ideal transfer curve
4
(3) Differential non-linearity error (DNL)
(4)
(4) Integral non-linearity error (INL)
3
(5) Center of a step of the actual transfer curve

2 (3)

1
1 LSB (ideal)

0
1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal)

Offset Error (EO)

Table 46. ADC_1 conversion characteristics (12-bit ADC_1)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Voltage on VSS_HV_ADC1
VSS_ADC1 SR — (ADC_1 reference) pin with — –0.1 — 0.1 V
respect to ground (VSS)(2)
Voltage on VDD_HV_ADC1
VDD_ADC1 SR — pin (ADC_1 reference) with — VDD – 0.1 — VDD + 0.1 V
respect to ground (VSS)
VSS_ADC1 VDD_ADC1
VAINx SR — Analog input voltage(3) — — V
– 0.1 + 0.1

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Table 46. ADC_1 conversion characteristics (12-bit ADC_1) (continued)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

ADC_1 consumption in power

IADC1pwd SR — — — — 50 µA
down mode
ADC_1 consumption in
IADC1run SR — — — — 6 mA
running mode
VDD = 3.3 V 3.33 — 20 + 4%
fADC1 SR — ADC_1 analog frequency MHz
VDD = 5 V 3.33 — 32 + 4%
tADC1_PU SR — ADC_1 power up delay — — — 1.5 µs
Sampling time(4) fADC1 = 20 MHz,
600 — —
VDD = 3.3 V INPSAMP = 12
ns
Sampling time(4) fADC1 = 32 MHz,
500 — —
VDD = 5.0 V INPSAMP = 17
tADC1_S CC T
Sampling time(4) fADC1 = 3.33 MHz,
— — 76.2
VDD = 3.3 V INPSAMP = 255
µs
Sampling time(4) fADC1 = 3.33 MHz,
— — 76.2
VDD = 5.0 V INPSAMP = 255
Conversion time(5) fADC1 = 20 MHz,
2.4 — — µs
VDD = 3.3 V INPCMP = 0

Conversion time(5) fADC 1 = 32 MHz,

1.5 — — µs
VDD = 5.0 V INPCMP = 0
tADC1_C CC P
Conversion time(5) fADC 1 = 13.33 MHz,
— — 3.6 µs
VDD = 3.3 V INPCMP = 0

Conversion time(5) fADC1 = 13.33 MHz,

— — 3.6 µs
VDD = 5.0 V INPCMP = 0

ADC1_SYS SR — ADC_1 digital clock duty cycle ADCLKSEL = 1(6) 45 — 55 %

ADC_1 input sampling
CS CC D — — — 5 pF
capacitance
ADC_1 input pin capacitance
CP1 CC D — — — 3 pF
1
ADC_1 input pin capacitance
CP2 CC D — — — 1 pF
2
ADC_1 input pin capacitance
CP3 CC D — — — 1.5 pF
3
Internal resistance of analog
RSW1 CC D — — — 1 k
source
Internal resistance of analog
RSW2 CC D — — — 2 k
source
Internal resistance of analog
RAD CC D — — — 0.3 k
source

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Table 46. ADC_1 conversion characteristics (12-bit ADC_1) (continued)

Value
Symbol C Parameter Conditions(1) Unit
Min Typ Max

Current VDD = 3.3 V ±

–5 — 5
injection on 10%
one ADC_1
input,
IINJ SR — Input current Injection mA
different VDD = 5.0 V ±
from the –5 — 5
10%
converted
one
Absolute integral nonlinearity
| INLP | CC T No overload — 1 3 LSB
– Precise channels
Absolute integral nonlinearity
| INLX | CC T No overload — 1.5 5 LSB
– Extended channels
Absolute differential
| DNL | CC T No overload — 0.5 1 LSB
nonlinearity
| EO | CC T Absolute offset error — — 2 — LSB
| EG | CC T Absolute gain error — — 2 — LSB
P Total unadjusted error for Without current injection –6 — 6
TUEP(7) CC precise channels, input only LSB
T pins With current injection –8 — 8

T Total unadjusted error for Without current injection –10 — 10

TUEX(7) CC LSB
T extended channel With current injection –12 — 12
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = –40 to 125 °C, unless otherwise specified
2. Analog and digital VSS must be common (to be tied together externally).
3. VAINx may exceed VSS_ADC1 and VDD_ADC1 limits, remaining on absolute maximum ratings, but the results of the
conversion will be clamped respectively to 0x000 or 0xFFF.
4. During the sampling time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the end of
the sampling time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values for the
sampling clock tADC1_S depend on programming.
5. This parameter does not include the sampling time tADC1_S, but only the time for determining the digital result and the time
to load the result’s register with the conversion result.
6. Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured by internal
divider by 2.
7. Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.

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4.18 On-chip peripherals

4.18.1 Current consumption

Table 47. On-chip peripherals current consumption(1)

Typical
Symbol C Parameter Conditions Unit
value(2)

Bitrate: Total (static + dynamic)

8 * fperiph + 85
500 Kbyte/s consumption:
– FlexCAN in loop-back
CAN (FlexCAN)
mode
IDD_BV(CAN) CC T supply current on µA
VDD_BV Bitrate: – XTAL at 8 MHz used as
CAN engine clock source 8 * fperiph + 27
125 Kbyte/s
– Message sending period is
580 µs
Static consumption:
– eMIOS channel OFF 29 * fperiph
eMIOS supply current – Global prescaler enabled
IDD_BV(eMIOS) CC T µA
on VDD_BV Dynamic consumption:
– It does not change varying the frequency 3
(0.003 mA)
Total (static + dynamic) consumption:
SCI (LINFlex) supply
IDD_BV(SCI) CC T – LIN mode 5 * fperiph + 31 µA
current on VDD_BV
– Baudrate: 20 Kbyte/s
Ballast static consumption (only clocked) 1
Ballast dynamic consumption (continuous
SPI (DSPI) supply communication):
IDD_BV(SPI) CC T µA
current on VDD_BV – Baudrate: 2 Mbit/s 16 * fperiph
– Transmission every 8 µs
– Frame: 16 bits
Ballast static consumption (no
41 * fperiph
IDD_BV ADC_0/ADC_1 supply conversion)(3)
CC T VDD = 5.5 V µA
(ADC_0/ADC_1) current on VDD_BV Ballast dynamic consumption
46 * fperiph
(continuous conversion)(3)
Analog static consumption
200 µA
ADC_0 supply current (no conversion)
IDD_HV_ADC0 CC T VDD = 5.5 V
on VDD_HV_ADC0 Analog dynamic consumption
3 mA
(continuous conversion)
Analog static consumption
300 * fperiph µA
ADC_1 supply current (no conversion)
IDD_HV_ADC1 CC T VDD = 5.5 V
on VDD_HV_ADC1 Analog dynamic consumption
4 mA
(continuous conversion)

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Electrical characteristics SPC560B54x/6x

Table 47. On-chip peripherals current consumption(1) (continued)

Typical
Symbol C Parameter Conditions Unit
value(2)

CFlash + DFlash
IDD_HV(FLASH) CC T supply current on VDD = 5.5 V — 12 mA
VDD_HV
PLL supply current on
IDD_HV(PLL) CC T VDD = 5.5 V — 30 * fperiph µA
VDD_HV
1. Operating conditions: TA = 25 °C, fperiph = 8 MHz to 64 MHz.
2. fperiph is an absolute value.
3. During the conversion, the total current consumption is given from the sum of the static and dynamic consumption, i.e., (41
+ 46) * fperiph.

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 4.18.2 DSPI characteristics

SPC560B54x/6x
Table 48. DSPI characteristics(1)
DSPI0/DSPI1/DSPI3/DSPI5 DSPI2/DSPI4
No. Symbol C Parameter Unit
Min Typ Max Min Typ Max

Master mode
D 125 — — 333 — —
(MTFE = 0)
Slave mode
D 125 — — 333 — —
(MTFE = 0)
1 tSCK SR SCK cycle time ns
Master mode
D 83 — — 125 — —
(MTFE = 1)
Slave mode
D 83 — — 125 — —
(MTFE = 1)
DocID15131 Rev 9

— fDSPI SR D DSPI digital controller frequency — — fCPU — — fCPU MHz

Internal delay between pad
associated to SCK and pad
— tCSC CC D Master mode — — 130(2) — — 15(3) ns
associated to CSn in master
mode for CSn1->0
Internal delay between pad
associated to SCK and pad
— tASC CC D Master mode — — 130(3) — — 130(3) ns
associated to CSn in master
mode for CSn1->1
2 tCSCext(4) SR D CS to SCK delay Slave mode 32 — — 32 — — ns
(5)
3 tASCext SR D After SCK delay Slave mode 1/fDSPI + 5 — — 1/fDSPI + 5 — — ns

Electrical characteristics
CC D Master mode — tSCK/2 — — tSCK/2 —
4 tSDC SCK duty cycle ns
SR D Slave mode tSCK/2 — — tSCK/2 — —
5 tA SR D Slave access time Slave mode — — 1/fDSPI + 70 — — 1/fDSPI + 130 ns
6 tDI SR D Slave SOUT disable time Slave mode 7 — — 7 — — ns
7 tPCSC SR D PCSx to PCSS time — 0 — — 0 — — ns
109/133

8 tPASC SR D PCSS to PCSx time — 0 — — 0 — — ns

 Table 48. DSPI characteristics(1) (continued)
110/133

Electrical characteristics
DSPI0/DSPI1/DSPI3/DSPI5 DSPI2/DSPI4
No. Symbol C Parameter Unit
Min Typ Max Min Typ Max

Master mode 43 — — 145 — —

9 tSUI SR D Data setup time for inputs ns
Slave mode 5 — — 5 — —
Master mode 0 — — 0 — —
10 tHI SR D Data hold time for inputs ns
(6) 2(6)
Slave mode 2 — — — —
Master mode — — 32 — — 50
11 tSUO(7) CC D Data valid after SCK edge ns
Slave mode — — 52 — — 160
Master mode 0 — — 0 — —
12 tHO(7) CC D Data hold time for outputs ns
Slave mode 8 — — 13 — —
DocID15131 Rev 9

1. Operating conditions: CL = 10 to 50 pF, SlewIN = 3.5 to 15 ns.

2. Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK starts before CSn is
asserted. DSPI2 has only SLOW SCK available.
3. Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is deasserted before
SCK. DSPI0 and DSPI1 have only MEDIUM SCK available.
4. The tCSC delay value is configurable through a register. When configuring tCSC (using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay between internal CS
and internal SCK must be higher than tCSC to ensure positive tCSCext.
5. The tASC delay value is configurable through a register. When configuring tASC (using PASC and ASC fields in DSPI_CTARx registers), delay between internal CS and
internal SCK must be higher than tASC to ensure positive tASCext.
6. This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.
7. SCK and SOUT are configured as MEDIUM pad.

SPC560B54x/6x
SPC560B54x/6x Electrical characteristics

Figure 22. DSPI classic SPI timing — master, CPHA = 0

2 3

PCSx

4 1

SCK Output
(CPOL = 0)
4

SCK Output
(CPOL = 1)
10
9

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Note: Numbers shown reference Table 47.

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Electrical characteristics SPC560B54x/6x

Figure 23. DSPI classic SPI timing — master, CPHA = 1

PCSx

SCK Output
(CPOL = 0)
10

SCK Output
(CPOL = 1)

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Note: Numbers shown reference Table 47.

Figure 24. DSPI classic SPI timing — slave, CPHA = 0

3
2
SS

1
SCK Input 4
(CPOL = 0)

4
SCK Input
(CPOL = 1)

5
12 11 6

SOUT First Data Data Last Data

9
10

SIN First Data Data Last Data

Note: Numbers shown reference Table 47.

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SPC560B54x/6x Electrical characteristics

Figure 25. DSPI classic SPI timing — slave, CPHA = 1

SS

SCK Input
(CPOL = 0)

SCK Input
(CPOL = 1)
11
5 6
12

SOUT First Data Data Last Data

9
10
SIN First Data Data Last Data

Note: Numbers shown reference Table 47.

Figure 26. DSPI modified transfer format timing — master, CPHA = 0

3
PCSx

4 1
2
SCK Output
(CPOL = 0)
4
SCK Output
(CPOL = 1)

9 10

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Note: Numbers shown reference Table 47.

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Electrical characteristics SPC560B54x/6x

Figure 27. DSPI modified transfer format timing — master, CPHA = 1

PCSx

SCK Output
(CPOL = 0)

SCK Output
(CPOL = 1)
10
9

SIN First Data Data Last Data

12 11

SOUT First Data Data Last Data

Note: Numbers shown reference Table 47.

Figure 28. DSPI modified transfer format timing — slave, CPHA = 0

3
2
SS

SCK Input
(CPOL = 0)
4 4

SCK Input
(CPOL = 1)
11 12 6
5

SOUT First Data Data Last Data

9 10

SIN First Data Data Last Data

Note: Numbers shown reference Table 47.

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SPC560B54x/6x Electrical characteristics

Figure 29. DSPI modified transfer format timing — slave, CPHA = 1

SS

SCK Input
(CPOL = 0)

SCK Input
(CPOL = 1)
11
5 6
12

SOUT First Data Data Last Data

9
10
SIN First Data Data Last Data

Note: Numbers shown reference Table 47.

Figure 30. DSPI PCS strobe (PCSS) timing

7 8

PCSS

PCSx

Note: Numbers shown reference Table 47.

4.18.3 Nexus characteristics

Table 49. Nexus characteristics

Value
No. Symbol C Parameter Unit
Min Typ Max

1 tTCYC CC D TCK cycle time 64 — — ns

2 tMCYC CC D MCKO cycle time 32 — — ns
3 tMDOV CC D MCKO low to MDO data valid — — 8 ns
4 tMSEOV CC D MCKO low to MSEO_b data valid — — 8 ns

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Table 49. Nexus characteristics (continued)

Value
No. Symbol C Parameter Unit
Min Typ Max

5 tEVTOV CC D MCKO low to EVTO data valid — — 8 ns

tNTDIS CC D TDI data setup time 15 — — ns
6
tNTMSS CC D TMS data setup time 15 — — ns
tNTDIH CC D TDI data hold time 5 — — ns
7
tNTMSH CC D TMS data hold time 5 — — ns
8 tTDOV CC D TCK low to TDO data valid 35 — — ns
9 tTDOI CC D TCK low to TDO data invalid 6 — — ns

Figure 31. Nexus TDI, TMS, TDO timing

TCK

10
11

TMS, TDI

12

TDO

Note: Numbers shown reference Table 49.

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SPC560B54x/6x Electrical characteristics

4.18.4 JTAG characteristics

Table 50. JTAG characteristics

Value
No. Symbol C Parameter Unit
Min Typ Max

1 tJCYC CC D TCK cycle time 64 — — ns

2 tTDIS CC D TDI setup time 15 — — ns
3 tTDIH CC D TDI hold time 5 — — ns
4 tTMSS CC D TMS setup time 15 — — ns
5 tTMSH CC D TMS hold time 5 — — ns
6 tTDOV CC D TCK low to TDO valid — — 33 ns
7 tTDOI CC D TCK low to TDO invalid 6 — — ns

Figure 32. Timing diagram — JTAG boundary scan

TCK

2/4 3/5

DATA INPUTS INPUT DATA VALID

DATA OUTPUTS OUTPUT DATA VALID

DATA OUTPUTS

Note: Numbers shown reference Table 50.

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5 Package characteristics

5.1 ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

5.2 Package mechanical data

5.2.1 LQFP176

Figure 33. LQFP176 package mechanical drawing

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SPC560B54x/6x Package characteristics

Table 51. LQFP176 mechanical data(1)

mm inches(2)
Symbol
Min Typ Max Min Typ Max

A 1.400 — 1.600 — 0.063

A1 0.050 — 0.150 0.002 —
A2 1.350 — 1.450 0.053 — 0.057
b 0.170 — 0.270 0.007 — 0.011
C 0.090 — 0.200 0.004 — 0.008
D 23.900 — 24.100 0.941 — 0.949
E 23.900 — 24.100 0.941 — 0.949
e — 0.500 — — 0.020 —
HD 25.900 — 26.100 1.020 — 1.028
HE 25.900 — 26.100 1.020 — 1.028
(3)
L 0.450 — 0.750 0.018 — 0.030
L1 — 1.000 — — 0.039 —
ZD — 1.250 — — 0.049 —
ZE — 1.250 — — 0.049 —
q 0° — 7° 0° — 7°
Tolerance mm inches
ccc 0.080 0.0031
1. Controlling dimension: millimeter.
2. Values in inches are converted from mm and rounded to 4 decimal digits.
3. L dimension is measured at gauge plane at 0.25 mm above the seating plane.

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Package characteristics SPC560B54x/6x

5.2.2 LQFP144

Figure 34. LQFP144 package mechanical drawing

Table 52. LQFP144 mechanical data

mm inches(1)
Symbol
Min Typ Max Min Typ Max

A — — 1.600 — — 0.0630
A1 0.050 — 0.150 0.0020 — 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 — 0.200 0.0035 — 0.0079
D 21.800 22.000 22.200 0.8583 0.8661 0.8740

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Table 52. LQFP144 mechanical data (continued)

mm inches(1)
Symbol
Min Typ Max Min Typ Max

D1 19.800 20.000 20.200 0.7795 0.7874 0.7953

D3 — 17.500 — — 0.6890 —
E 21.800 22.000 22.200 0.8583 0.8661 0.8740
E1 19.800 20.000 20.200 0.7795 0.7874 0.7953
E3 — 17.500 — — 0.6890 —
e — 0.500 — — 0.0197 —
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 — 1.000 — — 0.0394 —
k 0.0 ° 3.5 ° 7.0° 3.5 ° 0.0 ° 7.0 °
Tolerance mm inches
ccc 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Package characteristics SPC560B54x/6x

5.2.3 LQFP100

Figure 35. LQFP100 package mechanical drawing

Table 53. LQFP100 mechanical data

mm inches(1)
Symbol
Min Typ Max Min Typ Max

A — — 1.600 — — 0.0630
A1 0.050 — 0.150 0.0020 — 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 — 0.200 0.0035 — 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 — 12.000 — — 0.4724 —
E 15.800 16.000 16.200 0.6220 0.6299 0.6378

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SPC560B54x/6x Package characteristics

Table 53. LQFP100 mechanical data (continued)

mm inches(1)
Symbol
Min Typ Max Min Typ Max

E1 13.800 14.000 14.200 0.5433 0.5512 0.5591

E3 — 12.000 — — 0.4724 —
e — 0.500 — — 0.0197 —
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 — 1.000 — — 0.0394 —
k 0.0 ° 3.5 ° 7.0 ° 0.0 ° 3.5 ° 7.0 °
Tolerance mm inches
ccc 0.080 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Package characteristics SPC560B54x/6x

5.2.4 LBGA208

Figure 36. LBGA208 package mechanical drawing

Seating
plane

ddd C
A
D

A2
A4
A3

A1
A
D

B
D1
A
e F

T
R

F
P
N
M
L
K
J

E1
E
H
G
F
E
D
C
B

e
A
1 3 5 7 9 11 13 15
2 4 6 8 10 12 14 16

A1 corner index area b (208 balls)

(See note 1)
eee M C A B
fff M C

Bottom view

1. The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized
markings, or other feature of package body or integral heatslug.
A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional.

Table 54. LBGA208 mechanical data

mm inches(1)
Symbol Notes
Min Typ Max Min Typ Max
(2)
A — — 1.70 — — 0.0669
A1 0.30 — — 0.0118 — — —
A2 — 1.085 — — 0.0427 — —
A3 — 0.30 — — 0.0118 — —
A4 — — 0.80 — — 0.0315 —
(3)
b 0.50 0.60 0.70 0.0197 0.0236 0.0276

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SPC560B54x/6x Package characteristics

Table 54. LBGA208 mechanical data (continued)

mm inches(1)
Symbol Notes
Min Typ Max Min Typ Max

D 16.80 17.00 17.20 0.6614 0.6693 0.6772 —

D1 — 15.00 — — 0.5906 — —
E 16.80 17.00 17.20 0.6614 0.6693 0.6772 —
E1 — 15.00 — — 0.5906 — —
e — 1.00 — — 0.0394 — —
F — 1.00 — — 0.0394 — —
ddd — — 0.20 — — 0.0079
(4)
eee — — 0.25 — — 0.0098
(5)
fff — — 0.10 — — 0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. LBGA stands for Low profile Ball Grid Array.
– Low profile: The total profile height (Dim A) is measured from the seating plane to the top of the component
– The maximum total package height is calculated by the following methodology:
A2 (Typ) + A1 (Typ) + (A12 + A32 + A42 tolerance values)
– Low profile: 1.20 mm < A < 1.70 mm
3. The typical ball diameter before mounting is 0.60mm.
4. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to
datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
5. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e.
The axis perpendicular to datum C of each ball must lie within this tolerance zone.
Each tolerance zone fff in the array is contained entirely in the respective zone eee above.
The axis of each ball must lie simultaneously in both tolerance zones.

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Ordering information SPC560B54x/6x

6 Ordering information

Figure 37. Commercial product code structure

Example code:
SPC56 0 B 64 L3 C 6E0 Y
Product identifier Core Family Memory Package Temperature Custom vers. Packing

Y = Tray
X = Tape and Reel 90°

4E0 = 48 MHz EEPROM 5V/3V

6E0 = 64 MHz EEPROM 5V/3V

B = 40 to 105°C
C = 40 to 125°C

L3 = LQFP100
L5 = LQFP144
L7 = LQFP176
B2 = LBGA2081

64 = 1536 KB
60 = 1024 KB
54 = 768 KB

B = Body

0 = e200z0h

SPC56 = Power Architecture in

90nm

1. LBGA208 is available only as development package for Nexus2+.

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SPC560B54x/6x Abbreviations

Appendix A Abbreviations

Table 55 lists abbreviations used but not defined elsewhere in this document.

Table 55. Abbreviations

Abbreviation Meaning

CMOS Complementary metal oxide semiconductor

CPHA Clock phase
CPOL Clock polarity
CS Peripheral chip select
EVTO Event out
MCKO Message clock out
MDO Message data out
MSEO Message start/end out
MTFE Modified timing format enable
SCK Serial communications clock
SOUT Serial data out
TBD To be defined
TCK Test clock input
TDI Test data input
TDO Test data output
TMS Test mode select

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Revision history SPC560B54x/6x

Revision history

Table 56 summarizes revisions to this document.

Table 56. Revision history

Date Revision Changes

12-Jan-2009 1 Initial release

Updated Device Summary-added LBGA208 Part number
Updated Features
Replaced 27 IRQs in place of 23
ADC features
External Ballast resistor support conditions
Updated device summary-added 208 BGA details
Updated block diagram to include WKUP
Updated block diagram to include 5 ch ADC 12 -bit
Updated Block summary table
Updated LQFP 144, 176 and 100 pinouts. Applied new naming convention for ADC
signals as ADCx_P[x] and ADCx_S[x]
Section 1, “General description
Updated SPC560B54/60/64 device comparison table
Updated block diagram-aligned with 512k
Updated block summary-aligned with 512k
Section 2, “Package pinouts
Updated 100,144,176,208 packages according to cut2.0 changes
07-Dec-2009 2 Added Section 3.5.1, “External ballast resistor recommendations
Added NVUSRO [WATCHDOG_EN] field description
Updated Absolute maximum ratings
Updated LQFP thermal characteristics
Updated I/O supply segments
Updated Voltage regulator capacitance connection
Updated Low voltage monitor electrical characteristics
Updated Low voltage power domain electrical characteristics
Updated DC electrical characteristics
Updated Program/Erase specifications
Updated Conversion characteristics (10 bit ADC)
Updated FMPLL electrical characteristics
Updated Fast RC oscillator electrical characteristics-aligned with
SPC560B4x/B5x/C4x/C5x
Updated On-chip peripherals current consumption
Updated ADC characteristics and error definitions diagram
Updated ADC conversion characteristics (10 bit and 12 bit)
Added ADC characteristics and error definitions diagram for 12 bit ADC

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SPC560B54x/6x Revision history

Table 56. Revision history (continued)

Date Revision Changes

Updated Features
Updated block diagram to connect peripherals to pad I/O
Updated block summary to include ADC 12-bit
23-Feb-2010 3
Updated 144, 176 and 100 pinouts to adjust format issues
Table 26 Flash module life-retention value changed from 1-5 to 5 yrs
Minor editing changes
Editorial changes and improvements.
Cover page: removed LBGA208 package silhouette
Updated “Features“ section
Table 2: updated footnote concerning LBGA208
In the block diagram:
– Added “5ch 12-bit ADC“ block.
– Updated Legend.
– Added “Interrupt request with wakeup functionality” as an input to the WKPU block.
Figure 2: removed alternate functions
Figure 3: removed alternate functions
Figure 4: removed alternate functions
Table 3: added contents concerning the following blocks: CMU, eDMA, ECSM,
MC_ME, MC_PCU, NMI, SSCM, SWT and WKPU
Added Section 3.2, Pin muxing
Section 4: Electrical characteristics: removed “Caution” note
Section 4.2: NVUSRO register: removed “NVUSRO[WATCHDOG_EN] field
description“ section
13-Sep-2010 4 Table 12: VIN: removed min value in “relative to VDD” row
Table 13
– TVDD: contents merged into one row
– VDD_BV: changed min value in “relative to VDD” row
Section 4.5: Thermal characteristics
– Section 4.5.1: External ballast resistor recommendations: added new paragraph
about power supply
– Table 15: added RJB and RJC rows
– Removed “LBGA208 thermal characteristics” table
Table 16: rewrote parameter description of WFI and WNFI
Section 4.6.5: I/O pad current specification
– Removed IDYNSEG information
– Updated “I/O supply segments” table
Table 23: removed IDYNSEG row
Added Table 24

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Revision history SPC560B54x/6x

Table 56. Revision history (continued)

Date Revision Changes

Table 26
– Updated all values
– Removed IVREGREF and IVREDLVD12 rows
– Added the footnote “The duration of the in-rush current depends on the capacitance
placed on LV pins. BV decaps must be sized accordingly. Refer to IMREG value for
minimum amount of current to be provided in cc.” to the IDD_BV specification.
Table 27
– Updated VPORH min/max value
– Updated VLVDLVCORL min value
Updated Table 28
Table 29
– Tdwprogram: added initial max value
– Inserted Teslat row
Table 30: removed the “To be confirmed” footnote
In the “Crystal oscillator and resonator connection scheme” figure, removed RP.
4 Table 40
13-Sep-2010 – Removed gmSXOSC row
(cont.)
– ISXOSCBIAS: added min/typ/max value
Table 41:
– Added fVCO row
– Added tSTJIT row
Table 42
– IFIRCPWD: removed row for TA = 55 °C
– Updated TFIRCSU row
Table 45: Added two rows: IADC0pwd and IADC0run
Table 46
– Added two rows: IADC1pwd and IADC1run
– Updated values of fADC_1 and tADC1_PU
– Updated tADC1_C row
Updated Table 47
Updated Table 48
Added Table 55
Removed “Preliminary—Subject to Change Without Notice” marking. This data sheet
contains specifications based on characterization data.
29-Oct- 2010 5 Updated Table 55
Added Table 56
Updated Figure 37

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SPC560B54x/6x Revision history

Table 56. Revision history (continued)

Date Revision Changes

Editorial and formatting changes throughout

Replaced instances of “e200z0” with “e200z0h”
Device family comparison table:
– added 1 MB code flash LQFP100 version
– added 1.5 MB code flash LQFP144 version
– removed 768 KB code flash LQFP176 version
– changed LINFlex count for 144-pin LQFP—was ‘6’; is ‘8’
– changed LINFlex count for 176-pin LQFP—was ‘8’; is ‘10’
– replaced 105 °C with 125 °C in footnote 2
SPC560B54/6x block diagram: added GPIO and VREG to legend
SPC560B54/6x series block summary: added acronym “JTAGC”; in WKPU function
changed “up to 18 external sources” to “up to 27 external sources”
LQFP144 pin configuration: for pins 37–72, restored the pin labels that existed prior to
27 July 2010
LQFP176 pin configuration: corrected name of pin 4: was EPC[15]; is PC[15]
Added following sections:
– Pad configuration during reset phases
– Pad configuration during standby mode exit
– Voltage supply pins
– Pad types
– System pins
– Functional port pins
– Nexus 2+ pins
12-Sep- 2011 6
Section “NVUSRO register”: edited content to separate configuration into electrical
parameters and digital functionality; updated footnote describing default value of ‘1’
in field descriptions NVUSRO[PAD3V5V] and NVUSRO[OSCILLATOR_MARGIN]
Added section “NVUSRO[WATCHDOG_EN] field description”
Tables “Absolute maximum ratings” and “Recommended operating conditions (3.3 V)”:
replaced “VSS_HV_ADC0, VSS_HV_ADC1” with “VDD_HV_ADC0,
VDD_HV_ADC1” in VDD_ADC parameter description
“Recommended operating conditions (5.0 V)” table: replaced “VSS_HV_ADC0,
VSS_HV_ADC1” with “VDD_HV_ADC0, VDD_HV_ADC1” in VDD_ADC parameter
description; changed 3.6V to 3.0V in footnote 2
Section “External ballast resistor recommendations”: replaced “low voltage monitor”
with “low voltage detector (LVD)”
“I/O input DC electrical characteristics” table: updated ILKG characteristics
“MEDIUM configuration output buffer electrical characteristics” table: changed
“IOH = 100 µA” to “IOL = 100 µA” in VOL conditions
I/O weight: updated table (includes replacing instances of bit “SRE” with “SRC”)
“Reset electrical characteristics” table: updated parameter classification for |IWPU|
Updated voltage regulator electrical characteristics
Section “Low voltage detector electrical characteristics”: changed title (was “Voltage
monitor electrical characteristics”); changed “as well as four low voltage detectors” to
“as well as five low voltage detectors”; added event status flag names found in RGM
chapter of device reference manual to POR module and LVD descriptions; replaced
instances of “Low voltage monitor” with “Low voltage detector”; updated values for
VLVDLVBKPL and VLVDLVCORL
Updated section “Power consumption”

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Revision history SPC560B54x/6x

Table 56. Revision history (continued)

Date Revision Changes

Section “Program/erase characteristics”: removed table “FLASH_BIU settings vs.

frequency of operation” and associated introduction
“Program and erase specifications” table: updated symbols
PFCRn settings vs. frequency of operation: replaced “FLASH_BIU” with “PFCRn” in
table title; updated field names and frequencies
“Flash power supply DC electrical characteristics” table: deleted footnote 2
Crystal oscillator and resonator connection scheme: inserted footnote about possibly
requiring a series resistor
Fast external crystal oscillator (4 to 16 MHz) electrical characteristics: updated
parameter classification for VFXOSCOP
Slow external crystal oscillator (32 kHz) electrical characteristics: updated footnote 1
12-Sep- 2011 6 Section “ADC electrical characteristics”: updated symbols for offset error and gain error
(continued) (continued) Section “Input impedance and ADC accuracy”: changed “VA/VA2” to “VA2/VA” in
Equation 11
ADC input leakage current: updated ILKG characteristics
ADC_0 conversion characteristics table: replaced instances of
“ADCx_conf_sample_input” with “INPSAMP”; replaced instances of
“ADCx_conf_comp” with “INPCMP
ADC_1 characteristic and error definitions: replaced “AVDD” with “VDD_ADC”
ADC_1 conversion characteristics table: replaced instances of
“ADCx_conf_sample_input” with “INPSAMP”; replaced instances of
“ADCx_conf_comp” with “INPCMP”
Updated “On-chip peripherals current consumption” table
Removed order codes tables.
18-Sep-2013 7 Updated Disclaimer.
Table 13: Recommended operating conditions (3.3 V), added minimum value of TVDD
and footnote about it.
Table 14: Recommended operating conditions (5.0 V), added minimum value of TVDD
and footnote about it.
Table 21: Output pin transition times, replaced Ttr with ttr
Table 25: Reset electrical characteristics, replaced Ttr with ttr
Updated Section 4.17.2: Input impedance and ADC accuracy
Table 27: Low voltage detector electrical characteristics, changed VLVDHV3L(min) and
05-May-2014 8
VLVDHV3BL(min) from 2.7 V to 2.6 V.
Table 29: Program and erase specifications, added footnote about tESRT
Table 41: FMPLL electrical characteristics, deleted footnote relative to maximum value
of fCPU
Table 45: ADC_0 conversion characteristics (10-bit ADC_0), changed IADC0run value
from 40 mA to 5 mA.
Table 48: DSPI characteristics, in the heading row, replaced
DSPI0/DSPI1/DSPI5/DSPI6 with DSPI0/DSPI1/DSPI3/DSPI5.
In Table 1: Device summary, added SPC560B64L3 for 1.5 MB code flash devices.
In Table 2: SPC560B54/6x family comparison, added column relating to “LQFP100”
package in SPC560B64 devices.
In Table 28: Power consumption on VDD_BV and VDD_HV:
22-Jan-2016 9
– changed footnote 2 “Running consumption does not include I/Os...” to “IDDMAX is
drawn only from the VDD_BV pin. Running consumption does not include I/Os...”
– changed footnote 4 “RUN current measured with...” to “IDDRUN is drawn only from
the VDD_BV pin. RUN current measured with...”

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