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PHAL Visoth E20200158

Combinational Logic Design

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Visoth Phal
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38 views5 pages

PHAL Visoth E20200158

Combinational Logic Design

Uploaded by

Visoth Phal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Name: PHAL VISOTH

ID: e20200158
Group: I3-GEE-C1

Exam: Combinational Logic Design

Prob 1. Derive the Boolean equation for the circuit below. The switches are inputs (K1, K2,
and K3). The lamp L is the output. (K1 is close when K1 =1; K1 is opened when K1 =0 ) (L =
1 when light is ON, L = 0 when light is OFF)

Solution 1
Required Boolean equation for the circuit is 𝐿 = 𝐾1 (𝐾2 + 𝐾3 )
Truth Table:
𝐾1 𝐾2 𝐾3 L
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

K-map
Logic function is,
𝑳 = 𝑲𝟏 𝑲 𝟐 + 𝑲𝟏 𝑲𝟑
Thus 𝑳 = 𝑲𝟏 (𝑲𝟐 + 𝑲𝟑 )

For the lamp to glow, K1 must be closed and either or both of K2 and K3 to be closed.

Prob 2. What is the Boolean expression of Y?

Solution 2 𝒀 = 𝑨(𝑩𝑪 + 𝑫𝑬)

Prob 3. A majority gate produces a TRUE output if and only if more than half of its inputs
are TRUE.
• Complete a truth table for the 5-inputs majority gate.
Solution 3
We can see that there are five inputs. Thus, 25 = 32
Truth Table
A B C D E Y
0 0 0 0 0 0
0 0 0 0 1 0
0 0 0 1 0 0
0 0 0 1 1 1
0 0 1 0 0 0
0 0 1 0 1 1
0 0 1 1 0 1
0 0 1 1 1 1
0 1 0 0 0 0
0 1 0 0 1 1
0 1 0 1 0 1
0 1 0 1 1 1
0 1 1 0 0 1
0 1 1 0 1 1
0 1 1 1 0 1
0 1 1 1 1 1
1 0 0 0 0 0
1 0 0 0 1 1
1 0 0 1 0 1
1 0 0 1 1 1
1 0 1 0 0 1
1 0 1 0 1 1
1 0 1 1 0 1
1 0 1 1 1 1
1 1 0 0 0 1
1 1 0 0 1 1
1 1 0 1 0 1
1 1 0 1 1 1
1 1 1 0 0 1
1 1 1 0 1 1
1 1 1 1 0 1
1 1 1 1 1 1

0 indicate the FALSE.


1 indicate the TRUE.
Prob 4. A parity bit is extra bit included with a binary message to make the number of 1’s ether
odd or even. The message, including the parity bit, is transmitted and then checked at the
receiving end for errors. An error is detected if the checked parity does not correspond with the
one transmitted. Consider a 4-bit message, design a logic circuit that generates the even parity
bit. The inputs are m0, m1, m2 and m3. The output is the parity bit P.
• Draw a truth table for the circuit.
• Using K-map to derive the minimal expression of P.
• Draw the design of the circuit using logic gates.

Solution 4

Truth table for the circuit


𝒎𝟑 𝒎𝟐 𝒎𝟏 𝒎𝟎 𝑷
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0

Using K-map to derive the minimal expression of P


CD
AB 00 01 11 10
00 0 1 0 1
01 1 0 1 0
11 0 1 0 1
10 1 0 1 0
𝑃=𝑚
̅ 3𝑚
̅ 2𝑚
̅ 1 𝑚0 + 𝑚
̅ 3𝑚̅ 2 𝑚1 𝑚
̅ 0 +𝑚
̅ 3 𝑚2 𝑚̅ 1𝑚
̅0 + 𝑚
̅ 3 𝑚2 𝑚1 𝑚0 + 𝑚3 𝑚
̅ 2𝑚
̅ 1𝑚
̅0
+ 𝑚3 𝑚
̅ 2 𝑚1 𝑚0 + 𝑚3 𝑚2 𝑚 ̅ 1 𝑚0 + 𝑚3 𝑚2 𝑚1 𝑚̅0
𝑃=𝑚 ̅ 2 (𝑚
̅ 3𝑚 ̅ 0) + 𝑚
̅ 1 𝑚0 + 𝑚1 𝑚 ̅ 3 𝑚2 (𝑚 ̅ 0 + 𝑚1 𝑚0 ) + 𝑚3 𝑚
̅ 1𝑚 ̅ 2 (𝑚 ̅ 0 + 𝑚1 𝑚0 )
̅ 1𝑚
+ 𝑚3 𝑚2 (𝑚 ̅ 0)
̅ 1 𝑚0 + 𝑚1 𝑚

𝑃=𝑚 ̅ 2 (𝑚1 ⊕ 𝑚0 ) + 𝑚
̅ 3𝑚 ̅̅̅̅̅̅̅̅̅̅̅̅
̅ 3 𝑚2 (𝑚 1 ⊕ 𝑚0 ) + 𝑚3 𝑚
̅̅̅̅̅̅̅̅̅̅̅̅
̅ 2 (𝑚 1 ⊕ 𝑚0 ) + 𝑚3 𝑚2 (𝑚1 ⊕ 𝑚0 )

𝑃=𝑚
̅ 3 {𝑚 ̅̅̅̅̅̅̅̅̅̅̅̅
̅ 2 (𝑚1 ⊕ 𝑚0 ) + 𝑚2 (𝑚 1 ⊕ 𝑚0 )} + 𝑚3 {𝑚
̅̅̅̅̅̅̅̅̅̅̅̅
̅ 2 (𝑚 1 ⊕ 𝑚0 ) + 𝑚2 (𝑚1 ⊕ 𝑚0 )}

𝑃=𝑚 ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅ 3 (𝑚2 ⊕ 𝑚1 ⊕ 𝑚0 ) + 𝑚3 (𝑚 2 ⊕ 𝑚1 ⊕ 𝑚0 )

Thus, 𝑃 = 𝑚3 ⊕ 𝑚2 ⊕ 𝑚1 ⊕ 𝑚0

Draw the design of the circuit using logic gates

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