Central Processing Unit

Also known as a processor or microprocessor the CPU was first developed by Intel in 1974 and is
short for Central Processing Unit. The computer CPU is responsible for handling all instructions and
calculation it receives from other hardware components in the computer and software programs
running on the computer.

Major Components of CPU

CPU Parts:

The CPU contains the hardware component for processing instructions and data. It is made up of three
major parts as

Major components of CPU

1. The Register Set stores intermediate data used during the execution of the instructions.

2. The Arithmetic Logic Unit (ALU) performs the required micro operations for executing the
instructions.
 3. The Control Unit supervises the sequence of micro operation.

General Register Organization

The number of registers in a processor unit may vary from just one processor register to as many as
64 registers or more.

1. One of the CPU registers is called as an accumulator AC or 'A' register. It is the main operand
register of the ALU.

2. The data register (DR) acts as a buffer between the CPU and main memory. It is used as an
input operand register with the accumulator.

3. The instruction register (IR) holds the opcode of the current instruction.

4. The address register (AR) holds the address of the memory in which the operand resides.

5. The program counter (PC) holds the address of the next instruction to be fetched for execution.

Additional addressable registers can be provided for storing operands and address. This can be
viewed as replacing the single accumulator by a set of registers. If the registers are used for many
purpose, the resulting computer is said to have general register organization. In the case of processor
registers, a registers is selected by the multiplexers that form the buses.

Bus System
A group of wires through which binary information is transferred one at a time among registers is
called a bus. A common bus system can be constructed using multiplexers, source registers, decoders
and destination registers.
 Bus organization for seven CPU registers

1. The output of the each register is connected to two multiplexers (MUX) to form the input buses A and
B.

2. The buses A and B are applied to a common arithmetic logic unit.

3. The operation selected in the ALU determines the arithmetic or logic micro operation that is to be
performed.

4. The result of the micro operation goes through the output bus into the inputs of all registers.

5. The destination register that receives the information from the output bus is selected by a decoder.

6. The decoder activates one of the register load inputs to select a destination register.

7. Control Word
8. There are 14 binary selection inputs in the units, and their combined value specified a control
word. It consists of four fields three fields contain three bits each, and one field has five bits. The
three bits of SEL A select a source register for the A input of the ALU. The three bits of SEL B
select a source register for the B input of the ALU. The three bit of SEC D selects a destination
register using the decoder and its seven load outputs. The five bits of OPR select one of the
operations in the ALU. The 14-bit control word when applied to the selection inputs specify a
particular micro-operation.
9. 3 3 3
5

SEL A SEL B SEL D OPR

10.

Table: Encoding of Register selection fields.

Binary Code SEL A SEL B SEL D

000 Input Input None

001 R1 R1 R1

010 R2 R2 R2

011 R3 R3 R3

100 R4 R4 R4

101 R5 R5 R5

110 R6 R6 R6
 111 R7 R7 R7

Instruction Format
The important fields of an instruction format are,

Opcode field(Operation code field):

If specifies which type of operation is to be performed.

Address field:

If designated a memory address or a processor register.

Mode field:

If specifies the way that the operand or the effective address is calculated.

Opcode Field Mode Field Address Fieldd

Instruction format

 The operations specified by computer instructions are performed on operands stored either in memory
registers or in processor registers. Operand residing in memory is specified by its memory address.
Operand residing in processor register is specified by a register address.

 Register address is a binary number of 'n' bits that define one of 2n registers in the central processing
unit. For example, CPU with 8 processor registers (R0 to R7) will have a register address field of three
bits.

 The binary number 011 represents the register R3. The number off address fields in the instruction
format of a computer depends on the internal organization of its registers.

Three Address Instructions

 Three address instructions computer needs three register address fields. The register address field
may be a processor register or a memory operand. Cyber 170 computer needs three address
instructions .

ADD R1, R2, R3

The above instruction denotes the operations,

R1 <-- R2 + R3 (arithmetic addition)

Where

R2, R3 = Source registers

R1 = Destination register

For Example:

ADD R1, A, B
R1M[A] + M[B]

As shown, it is clear that in the instruction 3 addresses are specified. In the above instruction one
register address and two memory addresses are specified. Example of computer using this type of
instructions Cyber 170.

Two Address Instructions

In this format each address field specify either a processor register or a memory word i.e., they
contain two address fields.

ADD R1, R2

It denotes the operation,

R1 <-- R1 + R2

Here the destination register is the same as any one of the source registers.

Mov R1, R2

It denotes the operation,

R1 <-- R2

It transfers the content of register R2 to register R1.

ADD R1, X

It denotes the operation,

R1 <-- R1 + M[X]

Where R1 = Processor register

M[X] = Memory operand at address X.

Example:

X=(A + B)-(C + D)
MOV R1,A ; R1 <- M[A]
ADD R1,B ; R1 <- R1 + M [B]
MOV R2,C ; R2 <- M [C]
ADD R2, D ; R2<-R2 + M[D]
SUB R1,R2 ; R1 <- R1 - R2
MOV X,R1 ; M[X] <- R1

One Address Instructions

One address instructions computers needs one address field. An implied accumulator (AC) register
is used for all data manipulation. Here all the operations are carried out between the accumulator
register and a memory operand.

ADD X

It denotes the operation,

AC <-- AC+ M[X]

Where

AC = Accumulator register

M[X] = Memory operand at address X.

Example:
X=(A + B)X(C + D)
LOAD A ; AC <- M [A]
ADD B ; AC <- AC + M[B]
STORE T ; M [T] <- AC
LOAD C ; AC <- M [C]
ADD D ; AC <- AC + M[D]
MUL T ; AC <- ACxM[T]
STORE X ; M[X] <- AC

Zero Address Instructions

An instruction that contains no address fields; operand sources and destination are both implicit. It
may for example enable stack processing: a zero-address instruction implies that the absolute address
of the operand is held in a special register that is automatically incremented (or decremented) to point
to the location of the top of the stack.

Example: ADD

The above instruction consists of an operation code only. It has no addrss field. The operation has
the effect of popping the two top numbers from the stack, adding the numbers and pushing the sum
into the stack. Here all operands are performed within stack. To evaluate arithmetic expressions, they
must be first converted into reverse polish notation. The operand at address X is pushed on to the top
of the stack. Automatically the stack pointer is incremented.

Example:

X=(A + B) + (C + D)
PUSH A ; TOS <- A top of the stack
PUSH B ; T0S <- B
ADD ; TOS <- A + B
PUSH C ; TOS <- C
PUSH D ; TOS <- D
ADD ; TOS <- C + D
ADD ; TOS <- (C + D) + (A + B)
POP X ; M [X] <- TOS

CISC Characteristics
A computer with large number of instructions is called complex instruction set computer or CISC.
Complex instruction set computer is mostly used in scientific computing applications requiring lots of
floating point arithmetic.
1. A large number of instructions - typically from 100 to 250 instructions.
2. Some instructions that perform specialized tasks and are used infrequently.
3. A large variety of addressing modes - typically 5 to 20 different modes.
4. Variable-length instruction formats
5. Instructions that manipulate operands in memory.

RISC Characteristics
A computer with few instructions and simple construction is called reduced instruction set
computer or RISC. RISC architecture is simple and efficient. The major characteristics of RISC
architecture are,

1. Relatively few instructions

2. Relatively few addressing modes
3. Memory access limited to load and store instructions
4. All operations are done within the registers of the CPU
5. Fixed-length and easily-decoded instruction format.
6. Single cycle instruction execution
7. Hardwired and micro programmed control

Control Unit
Control Unit Co-ordinates the input and output devices of a computer system. It fetches the code of all
of the instructions in the microprograms.

Fetch Cycle
Fetch cycle occurs at the beginning of each instruction cycle. It causes an instruction to be fetched
from memory/

1. MAR: Memory Address Register: MAR is connected to the address lines of the system bus. It
specifies the address in memory for a read or write operation.

2. MBR: MBR is connected to the data lines of the system bus. It contains the value to be stored in
memory or the last value read from memory.

3. PC: Program Counter: PC holds the address of the next instruction to be fetched.

4. IR: Instruction register: IR holds the opcode of the current instruction.

Interrupt Cycle
 After the execute cycle is completed, a test is made to determine if an interrupt was enabled (e.g. so
that another process can access the CPU)

 If not, instruction cycle returns to the fetch cycle

 If so, the interrupt cycle might performs the following tasks: (simplified...)
 move the current value of PC into MBR
 move the PC-save-address into MAR
 move the interrupt-routine-address into PC
 move the contents of the address in MBR into indicated memory cell
 continue the instruction cycle within the interrupt routine
 after the interrupt routine finishes, the PC-save-address is used to reset the value of PC and program
execution can continue

Microprogrammed Control
Microprogrammed Control Unit is a relatively logic circuit that is capable of sequencing through
micro-instructions and generating control signal to execute each micro-instruction. The two basic tasks
performed by a microprogrammed control unit are as follows: Micro-instruction sequencing: the
microprogrammed control unit get the next mico-instruction from the control memory. Micro-
instruction execution: the microprogrammed control unit generate the control signals needed to
execute the micro-instruction.

Advantage

 Since the microprograms can be changed relatively easily, therefore, microprogrammed

 control units are very flexible in comparison to hardwired control units.

Disadvantages

 Hardware cost is more because of the control memory and its access circuitry

 This is slower than hardwired control unit because the microinstruction are to be fetched from the control
memory which is time consuming.

 But, these disadvantages are gradually getting phased out as the new memory technologies are cheap
and high-speed memories are gradually becoming common.

Hardwired Control
To execute instructions, a computer's processor must generate the control signals used to perform
the processor's actions in the proper sequence. This sequence of actions can either be executed by
another processor's software (for example in software emulation or simulation of a processor) or in
hardware. Hardware methods fall into two categories: the processor's hardware signals are generated
either by hardwired control, in which the instruction bits directly generate the signals, or by
microprogrammed control in which a dedicated microcontroller executes a microprogram to generate
the signals.

Before microprocessors, hardwired control usually was implemented using discrete components,
flip-chips, or even rotating discs or drums. This can be generally done by two methods. The classical
method of sequential circuit design. It attempts to minimize the amount of hardwire, in particular, by
using only log2p flip flops to realize a p state circuit.

An approach that uses one flip flop per state. While expensive in terms of flip flops, this method
simplifies controller unit design and debugging.

In practice, processor control units are often so complex that no one design method by itself can
yield a satisfactory circuit at an acceptable cost. The most acceptable design may consist of several
linked, but independently designed, sequential circuits.

Microprogramming made it possible to re-wire, as it were, a computer by simply downloading a new

microprogram to it. This required dedicated hardware or an external processor. For example, some of
DEC's PDP-10 processors used a PDP-11 as a front-end which uploaded a microprogram to the main
processor at boot time.

Traditionally, a sewing machines' stitch patterns and a washing machine's wash programs were
implemented as hardwired, usually mechanical, controls. In modern machines, these are instead
implemented as software which controls a computer which controls the machine hardware. This makes
it possible, for example, to download additional stitch patterns for a small fee or upgrade a machine
without having to buy a complete new machine. It also opens up for intellectual property rights issues.

The term hardwired is also used in a biological context to denote behaviour that is innately
determined by an organism's genetically determined neurophysiology. Such hardwired behaviour
would include the well-known knee-jerk reflex. Non-hardwired behaviour is dependent upon learning
during the lifetime of the individual organism. As such the term is used in a way that is directly
analogous to its use in computing.