UNIT -II

Instruction Set Architecture: General Register Organization, Instruction Formats,

Addressing modes, Data Transfer and Manipulation, Program Control, Computer Arithmetic
Introduction to Computer Arithmetic: Addition and subtraction, multiplication Algorithms,
Division Algorithms, Floating – point Arithmetic operations.

Instruction Set Architecture

Central processing unit:
INTRODUCTION
The part of the computer that performs the bulk of data-processing operations is called the
central processing unit and is referred to as the CPU. The CPU is made up of three major
parts, as shown in Fig. The register set stores intermediate data used during the execution of
the instructions. The arithmetic logic unit (ALU) performs the required micro operations for
executing the instructions. The control unit supervises the transfer of information among the
registers and instructs the ALU as to which operation to perform.
The CPU performs a variety of functions dictated by the type of instructions that are
incorporated in the computer. Computer architecture is sometimes defined as the computer
structure and behavior as seen by the programmer that uses machine language instructions.
This includes the instruction formats, addressing modes, the instruction set, and the general
organization of the CPU registers.
Components of CPU

General register organization

A bus organization for seven CPU registers is shown in Fig. The output of each register is
connected to two multiplexers (MUX) to form the two buses A and B . The selection lines
in each multiplexer select one register or the input data for the particular bus.
The A and B buses form the inputs to a common arithmetic logic unit (ALU). The
operation selected in the ALU determines the arithmetic or logic micro operation that is to
be performed.
The result of the micro operation is available for output data and also
goes into the inputs of all the registers. The register that receives the information from the
output bus is selected by a decoder. The decoder activates one of the register load inputs,
thus providing a transfer path between the data in the output bus and the inputs of the
selected destination register.
The control unit that operates the CPU bus system directs the information flow through the
registers and ALU by selecting the various components in the system. For example, to
perform
the operation R 1 <--R2 + R3

the control must provide binary selection variables to the following selector inputs:
1. MUX A selector (SELA): to place the content of R2 into bus A .
2. MUX B selector (SELB): to place the content o f R 3 into bus B .
3 . ALU operation selector (OPR): to provide the arithmetic addition A + B .
4. Decoder destination selector (SELD): to transfer the content of the output bus into R1 .
The four control selection variables are generated in the control unit and must be available
at the beginning of a clock cycle. The data from the two source registers propagate through
the gates in the multiplexers and the ALU, to the output bus, and into the inputs of the
destination register, all during the clock cycle interval. Then, when the next clock transition
occurs, the binary information from the output bus is transferred into R 1.
To achieve a fast response time, the ALU is constructed with high speed circuits.

Control Word
There are 14 binary selection inputs in the unit, and their combined value specifies a control
word. Encoding of register selection fields

ALU
The ALU provides arithmetic and logic operations. In addition, the CPU must provide shift
operations. The shifter may be placed in the input of the ALU to provide a pre shift
capability, or at the output of the ALU to provide post shifting capability. In some cases, the
shift operations are included with the ALU.

Examples of Micro operations

R 1 <- R 2 - R3
specifies R2 for the A input of the ALU, R3 for the B input of the ALU, R1 for the
destination register, and an ALU operation to subtract A - B.
Instruction Formats
The most common fields found in instruction formats are:
1. An operation code field that specifies the operation to be performed.
2. An address field that designates a memory address or a processor register.
3. A mode field that specifies the way the operand or the effective address is determined.
Most computers fall into one of three types of CPU organizations:
1. Single accumulator organization.
2. General register organization.
3. Stack organization
To illustrate the influence of the number of addresses on computer programs, we will
evaluate the arithmetic statement
X = (A + B) • (C + D)
using zero, one, two, or three address instructions.
Three-Address Instructions
Computers with three-address instruction formats can use each address field to specify either
a processor register or a memory operand. The program in assembly language that evaluates
X = (A + B) • (C + D) is shown below, together with comments that explain the register
transfer operation of each instruction.

It is assumed that the computer has two processor registers, R 1 and R2. The symbol M [A ]
denotes the operand at memory address symbolized by A . The advantage o f the three-
address format i s that i t results in short programs when evaluating arithmetic expressions.
The disadvantage is that the binary-coded instructions require too many bits to specify three
addresses.
An example of a commercial computer that uses three-address instructions is the Cyber 170.
The instruction formats in the Cyber computer are restricted to either three register address
fields or two register address fields and one memory address field.
 Addressing Modes
3. Addressing Modes
The operation field of an instruction specifies the operation to be performed. This
operation must be executed on some data stored in computer registers or memory words.
The way the operands are chosen during program execution in dependent on the
addressing mode of the instruction. The addressing mode specifies a rule for interpreting or
modifying the address field of the instruction before the operand is actually referenced.
Computers use addressing mode techniques for the purpose of accommodating one or both
of the following provisions:
1 To give programming versatility to the user by providing such facilities as pointers to
Memory, counters for loop control, indexing of data, and program relocation
2 To reduce the number of bits in the addressing field of the instruction.
3 The availability of the addressing modes gives the experienced assembly language
programmer flexibility for writing programs that are more efficient with respect to the
number of instructions and execution time.
To understand the various addressing modes to be presented in this section, it is
imperative that we understand the basic operation cycle of the computer. The control unit of
a computer is designed to go through an instruction cycle that is divided into three major
phases:
1. Fetch the instruction from memory
2. Decode the instruction.
3. Execute the
instruction. Addressing modes
are as:
1. Implied Mode
Address of the operands are specified implicitly in the definition of the instruction
- No need to specify address in the instruction
- EA = AC, or EA = Stack[SP], EA: Effective Address.
2. Immediate Mode
Instead of specifying the address of the operand, operand itself is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand

EA=Not defined.
3. Register Mode
Address specified in the instruction is the register address.
- Designated operand need to be in a register
- Shorter address than the memory address
- Saving address field in the instruction
- Faster to acquire an operand than the memory
addressing EA = IR(R) (IR(R): Register field of IR)
4. Register Indirect Mode
Instruction specifies a register which contains the memory address of the operand
- Saving instruction bits since register
address is shorter than the memory
address
- Slower to acquire an operand than both
the register addressing or memory
addressing
- EA = [IR(R)] ([x]: Content of x)

5.Auto-increment or Auto-decrement features:

Same as the Register Indirect, but, when the address in the register is used to
access memory, the value in the register is incremented or decremented by 1 (after or
before the execution of the instruction).
6. Direct Address Mode
Instruction specifies the memory address
which can be used directly to the physical
memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the
address for a large physical memory
space
- EA = IR(address), (IR(address): address field of IR)
7.Indirect Addressing Mode
The address field of an instruction specifies the address of a memory location that
contains the address of the operand
- When the abbreviated address is used, large physical memory can be addressed with
a relatively small number of bits
- Slow to acquire an operand because of an additional memory access
- EA = M[IR(address)]

7. Displacement Addressing Mode

The Address fields of an instruction specifies the part of the address (abbreviated
address) which can be used along with a designated register to calculate the address of
the operand
a) PC Relative Addressing Mode(R = PC)
- EA = PC + IR(address)
- Address field of the instruction is short
- Large physical memory can be accessed with a small number of address bits
b) Indexed Addressing Mode
- XR : Index Register:
- EA = XR + IR(address)
c) Base Register Addressing Mode
BAR: Base Address Register:
- EA = BAR + IR(address)
Numerical Example:
 Data Transfer & Manipulation
Computer provides an extensive set of instructions to give the user the flexibility to
carryout various computational tasks. Most computer instruction can be classified into
three categories.
(1) Data transfer instruction
(2) Data manipulation instruction
(3) Program control instruction
Data transfer instruction cause transferred data from one location to another without
changing the binary instruction content. Data manipulation instructions are those that perform
arithmetic logic, and shift operations. Program control instructions provide decision-making
capabilities and change the path taken by the program when executed in the computer.
(1) Data Transfer Instruction
Data transfer instruction move data from one place in the computer to another without
changing the data content. The most common transfers are between memory and
processes registers, between processes register & input or output, and between processes
register themselves
(Typical data transfer instruction)
Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
(2) Data Manipulation Instruction
It performs operations on data and provides the computational capabilities for the
computer. The data manipulation instructions in a typical computer are usually divided
into three basic types.
(a) Arithmetic Instruction
(b) Logical bit manipulation Instruction
(c) Shift Instruction.

(a) Arithmetic Instruction

Name Mnemonic
Increment INC
Decrement DEC
Add Add
Subtract Sub
Multiply MUL
Divide DIV
Add with Carry ADDC
Subtract with Basses SUBB
Negate (2’s Complement) NEG
(b) Logical & Bit Manipulation Instruction

Name Mnemonic
Clear CLR
Complement COM
AND AND
OR OR
Exclusive-Or XOR
Clear Carry CLRC
Set Carry SETC
Complement Carry COMC
Enable Interrupt ET
Disable Interrupt OI
(c) Shift Instruction

Instructions to shift the content of an operand are quite useful and one often provided in
several variations. Shifts are operation in which the bits of a word are moved to the left or
right. The bit-shifted in at the and of the word determines the type of shift used. Shift
instruction may specify either logical shift, arithmetic shifts, or rotate type shifts.

Name Mnemonic
Logical Shift right SHR
Logical Shift left SHL
Arithmetic shift right SHRA
Arithmetic shift left SHLA
Rotate right ROR
Rotate left ROL
Rotate mgmt through carry RORC
Rotate left through carry ROLC

(3)Program Control:
Instructions are always stored in successive memory locations. When processed in the
CPU, the instructions are fetched from consecutive memory locations and executed
Status Bit Conditions
It is sometimes convenient to supplement the ALU circuit in the CPU with a status
register where status b it conditions can be stored for further analysis. Status bits are also
called condition-code bits or flag bits. The four status bits are symbolized by C, S, Z, and V. The

bits are set or cleared as a result of an operation performed in the ALU.

 1. Bit C (carry) is set to 1 if the end cany C8 is 1. It is cleared to 0 if the carry is 0.
2. Bit S (sign) is set to 1 if the highest-order bit F? is 1. It is set to 0 if the bit is 0.
3. Bit Z (zero) is set to 1 if the output of the ALU contains all 0's. It is cleared to 0
otherwise.
In other words, Z = 1 if the output is zero and Z = 0 if the output is not zero.
4. Bit V (overflow) is set to 1 if the exclusive-OR of the last two carries is equal to 1,
and Cleared to 0 otherwise. This is the condition for an overflow when negative
numbers are In 2's complement.
COMPUTER ARITHMETIC

Introduction:

Data is manipulated by using the arithmetic instructions in digital computers. Data is

manipulated to produce results necessary to give solution for the computation
problems. The Addition, subtraction, multiplication and division are the four basic
arithmetic operations. If we want then we can derive other operations by using these
four operations.

To execute arithmetic operations there is a separate section called arithmetic processing

unit in central processing unit. The arithmetic instructions are performed generally on
binary or decimal data. Fixed-point numbers are used to represent integers or fractions.
We can have signed or unsigned negative numbers. Fixed-point addition is the simplest
arithmetic operation.

If we want to solve a problem then we use a sequence of well-defined steps. These

steps are collectively called algorithm. To solve various problems we give algorithms.

In order to solve the computational problems, arithmetic instructions are used in digital
computers that manipulate data. These instructions perform arithmetic calculations.

And these instructions perform a great activity in processing data in a digital

computer. As we already stated that with the four basic arithmetic operations
addition, subtraction, multiplication and division, it is possible to derive other
arithmetic operations and solve scientific problems by means of numerical
analysis methods.

A processor has an arithmetic processor(as a sub part of it) that executes

arithmetic operations. The data type, assumed to reside in processor, registers
during the execution of an arithmetic instruction. Negative numbers may be in a
signed magnitude or signed complement representation. There are three ways
of representing negative fixed point - binary numbers signed magnitude, signed
1’s complement or signed 2’s complement. Most computers use the signed
magnitude representation for the mantissa.

Addition and Subtraction :

Addition and Subtraction with Signed –Magnitude Data

We designate the magnitude of the two numbers by A and B. Where the signed
numbers are added or subtracted, we find that there are eight different
conditions to consider, depending on the sign of the numbers and the operation
performed. These conditions are listed in the first column of Table 4.1. The other
columns in the table show the actual operation to be performed with the
 magnitude of the numbers. The last column is needed to present a negative
zero. In other words, when two equal numbers are subtracted, the result should
be +0 not -0.

The algorithms for addition and subtraction are derived from the table and can
be stated as follows (the words parentheses should be used for the subtraction
algorithm)
addition and Subtraction of Signed-Magnitude Numbers
Computer Arithmetic 2 Addition and Subtraction

SIGNED MAGNITUDEADDITION AND SUBTRACTION

Addition: A + B ; A: Augend; B: Addend
Subtraction: A - B: A: Minuend; B: Subtrahend

Add Subtract Magnitude

Operation Magnitude When A>B When A<B When A=B
(+A) + (+B) +(A + B)
(+A) + (- B) +(A - B) - (B - A) +(A - B)
(- A) + (+B) - (A - B) +(B - A) +(A - B)
(- A) + (- B) - (A + B)
(+A) - (+B) +(A - B) - (B - A) +(A - B)
(+A) - (- B) +(A + B)
(- A) - (+B) - (A + B)
(- A) - (- B) - (A - B) +(B - A) +(A - B)

Hardware Implementation Bs B Register

AVF Complementer E M(Mode Control)

Output
Parallel Adder Input
Carry
Carry
S
As A Register Load Sum
Computer Organization Prof. H. Yoon

Computer Arithmetic 3 Addition and Subtraction

SIGNED 2’S COMPLEMENT ADDITION AND SUBTRACTION

Hardware
B Register

Complementer and
V
Parallel Adder
Overflow

AC

Algorithm
Subtract Add

Minuend in AC Augend in AC
Subtrahend in B Addend in B

AC  AC + B’+ 1 AC  AC + B
V  overflow V  overflow

END END

Computer Organization Prof. H. Yoon

Algorithm:

The flowchart is shown in Figure 7.1. The two signs A, and B, are
compared by an exclusive-OR gate.

If the output of the gate is 0 the signs

are identical; If it is 1, the signs are
different.

For an add operation, identical signs dictate that the magnitudes be

added. For a subtract operation, different signs dictate that the
magnitudes be added.

The magnitudes are added with a microoperation EA A + B, where EA is a

register that combines E and A. The carry in E after the addition constitutes an
overflow if it is equal to 1. The value of E is transferred into the add-overflow
flip-flop AVF.

The two magnitudes are subtracted if the signs are different for an add
operation or identical for a subtract operation. The magnitudes are
subtracted by adding A to the 2's complemented B. No overflow can occur if
the numbers are subtracted so AVF is cleared to 0.

1 in E indicates that A >= B and the number in A is the correct result. If this
numbs is zero, the sign A must be made positive to avoid a negative zero.

0 in E indicates that A < B. For this case it is necessary to take the 2's
complement of the value in A. The operation can be done with one
microoperation A A' +1.
However, we assume that the A register has circuits for microoperations
complement and increment, so the 2's complement is obtained from these
two microoperations.

In other paths of the flowchart, the sign of the result is the same as the sign of
A. so no change in A is required. However, when A < B, the sign of the result is
the complement of the original sign of A. It is then necessary to complement
A, to obtain the correct sign.

The final result is found in register A and its sign in As. The value in AVF
provides an overflow indication. The final value of E is immaterial.

Figure 7.2 shows a block diagram of the hardware for implementing the
addition and subtraction operations.

It consists of registers A and B and sign flip-flops As and

Bs. Subtraction is done by adding A to the 2's
complement of B.

The output carry is transferred to flip-flop E , where it can be checked to

determine the relative magnitudes of two numbers.

The add-overflow flip-flop AVF holds the overflow bit when A and B are added.

The A register provides other microoperations that may be needed when

we specify the sequence of steps in the algorithm.
Multiplication Algorithm:

In the beginning, the multiplicand is in B and the multiplier in Q. Their corresponding

signs are in Bs and Qs respectively. We compare the signs of both A and Q and set to
corresponding sign of the product since a double-length product will be stored in
registers A and Q. Registers A and E are cleared and the sequence counter SC is set to
the number of bits of the multiplier. Since an operand must be stored with its sign, one
bit of the word will be occupied by the sign and the magnitude will consist of n-1 bits.

Now, the low order bit of the multiplier in Qn is tested. If it is 1, the multiplicand (B) is
added to present partial product (A), 0 otherwise. Register EAQ is then shifted once to
the right to form the new partial product. The sequence counter is decremented by 1
and its new value checked. If it is not equal to zero, the process is repeated and a new
partial product is formed. When SC = 0 we stops the process.
Booth’s algorithm :
Booth algorithm gives a procedure for multiplying binary integers in
signed- 2’s complement representation.

It operates on the fact that strings of 0’s in the multiplier require no addition but just
shifting, and a stringk+1of 1’s
m
in the multiplier from bit weight 2k to weight 2m
can be treated as 2 – 2 .

For example, the binary number 001110 (+14) has a string 1’s from 2 3 to 21
(k=3, m=1). The number can be represented as 2 k+1 – 2m. = 24 – 21 = 16 – 2 =
14. Therefore, the multiplication M X 14, where M is the multiplicand and 14
the multiplier, can be done as M X 24 – M X 21.
Thus the product can be obtained by shifting the binary multiplicand M four
times to the left and subtracting M shifted left once.
As in all multiplication schemes, booth algorithm requires
examination of the multiplier bits and shifting of partial product.

Prior to the shifting, the multiplicand may be added to the partial product,
subtracted from the partial, or left unchanged according to the following
rules:
1. The multiplicand is subtracted from the partial product upon encountering
the first least significant 1 in a string of 1’s in the multiplier.

2. The multiplicand is added to the partial product upon encountering the first
0 in a string of 0’s in the multiplier.

3. The partial product does not change when multiplier bit is identical to
the previous multiplier bit.

The algorithm works for positive or negative multipliers in 2’s

complement representation.

This is because a negative multiplier ends with a string of 1’s and the last
operation will be a subtraction of the appropriate weight.

The two bits of the multiplier in Qn and Qn+1 are inspected.

If the two bits are equal to 10, it means that the first 1 in a string of 1 's has
been encountered. This requires a subtraction of the multiplicand from the
partial product in AC.

If the two bits are equal to 01, it means that the first 0 in a string of 0's has
been encountered. This requires the addition of the multiplicand to the
partial product in AC.

When the two bits are equal, the partial product does not change.
Division Algorithms
Division of two fixed-point binary numbers in signed magnitude representation is
performed with paper and pencil by a process of successive compare, shift and subtract
operations. Binary division is much simpler than decimal division because here the
quotient digits are either 0 or 1 and there is no need to estimate how many times the
dividend or partial remainder fits into the divisor. The division process is described in
Figure

The devisor is compared with the five most significant bits of the dividend.
Since the 5-bit number is smaller than B, we again repeat the same process.
Now the 6-bit number is greater than B, so we place a 1 for the quotient bit in
the sixth position above the dividend. Now we shift the divisor once to the
right and subtract it from the dividend. The difference is known as a partial
remainder because the division could have stopped here to obtain a
quotient of 1 and a remainder equal to the partial remainder. Comparing
a partial remainder with the divisor continues the process. If the partial
remainder is greater than or equal to the divisor, the quotient bit is equal to
1. The divisor is then shifted right and subtracted from the partial remainder.
If the partial remainder is smaller than the divisor, the quotient bit is 0 and no
subtraction is needed. The divisor is shifted once to the right in any case.
Obviously the result gives both a quotient and a remainder.

Hardware Implementation for Signed-Magnitude Data

In hardware implementation for signed-magnitude data in a digital computer,

it is convenient to change the process slightly. Instead of shifting the divisor to
the right, two dividends, or partial remainders, are shifted to the left, thus
leaving the two numbers in the required relative position. Subtraction is
achieved by adding A to the 2's complement of B. End carry gives the
information about the relative magnitudes.
 The hardware required is identical to that of multiplication. Register EAQ is
now shifted to the left with 0 inserted into Qn and the previous value of E is
lost. The example is given in Figure 4.10 to clear the proposed division
process. The divisor is stored in the B register and the double-length dividend
is stored in registers A and Q. The dividend is shifted to the left and the divisor
is subtracted by adding its 2's complement value. E

Hardware Implementation for Signed-Magnitude Data

Algorithm:

Example of Binary Division with Digital Hardware

Floating-point Arithmetic operations :

In many high-level programming languages we have a facility for specifying floating-

point numbers. The most common way is by a real declaration statement. High level
programming languages must have a provision for handling floating-point arithmetic
operations. The operations are generally built in the internal hardware. If no hardware is
available, the compiler must be designed with a package of floating-point software
subroutine. Although the hardware method is more expensive, it is much more efficient
than the software method. Therefore, floating- point hardware is included in most
computers and is omitted only in very small ones.

Basic Considerations :

There are two part of a floating-point number in a computer - a mantissa m and an

exponent e. The two parts represent a number generated from multiplying m times a
radix r raised to the value of e. Thus

m x re

The mantissa may be a fraction or an integer. The position of the radix point and the
value of the radix r are not included in the registers. For example, assume a fraction
representation and a radix
10. The decimal number 537.25 is represented in a register with m = 53725 and e = 3 and
is interpreted to represent the floating-point number

.53725 x 103

A floating-point number is said to be normalized if the most significant digit of the

mantissa in nonzero. So the mantissa contains the maximum possible number of
significant digits. We cannot normalize a zero because it does not have a nonzero digit.
It is represented in floating-point by all 0’s in the mantissa and exponent.

Floating-point representation increases the range of numbers for a given register.

Consider a computer with 48-bit words. Since one bit must be reserved for the sign, the
range of fixed-point integer numbers will be + (247 – 1), which is approximately + 101 4.
The 48 bits can be used to represent a floating-point number with 36 bits for the
mantissa and 12 bits for the exponent. Assuming fraction representation for the
mantissa and taking the two sign bits into consideration, the range of numbers that can
be represented is

+ (1 – 2-35) x 22047
This number is derived from a fraction that contains 35 1’s, an exponent of 11 bits
(excluding its sign), and because 211–1 = 2047. The largest number that can be
accommodated is approximately 10615. The mantissa that can accommodated is 35 bits
(excluding the sign) and if considered as an integer it can store a number as large as (2 35
–1). This is approximately equal to 10 10, which is equivalent to a decimal number of 10
digits.

Computers with shorter word lengths use two or more words to represent a floating-
point number. An 8-bit microcomputer uses four words to represent one floating-point
number. One word of 8 bits are reserved for the exponent and the 24 bits of the other
three words are used in the mantissa.
Arithmetic operations with floating-point numbers are more complicated than with
fixed-point numbers. Their execution also takes longer time and requires more complex
hardware. Adding or subtracting two numbers requires first an alignment of the radix
point since the exponent parts must be made equal before adding or subtracting the
mantissas. We do this alignment by shifting one mantissa while its exponent is adjusted
until it becomes equal to the other exponent. Consider the sum of the following
floating-point numbers:

.5372400 x 102

+ .1580000 x 10-1

Floating-point multiplication and division need not do an alignment of the mantissas.

Multiplying the two mantissas and adding the exponents can form the product. Dividing
the mantissas and subtracting the exponents perform division.

The operations done with the mantissas are the same as in fixed-point numbers, so the
two can share the same registers and circuits. The operations performed with the
exponents are compared and incremented (for aligning the mantissas), added and
subtracted (for multiplication) and division), and decremented (to normalize the result).
We can represent the exponent in any one of the three representations - signed-
magnitude, signed 2’s complement or signed 1’s complement.
Biased exponents have the advantage that they contain only positive numbers. Now it
becomes simpler to compare their relative magnitude without bothering about their
signs. Another advantage is that the smallest possible biased exponent contains all
zeros. The floating-point representation of zero is then a zero mantissa and the smallest
possible exponent.

Register Configuration

The register configuration for floating-point operations is shown in figure 4.13. As a rule,
the same registers and adder used for fixed-point arithmetic are used for processing
the mantissas. The difference lies in the way the exponents are handled.

The register organization for floating-point operations is shown in Fig. 4.13. Three
registers are there, BR, AC, and QR. Each register is subdivided into two parts. The
mantissa part has the same uppercase letter symbols as in fixed-point representation.
The exponent part may use corresponding lower-case letter symbol.
omputer Arithmetic 14 Floating Point Arithmetic

FLOATING POINT ARITHMETIC OPERATIONS

F = m x re
where m: Mantissa
r: Radix
e: Exponent

Registers for Floating Point Arithmetic

Bs B b BR

Parallel Adder
E Parallel Adder and Comparator

A s A1 A a AC

Qs Q q QR

Computer Organization Prof. H. Yoon

Figure 4.13: Registers for Floating Point arithmetic operations

Assuming that each floating-point number has a mantissa in signed-magnitude

representation and a biased exponent. Thus the AC has a mantissa whose sign is in As,
and a magnitude that is in A. The diagram shows the most significant bit of A, labeled by
A1. The bit in his position must be a 1 to normalize the number. Note that the symbol
AC represents the entire register, that is, the concatenation of As, A and a.

In the similar way, register BR is subdivided into Bs, B, and b and QR into Qs, Q and q. A
parallel-adder adds the two mantissas and loads the sum into A and the carry into E. A
separate parallel adder can be used for the exponents. The exponents do not have a
district sign bit because they are biased but are represented as a biased positive
quantity. It is assumed that the floating- point number are so large that the chance of an
exponent overflow is very remote and so the exponent overflow will be neglected. The
exponents are also connected to a magnitude comparator that provides three binary
outputs to indicate their relative magnitude.

The number in the mantissa will be taken as a fraction, so they binary point is assumed
to reside to the left of the magnitude part. Integer representation for floating point
causes certain scaling problems during multiplication and division. To avoid these
problems, we adopt a fraction representation.

The numbers in the registers should initially be normalized. After each arithmetic
operation, the result will be normalized. Thus all floating-point operands are always
normalized.
Addition and Subtraction of Floating Point Numbers
During addition or subtraction, the two floating-point operands are kept in AC and
BR. The sum or difference is formed in the AC. The algorithm can be divided into
four consecutive parts:

1. Check for zeros.

2. Align the mantissas.

3. Add or subtract the mantissas

4. Normalize the result

A floating-point number cannot be normalized, if it is 0. If this number is used for

computation, the result may also be zero. Instead of checking for zeros during the
normalization process we check for zeros at the beginning and terminate the process if
necessary. The alignment of the mantissas must be carried out prior to their operation.
After the mantissas are added or subtracted, the result may be un-normalized. The
normalization procedure ensures that the result is normalized before it is transferred to
memory.

If the magnitudes were subtracted, there may be zero or may have an underflow in the
result. If the mantissa is equal to zero the entire floating-point number in the AC is
cleared to zero. Otherwise, the mantissa must have at least one bit that is equal to 1.
The mantissa has an underflow if the most significant bit in position A1, is 0. In that
case, the mantissa is shifted left and the exponent decremented. The bit in A1 is
checked again and the process is repeated until A1 = 1. When A1 = 1, the mantissa is
normalized and the operation is completed.
Algorithm for Floating Point Addition and Subtraction
 Multiplication

The multiplication of two floating-point numbers requires that we multiply the

mantissas and add the exponents. No comparison of exponents or alignment of
mantissas is necessary. The multiplication of the mantissas is performed in the
same way as in fixed-point to provide a double-precision product. The double-
precision answer is used in fixed-point numbers to increase the accu racy of the
product. In floating-point, the range of a single-precision mantissa combined with the
exponent is usually accurate enough so that only single precision numbers are
maintained. Thus the half most significant bits of the mantissa product and the
exponent wil be taken together to form a single precision floating-point product.

The multiplication algorithm can be subdivided into four parts:

1.Check for zeros.

2.Add the exponents.
3.Multiply the mantissas.
4.Normalize the product.

Steps 2 and 3 can be done simultaneously if separate adders are available

for the mantissas and exponents.
The two operands are checked to determine if they contain a zero. If either
operand is equal to zero, the product in the AC is set to zero and the
operation is
temtinated. If neither of the operands is equal to zero, the process
continues with the exponent addition.
The exponent of the multiplier is in q and the adder is between
exponents a and b. It is necessary to transfer the exponents from q to a, add the
two exponents, and transfer the sum into a . Since both exponents are biased
by the
addition of a constant, the exponent sum wil have double this bias. The
correct biased exponent for the product is obtained by subtracting the bias
number from the sum.
The multiplication of the mantissas is done as in the fixed-point case
with the product residing in A and Q. Overflow cannot occur during
multiplication, so there is no need to check for it.
The product may have an underflow, so the most significant bit in A is
checked. If it is a 1, the product is already normalized. If it is a 0, the
mantissa in AQ is shifted left and the exponent decremented. Note that
only one normalization shift is necessary. The multiplier and multiplicand
were originally normalized and contained fractions. The smallest
normalized operand is 0.1, so the smallest possible product is 0.01.
Therefore, only one leading zero may occur.
Although the low-order half of the mantissa is in Q, we do not use it for
the floating-point product. Only the value in the AC is taken as the
product.
Division
Floating-point division requires that the exponents be subtracted and the
mantissas divided. The mantissa division is done as in fixed-point except
that the dividend has a single-precision mantissa that is placed in the AC .
Remem ber that the mantissa dividend is a fraction and not an integer. For
 integer representation, a single-precision dividend must be placed in register
Q and register A must be cleared. The zeros in A are to the left of the
binary point and have no signllicance. In fraction representation, a single-
precision divi dend is placed in register A and register Q is cleared. The zeros
in Q are to the right of the binary point and have no signllicance.
The check for divide-overflow is the same as in fixed-point representation.
However, with floating-point numbers the divide-overflow imposes no
problems. If the dividend is greater than or equal to the divisor, the dividend
fraction is shifted to the right and its exponent incremented by 1. For normal
ized operands this is a sufficient operation to ensure that no mantissa divide-
overflow wil occur. The operation above is referred to as a dividend
alignment

The division of two normalized floating-point numbers will always result

in a normalized quotient provided that a dividend alignment is carried out
before the division. Therefore, unlike the other operations, the quotient
obtained after the division does not require a normalization.
The division algorithm can be subdivided into five parts:

1. Check for zeros.

2. Initialize registers and evaluate the sign.
3.Align the dividend.
4.Subtract the exponents.
5.Divide the mantissas

The two operands are checked for zero. If the divisor is zero, it indicates an
attempt to divide by zero, which is an illegal operation. The operation is
terminated with an error message. An alternative procedure would be to set the
quotient in QR to the most positive number possible (if the dividend is positive)
or to the most negative possible (if the dividend is negative). If the dividend in
AC is zero, the quotient in QR is made zero and the operation terminates.
If the operands are not zero, we proceed to determine the sign of the
quotient and store it in Q, . The sign of the dividend in A, is left unchanged to be
the sign of the remainder. The Q register is cleared and the sequence counter SC is
set to a number equal to the number of bits in the quotient.
The dividend alignment is similar to the divide-overflow check in the fixed-
point operation. The proper alignment requires that the fraction dividend be
smaller than the divisor. The two fractions are compared by a subtraction test.
The carry in E determines their relative magnitude. The dividend fraction is
restored to its original value by adding the divisor. If A >= B, it is necessary to
shift A once to the right and increment the dividend exponent. Since both
operands are normalized, this alignment ensures that A < B.
Next, the divisor exponent is subtracted from the dividend exponent. Since
both exponents were originally biased, the subtraction operation gives
the difference without the bias. The bias is then added and the result transferred
into q because the quotient is formed in QR .
 The magnitudes of the mantissas are divided as in the fixed-point case. After
the operation, the mantissa quotient resides in Q and the remainder in

A. The floating-point quotient is already normalized and resides in QR. The

exponent of the remainder should be the same as the exponent of the dividend. The
binary point for the remainder mantissa lies (n - 1) positions to the left of A1•
The remainder can be converted to a normalized fraction by subtracting n - 1
from the dividend exponent and by shift and decrement until the bit in A1 is equal
to 1. This is not shown in the flow chart and is left as an exercise.
Division of floating..point numbers