COMPUTER ORGANIZATION AND ARCHITECTURE (CS304PC)

COURSE PLANNER
I. Course Overview:

1 To know the background of internal communication of computer

2 To have better idea on how to write assemble language programs

3 To be clear with memory management techniques

4 To better with IO devices communication with processor

5 To notice how to perform computer arithmetic operations

6 To be clear with pipeline procedure and multi processors.

II. Prerequisites:

1. Digital Logic Design

III. Course Objectives:

1 The purpose of the course is to introduce principles of computer organization and the
basic architectural concepts.
2 It begins with basic organization, design, and programming of a simple digital computer
and introduces simple register transfer language to specify various computer operations.
Topics include computer arithmetic, instruction set design, microprogrammed control
3 unit, pipelining and vector processing, memory organization and I/O systems, and
multiprocessors

IV.Course Outcomes:

After completing this course the student must demonstrate the knowledge and ability to:

S.No Description Bloom’s Taxonomy Level

Understand the basics of instructions sets and their
1 L2:Understand
impact on processor design
Demonstrate an understanding of the design of the
2 L3 : Application
functional units of a digital computer system.
Evaluate cost performance and design trade-offs in
3 designing and constructing a computer processor L3 : Application
including memory.
4 Design a pipeline for consistent execution of L5 : Synthesize

CSE II Year I - Semester

 instructions with minimum hazards
5 Manipulate representations of numbers stored in L3 : Application
digital computers

V. How program outcomes are assessed:

Proficiency
Program Level assessed by
Outcomes (PO)
Engineering knowledge: Apply the knowledge of
mathematics, science, engineering fundamentals, and an Assignment
PO1 engineering specialization to the solution of complex 3 Mock test
engineering problems related to Computer Quiz
Science and Engineering.
Problem analysis: Identify, formulate, review research
literature, and analyze complex engineering problems
Assignment
related to Computer Science and Engineering and
PO2 3 Mock test
reaching substantiated conclusions using first principles
Quiz
of mathematics, natural sciences, and engineering
sciences.
Design/development of solutions: Design solutions for
complex engineering problems related to Computer
Science and Engineering and design system components Assignment
PO3 or processes that meet the specified needs with 3 Mock test
appropriate consideration for the public health and Quiz
safety, and the cultural, societal, and environmental
considerations.
Conduct investigations of complex problems: Use Assignment
research-based knowledge and research methods Mock test
PO4 including design of experiments, 3 Quiz
analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
Modern tool usage: Create, select, and apply Mini Project
appropriate techniques, resources, and modern
PO5 engineering and IT tools including prediction and 3
modeling to complex engineering activities with an
understanding of the limitations.
The engineer and society: Apply reasoning informed by Quiz
the contextual knowledge to assess societal, health,
PO6 safety, legal and cultural issues and the consequent 1
responsibilities relevant to the Computer Science and
Engineering professional engineering practice.
Environment and sustainability: Understand the
impact of the Computer Science and Engineering
PO7 professional engineering solutions in societal and 2 Quiz
environmental contexts, and demonstrate the knowledge
of, and need for sustainable development.
Ethics: Apply ethical principles and commit to
PO8 professional ethics and responsibilities and norms of the - -
engineering practice.

CSE II Year I - Semester

 Individual and team work: Function effectively as an Quiz
PO9 individual, and as a member or leader in diverse teams, 3
and in multidisciplinary
settings.
Communication: Communicate effectively on complex
engineering activities with the engineering community
PO10 and with society at large, such as, being able to
- -
comprehend and write effective reports and design
documentation, make effective presentations, and give
and receive clear instructions.
Project management and finance: Demonstrate
knowledge and understanding of the engineering and
PO11 management principles and apply these to one’s own - -
work, as a member and leader in a team, to manage
projects and in multidisciplinary environments.
Life-long learning: Recognize the need for, and have the Competitive
preparation
PO12 and ability to engage in independent and life-long 3 Examinatio
learning in the broadest context of technological change. ns

1: Slight (Low) 2: Moderate (Medium) 3: Substantial (High) - : None

• End-of-course surveys (Quarterly).

• Instructor evaluation reports (Quarterly).
• Department performance report (Quarterly).
• Student exit survey (Yearly).
• Alumni survey (Yearly).
• Alumni Advisory Board (Once or twice yearly).
• Student Advisory Committee (Once or twice yearly).

VI. How Program Specific Outcomes are Assessed:

Proficiency
Program Specific Outcomes (PSO) Level assessed by
Foundation of mathematical concepts:
PSO1 To use mathematical methodologies to crack problem 3
Technical Paper
using suitable mathematical analysis, data structure and Writing
suitable algorithm.
Foundation of Computer System: The ability to interpret
PSO2 the fundamental concepts and methodology of computer
systems. Students can understand the functionality of 3 Slip Test
hardware and software aspects of computer systems.
Foundations of Software development: The ability to
grasp the software development lifecycle and
methodologies of software systems. Possess competent Research
PSO3 skills and knowledge of software design process. 2 oriented
Familiarity and practical proficiency with a broad area of Studies
programming concepts and provide new ideas and
innovations towards research.

CSE II Year I - Semester

VII. Scope of Course:

At the end of the course the student would:

1. Ability to understand basic structure of computer.
2. Ability to perform computer arithmetic operations.
3. Ability to understand control unit operations.
4. Ability to understand the concept of cache mapping techniques.
5. Ability to understand the concept of I/O organization.
6. Ability to conceptualize instruction level parallelism.

VIII. Syllabus:

UNIT - I
Digital Computers: Introduction, Block diagram of Digital Computer, Definition of
Computer Organization, Computer Design and Computer Architecture.
Register Transfer Language and Micro operations: Register Transfer language,
Register Transfer, Bus and memory transfers, Arithmetic Micro operations, logic micro
operations, shift micro operations, Arithmetic logic shift unit.
Basic Computer Organization and Design: Instruction codes, Computer Registers
Computer instructions, Timing and Control, Instruction cycle, Memory Reference
Instructions, Input – Output and Interrupt.
UNIT - II
Microprogrammed Control: Control memory, Address sequencing, micro program
example, design of control unit.
Central Processing Unit: General Register Organization, Instruction Formats,
Addressing modes, Data Transfer and Manipulation, Program Control.
UNIT - III
Data Representation: Data types, Complements, Fixed Point Representation, Floating Point
Representation.
Computer Arithmetic: Addition and subtraction, multiplication Algorithms, Division
Algorithms, Floating – point Arithmetic operations. Decimal Arithmetic unit, Decimal
Arithmetic operations.
UNIT - IV
Input-Output Organization: Input-Output Interface, Asynchronous data transfer, Modes of
Transfer, Priority Interrupt Direct memory Access.
Memory Organization: Memory Hierarchy, Main Memory, Auxiliary memory,
Associate Memory, Cache Memory.
UNIT - V
Reduced Instruction Set Computer: CISC Characteristics, RISC Characteristics.
Pipeline and Vector Processing: Parallel Processing, Pipelining, Arithmetic Pipeline,
Instruction Pipeline, RISC Pipeline, Vector Processing, Array Processor.
Multi Processors: Characteristics of Multiprocessors, Interconnection Structures,
Interprocessor arbitration, Interprocessor communication and synchronization, Cache
Coherence.

CSE II Year I - Semester

TEXT BOOK:
1. Computer System Architecture – M. Moris Mano, Third Edition, Pearson/PHI.

REFERENCES:
1. Computer Organization – Car Hamacher, Zvonks Vranesic, Safea Zaky, Vth
Edition, McGraw Hill.
2. Computer Organization and Architecture – William Stallings Sixth Edition,
Pearson/PHI.
3. Structured Computer Organization – Andrew S. Tanenbaum, 4th Edition,
PHI/Pearson.

IX. LESSON PLAN-COURSE SCHEDULE:

Teaching Text
S.No Unit Topics To be Covered Course Learning Outcome
Aids Book
Digital Computers:
1 Define a Computer BB, PPT T1
Introduction
Block diagram of Digital Discuss about the Block Diagram of a
2 BB, PPT T1
Computer Computer
Definition of Computer
Organization, Computer
3 Define CO,CA and CD BB, PPT T1
Design and Computer
Architecture.
Register Transfer Language
and Micro operations:
4 Discuss about RTL BB, PPT T1
Register Transfer language,
Register Transfer
5 Bus and memory transfers Discuss about bus ,memory transfers BB, PPT T1
6 Arithmetic Micro operations Explain Arithmetic Micro operations BB, PPT T1
7 Arithmetic Micro operations Explain Arithmetic Micro operations BB, PPT T1
8 logic micro operations Explain logic micro operations BB, PPT T1
9 I logic micro operations Explain logic micro operations BB, PPT T1
10 shift micro operations Explain shift micro operations BB, PPT T1
11 shift micro operations Explain shift micro operations BB, PPT T1
12 Arithmetic logic shift unit. Explain ALU BB, PPT T1
13 Arithmetic logic shift unit. Explain ALU BB, PPT T1
Basic Computer List Computer Registers
14 Organization and Design: BB, PPT T1
Instruction codes,
15 Computer Registers List Computer Registers BB, PPT T1
16 Computer instructions Explain computer instructions BB, PPT T1
17 Timing and Control Discuss Timing And Control BB, PPT T1
18 Instruction cycle Define Instruction Cycle BB, PPT T1
Memory Reference
19 BB, PPT T1
Instructions, Explain memory and I/O instructions
20 Input – Output and Interrupt. Explain I /O Interrupt BB, PPT T1
Microprogrammed Control: Discuss different terminology in MPU
21 BB, PPT T1
Control memory,
22 II Address sequencing BB, PPT T1
Discuss Address Sequencing Tech.
23 Micro program example Write example micro programs BB, PPT T1

CSE II Year I - Semester

 24 Micro program example Write example micro programs BB, PPT T1
25 Design of control unit. Design control unit BB, PPT T1
26 Design of control unit. Design control unit BB, PPT T1
Central Processing Unit:
27 General Register Discuss Register Org BB, PPT T1
Organization,
28 ** Stack Organization Discuss Stack Org BB, PPT T1
Instruction Formats: Three
29 Address Instructions, Two Explain Instruction Formats BB, PPT T1
Address Instructions
Instruction Formats : One
30 Address Instructions, Zero Explain Instruction Formats BB, PPT T1
Address Instructions
31 Addressing modes Explain Addressing mode of operation BB, PPT T1
32 Addressing modes Explain Addressing mode of operation BB, PPT T1
Data Transfer and
33 BB, PPT T1
Manipulation Explain Data Transfer and Manipulation
Data Transfer and
34 Explain Data Transfer and Manipulation BB, PPT T1
Manipulation
35 Program Control. Define Program Control. BB, PPT T1
36 Program Control. Define Program Control. BB, PPT T1
Data Representation: Data
37 BB, PPT T1
types Explain data representation
Complements (r-1)'s
Explain 1's and r's complement with
38 Complement and (r's BB, PPT T1
example
Complement)
39 Fixed Point Representation, Explain Fixed Point Representation, BB, PPT T1
40 Fixed Point Representation, Explain Fixed Point Representation, BB, PPT T1
Floating Point
41 Explain Floating Point Representation. BB, PPT T1
Representation.
Computer Arithmetic:
42 BB, PPT T1
Addition and subtraction Explain computer arithmetic operations
Computer Arithmetic:
43 III BB, PPT T1
Addition and subtraction Explain computer arithmetic operations
44 Multiplication Algorithms Design multiplication algorithm BB, PPT T1
45 Multiplication Algorithms Design multiplication algorithm BB, PPT T1
46 Division Algorithms Design multiplication algorithm BB, PPT T1
47 Division Algorithms Design division algorithm BB, PPT T1
Floating – point Arithmetic
48 Explain floating point arithmetic BB, PPT T1
operations.
Floating – point Arithmetic
49 BB, PPT T1
operations. Explain floating point arithmetic
50 Decimal Arithmetic unit Explain DAU BB, PPT T1
51 Decimal Arithmetic unit Explain DAU BB, PPT T1
Input-Output Organization:
52 Define IOI BB, PPT T1
Input-Output Interface
53 Asynchronous data transfer Discuss Asynchronous Data BB, PPT T1
54 Modes of Transfer Explain Modes of transfer BB, PPT T1
IV
55 Priority Interrupt Explain Priority Interrupt BB, PPT T1
56 Direct memory Access. Explain DMA BB, PPT T1
Discuss Memory Hierarchy, Explain Main Memory, Discuss
57 BB, PPT T1
Main Memory Memory Hierarchy

CSE II Year I - Semester

 58 Auxiliary memory Explain Auxiliary memory BB, PPT T1
59 Associate Memory Explain Associate Memory BB, PPT T1
60 Cache Memory Explain Cache Memory BB, PPT T1
Reduced Instruction Set
61 Computer: Define RISC & CISC BB, PPT T1
CISC Characteristics,
62 RISC Characteristics. Difference btw RISC & CISC BB, PPT T1
Pipeline and Vector
63 Expain Pipeline and Vector Processing BB, PPT T1
Processing:
64 Parallel Processing, discuss about Parallel Processing BB, PPT T1
Pipelining, Arithmetic
65 Explain pipelining types BB, PPT T1
Pipeline,
66 Instruction Pipeline, Explain pipelining types BB, PPT T1
67 RISC Pipeline, Explain pipelining types BB, PPT T1
V
68 Vector Processing, Explain Vector Processing BB, PPT T1
69 Array Processor Expalin Vector Processing BB, PPT T1
Multi Processors:
Explain Characteristics of
70 Characteristics of BB, PPT T1
Multiprocessor
Multiprocessors,
71 Interconnection Structures, Explain Interconnection Structures BB, PPT T1
72 Inter - Processor arbitration, Define Inter - Processor arbitration BB, PPT T1
Inter - Processor
73 communication and Define IPC And Synchronization BB, PPT T1
synchronization,
74 Cache Coherence. Discuss about Cache Coherence Prob. BB, PPT T1

X. MAPPING COURSE OUTCOMES LEADING TO THE ACHIEVEMENT OF

PROGRAM OUTCOMES AND PROGRAM SPECIFIC OUTCOMES:

Program
Program Outcomes Specific
Outcomes
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3

CO1 3 3 - - 3 - 2 - - - - 2 2 3 2
CO2 3 3 - 3 2 - - - - - - - 3 3 2
CO3 3 3 - 3 2 - 2 - - - - - 3 3 2
CO4 3 2 3 2 - - 2 - - - - - 3 2 1
CO5 3 3 3 - 2 - - - 3 - - - 3 3 1
AVG 3.00 2.80 3.00 2.67 2.25 0.00 2.00 0.00 3.00 0.00 0.00 2.00 2.80 2.80 1.60

DESCRIPTIVE QUESTIONS:
UNIT-I
Short Answer Questions-

S.NO QUESTION BLOOMS

Taxonomy

CSE II Year I - Semester

 1. Define Computer Architecture? L1:Remember

2. Define a Digital Computer ? Draw block diagram of L1:Remember

Computer.
3. What is the need of Register? Explain the different L1:Understand
types of Registers.
4. L1:Understand
What is control memory?
5. Define a Micro Program & Micro Instruction? L1:Remember

Long Answer Questions-

S.NO QUESTION BLOOMS

Taxonomy
1. How to do address sequencing with diagram. L2:Understand

2. What is instruction format? Explain the different L2:Understand

instruction formats in detail.
3. Explain the different phases of Instruction Cycle? L2:Understand

4. Explain the Micro Program Control with Diagram L2:Understand

& Examples?
5. List out any 5 Registers with explains in detail. L1:Remember

6. Demonstrate the Three – State Bus Buffer with neat L2:Understand

diagram
7. List and Explain in detail about the memory L1:Remember
reference Instructions
8. Draw the flowchart for interrupt cycle and L3:Applying
experiment with it with explanation
9. Determine the input-outpu configuration L5: Evaluating

10. Explain the stored program organization with neat L2:Understand

diagram

UNIT-2
Short Answer Questions

S.NO QUESTION BLOOMS

Taxonomy
1. Define Data path. L1:Remember

2. Define Latency and throughput L1:Remember

3. Discuss the principle operation of micro programmed L2:Understand

control unit.

4. What is control store? L2:Understand

CSE II Year I - Semester

 5. Define Processor clock. L1:Remember

Long Answer Questions-

S.NO QUESTION BLOOMS

Taxonomy
1. Draw and explain typical hardware control unit. L2:Understand

2. Draw and explain about micro program control unit. L2:Understand

3. Write short notes on L2:Understand

(i)Micro instruction format (ii) Symbolic micro
instruction.
4. Explain multiple bus organization in detail. L2:Understand

5. Explain in detail about conditional branching with L2:Understand

neat diagram
6. Explain general register organization in detail with L2:Understand
neat diagrams
7. **Explain Stack organization in detail with neat L2:Understand
diagrams
8. Evaluate the following program using three address L5: Evaluate
Instruction format
X = (A+B) * (C+D)
9. Evaluate the following program using two address L5: Evaluate
Instruction format
X = (A+B) * (C+D)
10. Evaluate the following program using one address L5: Evaluate
Instruction format
X = (A+B) * (C+D)

UNIT-3
Short Answer Questions-

S.NO QUESTION BLOOMS

Taxonomy
1. Convert the following decimal number to the base L5: Evaluate
indicated
a. 7562 to octal
b. 1938 to hexadecimal
2. Find the 1’s and 2’s complement of the following L1: Remember
eight digit binary number
a. 10101110
b. 10000001
3. List the steps of Booth’s Multiplication algorithm L4:Analyze

4. Convert the following decimal number to the base L5: Evaluate

indicated

CSE II Year I - Semester

 a. 17562 to octal
b. 11938 to hexadecimal
5. Briefly explain r’s complement with example L2:Understand

Long Answer Questions-

S.NO QUESTION BLOOMS

Taxonomy
1. Draw and explain the hardware for signed – L2:Understand
magnitude addition and subtraction.
2. Explain the booth’s multiplication algorithm with neat L6:Design
sketch of hardware design
3. Perform division of 1000 and 0011 using restoring L5:Evaluate
division algorithm.
4. Multiply 7 and 3 using Booth’s algorithm. L4:Analyse

5. Draw a flowchart for adding and subtracting two fixed L2:Understand

point binary numbers where negative numbers are
signed 1’s complement presentation
6. Multiply each of the following pairs of signed 2's L4:Analyse
compliment numbers using the Booth multiplication
and n- bit multipliers. In each case assume that A is
multiplicand and B is multiplier. (i) A=010111 and
B=110110. (ii) A=110011 and B=101100
7. Discuss about the IEEE standard for binary floating L2:Understand
point arithmetic
8. Draw the flowchart for divide operation and explain L2:Understand

9. Draw and explain the one stage decimal arithmetic L2:Understand

unit
10. **Explain in detail about the derivation of BCD adder L2:Understand

UNIT-4
Short Answer Questions-

S.NO QUESTION BLOOMS

Taxonomy
1. What is DMA? L2:Understand

2. What is the need of IO Interface? L2:Understand

3. Define Priority Interrupt? L1:Remember

4. List out any 5 IO Devices? L1:Remember

5. What are peripheral devices? Give a note on video L2:Understand

monitors.

CSE II Year I - Semester

 Long Answer Questions-

S.NO QUESTION BLOOMS

Taxonomy
1. What is asynchronous data transfer? Explain the L2:Understand
different types of Asynchronous data transfer
techniques.
2. Explain in detail floating point arithmetic operations L2:Understand
with examples.
3. What is IOP? Explain the communication between L2:Understand
IOP and CPU.
4. Explain the following data transfer modes/techniques. L2:Understand
a)Program Controlled IO
b)Interrupt Initiated IO
5. Write a note on memory hierarchy with the neat L2:Understand
diagram.

6. Consider a cache consisting of 256 blocks of 8 words L4: Analyse

each, for a total of 2048 words, and assume that the
main memory is addressable by a 16-bit address. The
main memory has 64K words which are divided into
8192 blocks of 8 words each. Find the number of bits
in Tag, Block and Word Field of the main memory
address for direct mapping scheme.
7. Explain in detail about DMA operation with neat L2:Understand
diagram
8. Describe in brief the different modes by which data L1: Remember
transfer can take place between a computer unit and
its I/O devices. What is the difference between
synchronous and asynchronous data transfer?
9. Explain in detail about Cache memory mechanisms L2:Understand

10. Explain in detail about Associative memory L2:Understand

mechanisms

UNIT-5
Short Answer Questions-

S.NO QUESTION BLOOMS

Taxonomy
1. List out the memory hierarchy? L1:Remember

2. What is associative memory? L2:Understand

3. What is the need of Cache Memory? L1:Understand

4. Define a Pipeline? Give an example. L2:Remember

5. What is inter process arbitration? L2:Understand

CSE II Year I - Semester

Long Answer Questions-

S.NO QUESTION BLOOMS

Taxonomy
1. Explain the different types of Pipeline techniques. L2:Understand

2. What is mean by IPC. Explain the Concurrency & L2:Understand

Synchronization with IPC?
3. What is Multiprocessors? Explain in detail . L1:Remember

4. List out Cache mapping techniques and Explain all the L2:Understand
mapping techniques?
5. Define Auxiliary memory ? Explain with neat diagram L2:Understand

6. Explain in detail about the RISC Characteristics L2:Understand

7. Explain in detail about the CISC Characteristics L2:Understand

8. Explain in detail about the Instruction Pipeline L2:Understand

9. List the Characteristics of Multiprocessors L4:Analyse

Explain in detail about the Interconnection structures of
Multiprocessor

10. Explain in detail about the Interprocessor arbitration L2:Understand

OBJECTIVE QUESTIONS:
UNIT-I
1. Identify the output Device
a)Scanner b)Keyboard c)Joystick d) Plotter
2. To design a common bus system for 8 registers of 16 bits each, how many
multiplexers are required?
a) MUXs b) 12 MUXs c) 16 MUXs d) 4 MUXs
3. The Complement of decimal number 85 is_____________
a) 84 b) 15 c)14 d)16
4. The memory word that holds the address of the operand in an indirect address
instruction is used as a _______to an array of day
a) Variable b) Pointer c) Expression d) None
5. The memory Address Register (AR) and Program Counter (PC) has___bits
a) 8 b)12 c)16 d)24

6. The Multiplication Operation is implemented with a Sequence of ___ and____

Micro Operations
a) Add & Shift b) Subtract & Shift c) Shift & Complement d) None
7. A mapping procedure is a rule that transforms the instruction code into a
a)Control Memory Address b)Register Memory Address c)Memory Address d)Direct
Memory Address

CSE II Year I - Semester

 8. The decoded instruction is stored in ______
a) IR
b) PC
c) Registers
d) MDR
Answer: a
9. The instruction -> Add LOCA, R0 does _______
a) Adds the value of LOCA to R0 and stores in the temp register
b) Adds the value of R0 to the address of LOCA
c) Adds the values of both LOCA and R0 and stores it in R0
d) Adds the value of LOCA with a value in accumulator and stores it in R0
Answer: c
10. Which registers can interact with the secondary storage?
a) MAR
b) PC
c) IR
d) R0
Answer: c
11. ISP stands for _________
a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
d) Interrupt Service Procedure
Answer: a
12. The internal Components of the processor are connected by _______
a) Processor intra-connectivity circuitry
b) Processor bus
c) Memory bus
d) Rambus
Answer: b
13. The instruction, Add #45,R1 does _______
a) Adds the value of 45 to the address of R1 and stores 45 in that address
b) Adds 45 to the value of R1 and stores it in R1
c) Finds the memory location 45 and adds that content to that of R1
d) None of the mentioned
Answer: b
14. In case of, Zero-address instruction method the operands are stored in _____
a) Registers
b) Accumulators
c) Push down stack
d) Cache
Answer: c
15. Add #45, when this instruction is executed the following happen/s _______
a) The processor raises an error and requests for one more operand
b) The value stored in memory location 45 is retrieved and one more operand is
requested
c) The value 45 gets added to the value on the stack and is pushed onto the stack
d) None of the mentioned
Answer: b

CSE II Year I - Semester

 16. The addressing mode which makes use of in-direction pointers is ______
a) Indirect addressing mode
b) Index addressing mode
c) Relative addressing mode
d) Offset addressing mode
Answer: a
17. The addressing mode/s, which uses the PC instead of a general purpose register is
______
a) Indexed with offset
b) Relative
c) direct
d) both Indexed with offset and direct
Answer: b
18. If we want to perform memory or arithmetic operations on data in Hexa-decimal
mode then we use ___ symbol before the operand.
a) ~
b) !
c) $
d) *
Answer: c
19. The unit which acts as an intermediate agent between memory and backing store to
reduce process time is _____
a) TLB’s
b) Registers
c) Page tables
d) Cache
Answer: d
20. Complete the following analogy :- Registers are to RAM’s as Cache’s are to _____
a) System stacks
b) Overlays
c) Page Table
d) TLB
Answer: d
21. The BOOT sector files of the system are stored in _____
a) Harddisk
b) ROM
c) RAM
d) Fast solid state chips in the motherboard
Answer: b
22. The transfer of large chunks of data with the involvement of the processor is done by
_______
a) DMA controller
b) Arbitrator
c) User system programs
d) None of the mentioned
Answer: a
23. Which of the following technique/s used to effectively utilize main memory ?
a) Address binding
b) Dynamic linking

CSE II Year I - Semester

 c) Dynamic loading
d) Both Dynamic linking and loading
Answer: c
24. Add #%01011101,R1 , when this instruction is executed then _________
a) The binary addition between the operands takes place
b) The Numerical value represented by the binary value is added to the value of R1
c) The addition doesn’t take place , whereas this is similar to a MOV instruction
d) None of the mentioned
Answer: a
Fill in the Blanks:
1. During the execution of the instructions, a copy of the instructions is placed in the
_____
Ans: Cache
2. A processor performing fetch or decoding of different instruction during the execution
of another instruction is called ______
Ans: Pipe-lining
3. When Performing a looping operation, the instruction gets stored in the ______
Ans: Cache
4. The main virtue for using single Bus structure is ____________
Ans: Cost effective connectivity and ease of attaching peripheral devices
5. To extend the connectivity of the processor bus we use ________
Ans: PCI bus
6. The _________micro operator can be used to selective set bit of a register
7. The transfer of information from a memory word to the outside environment is called
a ___________
8. The Data Register sometimes called a ______________register
9. The addressing mode/s, which uses the PC instead of a general purpose register is
______
10. In the following indexed addressing mode instruction, MOV 5(R1),LOC the effective
address is ______ Ans:E=5+[R1]

11. The method of accessing the I/O devices by repeatedly checking the status flags is
___________.
Ans: Status flags
12. The method of accessing the I/O devices by repeatedly checking the status flags is
___________.
Ans: a) Program-controlled I/O
13. The pipelining process is also called as ______.
Ans: Assembly line operation
14. The fetch and execution cycles are interleaved with the help of ________
Ans: Clock
15. To increase the speed of memory access in pipelining, we make use of _______.
Ans: Cache
16. ______ have been developed specifically for pipelined systems.
Ans: Optimizing compilers
17. The clock rate of the processor can be improved by _________
Ans: Reducing the amount of processing done in one step
By using the overclocking method
18. Which representation is most efficient to perform arithmetic operations on the
numbers?

CSE II Year I - Semester

 Ans: 2’S complement
19. The processor keeps track of the results of its operations using a flags called
________
Ans: Conditional code flags
20. The register used to store the flags is called as _________
Ans: Status register
21. The Flag ‘V’ is set to 1 indicates that,
Ans: The operation has resulted in an overflow
22. The most efficient method followed by computers to multiply two unsigned numbers
is _______
Ans: Bit pair recording of multipliers
23. In multiple Bus organisation, the registers are collectively placed and referred as
______
Ans: Register file
24. The main advantage of multiple bus organisation over a single bus is ____
Ans: Reduction in the number of cycles for execution

GATE: (If applicable)

1. Consider a two-level cache hierarchy with L1 and L2 caches. An application
incurs 1.4 memory accesses per instruction on average. For this application, the miss
rate of L1 cache is 0.1; the L2 cache experiences, on average, 7 misses per 1000
instructions. The miss rate L2 expressed correct to two decimal places is _________.
(GATE 2107)
2. A processor can support a maximum memory of 4GB, where the memory is word-
addressable (a word consists of two bytes). The size of the address bus of the
processor is at least bits. (GATE2016)
3. The width of the physical address on a machine is 40 bits. The width of the tag field
in a 512 KB 8-way set associative cache is _______ bits. (GATE 2016)
4. A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit
instruction word has an opcode, two register operands and an immediate operand. The
number of bits available for the immediate operand field is __________. (GATE
2016)
5. Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average
cycles per instruction of four. The same processor is upgraded to a pipelined
processor with five stages; but due to the internal pipelined delay, the clock speed is
reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up
achieved in this pipelined processor is _____. (GATE 2016)

WEBSITES:
http://www.geeksforgeeks.org/computer-organization-and-architecture-gq/
https://www.cs.virginia.edu/c++programdesign/slides/pdf/bw01.pdf
https://www.tutorialspoint.com/computer_organization/index.asp
https://sites.google.com/site/uopcog/

Seminar Topics:
1) Pentium IV Architecture
2) SIMD
3) High performance Architecture
4) Parallel Computer Architecture

CSE II Year I - Semester