International Journal of Electronics

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DC and RF analysis of Vertical 3D p-type Silicon

Nanotube FET for low power applications

Josephine Anucia. A, Gracia. D & Jackuline Moni D

To cite this article: Josephine Anucia. A, Gracia. D & Jackuline Moni D (2021): DC and RF
analysis of Vertical 3D p-type Silicon Nanotube FET for low power applications, International
Journal of Electronics, DOI: 10.1080/00207217.2021.1941288

To link to this article: https://doi.org/10.1080/00207217.2021.1941288

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Jun 2021.

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Publlisher: Tayllor & Franccis & Inform
ma UK Limiited, trading
g as Taylor & Francis
Grouup

Jourrnal: International Jou

urnal of Elecctronics

DOII: 10.1080/000207217.20
021.19412888
DC and RF analysis
a of Verticall 3D p-typ
pe Silicon
n Nanotub
be FET fo
or
low power ap
pplication
ns.

Joseephine Anuucia. A, Gracia.

G D, Jackuline Moni D.

Depaartment of Electronics
E and Commuunication Engineering,
E , Karunya IInstitute of
Techhnology andd Sciences, Coimbatore
C e-641114, Tamil
T Nadu, India.
Correesponding auuthor: Dr. D.
D Jackulinee Moni,
Proffessor, ECE D
Department,
Karu
unya Institutte of Technollogy and Sciences,
Coim
mbatore-641 114, Tamil Nadu,
N India.
email: monni@karunya.eedu
Josephine Anucia. A did her B.Tech in Eleectronics andd Communication
ng and M.Tecch in VLSI Design
Engineerin D at Kaarunya Instituute of Techn
nology
and Sciences, coimbaatore. She iss currently pursuing thhe PhD degrree at
Karunya Institute of T
Technology and Sciencees, Coimbato
tore. Her ressearch
interests in
nclude semiiconductor device
d modeelling and L
Low Power VLSI
Design.
Gracia. D did her B.T
Tech in Electrronics and Communicati
C ion Engineerring at
Karunya In
nstitute of T
Technology and
a Sciencess, Coimbatorre. She comp
pleted
her M.E in
n VLSI Dessign at SSN college of Engineeringg, Chennai. She
S is
currently pursuing
p her PhD degreee in Nano Devices at Kaarunya Institute of
Technolog
gy and Sciiences, Coiimbatore. Her
H researchh area inccludes
semicondu
uctor device modelling, Low
L Power VLSI
V Designn and Testin
ng and
Verificatio
on.

ni did her B.T

Dr. D. Jacckuline Mon Tech in Electronics Engin
ineering at Madras
M
Institute of
o Technologgy, Anna University,
U Chennai
C and M.E in Ap
pplied
Electronicss from Govvernment Co
ollege of Technology,
T Coimbatoree. She
completed her PhD deegree in Info
ormation and
d Communiccation Engineeering
na Universityy, Chennai. She
under Ann S is curren
ntly workingg as a Professsor in
 ECE department, Karunya Institute of Technology & Sciences, Coimbatore,
India. She has 32 years of teaching and research experience. She has
published more than 80 papers in National and International Journals and
Conferences. Her research area includes semiconductor device modeling,
Low Power VLSI Design, Analog VLSI and Embedded Systems design.

DC and RF analysis of Vertical 3D p-type Silicon Nanotube FET for

low power applications.
A vertical p-type 3D Silicon nanotube field effect transistor (p-type Si-NTFET) is
designed and simulated by using the tool Sentaurus Technology computer-aided
design (TCAD). To improve the performance with reduced short channel effects,
Si-NTFET device is created with inner and outer gate structures. The
performance of the proposed device is analysed in terms of outer gate length. The
Vertical 3D p-type Si-NTFET gives an on state current (ION) of -2.084×10-3
A/µm, off state current of (IOFF) of -2.457×10-12A/µm and subthreshold swing of
the p-type Si-NTFET device is 53 mV/dec at VDS of -0.3V. The obtained ION/IOFF
ratio of the device is 109. The capacitances (CGD, CGG) and the transconductance
(gm) and cut off frequency (ft) of the device are also analysed. The simulated p-
type Si-NTFET device has proved that the device is suitable for low power
applications.

Keywords: Silicon Nanotube FET; Silicon Nanowire FET; subthreshold swing;

transconductance; miller capacitance; cut off frequency.

1. Introduction
The conventional MOSFETs suffer by the short channel effects when it is scaled
down to nanometer regime. Reliability and drivability of the device are affected by the
short channel effects (SCEs) (Taur, 2002). To overcome the problems in the
conventional MOSFETs, the 3D devices with multi-gates have been created (Dixit et
al., 2005). Multigate devices, Gate-all-around (GAA) devices, underlap FET, FinFETs,
Tunnel FETs, Nanowires, and Nanotubes (NT) are created to meet the low power ITRS
requirements. (Kranti & Armstrong, 2007a, 2007b; Nandi et al., 2013; Wang et al.,
2007),(Buddharaju et al., 2007).Double Surrounding Gate (DSG) FET provides more
gate control and also enhances the reliability of the device compared with the single and
double gate FETs (Goel et al., 2019, 2020b, 2020a; Rewari et al., 2019b, 2019a).
Shallow Extension with dual metal gate structure reduces the Gate-Induced Drain
Leakage (GIDL) (Goel et al., 2020b). Shallow extension with dual material gate not
only minimizes the leakage current but also enhances the noise margin (Goel et
al., 2019). High-K spacer with junctionless dual metal gate reduces the poly
depletion effect, channel resistance and improves the ION/IOFF ratio (Goel et al.,
2020a).
Nanowire is providing good immunity to SCEs effect (Hamedi-Hagh & Bindal,
2008; Zhang et al., 2018). Compared with planar DG FETs, silicon nanowire FET (Si-
NWFET) provides low leakage current and high capacitive-coupling ratio(Lim et al.,
2017).The GAA Si-NWFET has risen as a suitable device structure for scaled down
device, due to its high packaging density and good control over the gate(Lu et al., 2008;
Sharma et al., 2016). However GAA Si-NTFET suffers due to its steep series resistance
which occurs because of the abrupt junction development between the heavily doped
source/drain region and lightly doped silicon body (Liu et al., 2013; Shih et al.,
2011).An array of nanowires is required to attain the reliability, hence the area gets
increased (Sahay & Kumar, 2017).An array of nanowires will improve the drive current
but increase the leakage current. In order to overcome this problem, nanotubes have
been created by Tekleab et.al(Tekleab et al., 2012; Tekleab, 2014). A few researchers
have inspected the silicon nanotube FET (Si-NTFET), junctionless silicon nanotube
FET (JL-Si-NTFET) and stated that Si-NTFET surpasses the Si-NWFET in terms of
drive current and transconductance. Through an analytical modelling, the L-BTBT
impact on DM-JAM-TFET (Dual-Metal Junctionless Accumulation nanotube
FET) is investigated and linearity of the device is also analysed. It shows DM-
JAM-TFET produces low leakage and used for high linearity RFIC applications.
The junctionless FET decreases the problems caused by the junction resistance
(Goel et al., 2020c; Rewari et al., 2016).The short channel effects in Si-NTFETs are
minimal when compared with the NWFET. Si-NTFET achieves the same output current
with very less area occupied (Ambika & Srinivasan, 2016; Fahad et al., 2011; Fahad &
Hussain, 2012, 2013; Hur et al., 2016)(Apoorva et al., 2020) (Jayakumar & Srinivasan,
2017).At very low voltage (VDS), nanotubes attain high drive current and
transconductance. The core gate drives the appreciable increment in the gate
capacitance of Si-NTFETs; the architecture of the Si-NTFET enhances the drive current
compared with Si-NWFETs(Sahay & Kumar, 2017). Si-NTFET hollow cylindrical
shape contributes eventual electrostatic controllability to the gates. The Si-NTFET has
attracted attention due to its structure, high drive current, suitability for scaled down
devices and helps to overcome the problem raised in nanowires (Tekleab, 2014). The
use of inner/outer core-shell gates of Si-NTFETs leads to higher drive current and
excluding the need of array requirement. In Si-NTFET architecture the outer gate act as
a NWFET while the inner gate operate as an additional gate which helps to enhance the
charge control over the channel. This exhibits notable charge control benefitting scaling
roadmap to extend beyond GAA(Singh, Chaudhury, et al., 2019; Singh, Pandey, et al.,
2019).
In this work, 3D vertical p-type Si-NTFET has been proposed based on the
structure described in (Tekleab, 2014). There is a limited reported data available on a p-
type NTFET compared with the n-type NTFET. The input and output characteristics,
capacitance and transconductance analysis of the simulated device are discussed. In
Section 2 the structure of device and parameters used for the simulation are discussed.
In section 3 p-type Si-NTFET device with different outer gate length, output
characteristics, transconductance, cut off frequency and capacitance analysis are
investigated. Section 4 gives conclusion followed by reference.

2. P-type Vertical Silicon Nanotube Structure

The created 3D P-type Vertical Nanotube FET device and its cross sectional
view is shown in Figure.1 (a) and 1(b)(Tekleab, 2014).

(a) (b)
Figure.1 (a) Vertical p-type Si-NTFET (b) Cross - sectional view of p-type Si-NTFET

A Sentaurus TCAD tool was used to simulate and analyse the device. For
creating the 3D vertical silicon nanotube FET device with the gate, source and drain
contacts and doping and meshing generation, Sentaurus Structure Editor was used. For
DC aand RF anaalysis of creeated p-typee Si-NTFET
T device, th
he Sentauruus Device Editor
E
was uused. The work
w functio
on of inner and outer gate
g is 4.8eV
V. The innerr and outer gates
of the device plaay an imporrtant role inn reducing th
he SCEs. Th
his structuree design helps to
overccome the SCEs probleem in the sccaled down devices. Th
he source aand drain reegions
are hheavily dopeed. The exteension of thhe source an
nd drain reg
gions are heeavily doped
d like
sourcce/drain reggion in order to minim
mize the seeries resistan
nce. The chhannel is liightly
dopeed to reducee the dopantt fluctuationn. The sourcce and drain
n extensionns are surrou
unded
by thhe spacer which
w is esseential for veertical nano
otube structu
ures, so Si3N 4 is used as
a the
spaceer material((Chen & Tan, 2014; F
Fahad et al., 2011; Krranti & Arm
mstrong, 20
007a).
Figurre 2 showss the suggeested devicce fabricatio
on process flow of S i-NTFET(S
Singh,
Panddey, et al., 2019).
2

 SOI WWafer
 Mesa F Formation
 Sacrificcial sidewall
 NT outter side formaation
 Outer GGate Oxide
 Outer GGate
 Spacerr Deposition
 Sacrificcial layer deposition
 Selectiive etching of spacer
 Epitaxiial growth of insitu
doped silicon
 Trenchh creation & inner
i gate
stack ddeposition
 Metal contacts, patterning
&depoosition

Diellectric

Sacrrificial Oxide
Burried Oxide
Siliccon Layer
Hanndle/Back Silicon

Siliccon-di-Oxide
 Figure.2 Fabrication process flow of a Si-NTFET(Singh, Pandey, et al., 2019)

The other parameters used for this device simulation is listed in Table 1.To improve the
reliability and drivability of the devices, models such as field and doping-dependent
mobility degradations, Shockley-Read-Hall (SRH), effective intrinsic density and
Hurkx model are used.

Table1.Parameters used for the device simulation

Parameter Value
Inner Gate Length (LIG) 130 nm
Outer Gate Length (LOG) (60 nm -14 nm)
Inner Gate Diameter (DIG) 20 nm
Outer Gate Diameter (DOG) 32 nm
Source/Drain Length (LS /LD) 15 nm
Source/Drain Extension Length (LSxtn /LDxtn) 33 nm
Oxide Thickness (TOX) 0.5 nm
Doping Concentration in Source/Drain Region 2×1020cm-3 (P+)
Doping Concentration in Source/Drain Extension 1×1020cm-3 (P+)

3. Results and Discussions

The investigation of outer gate length has been performed for the p-type Si-
NTFET and the outer gate length is scaled down from 60 nm to 14 nm their transfer
characteristic is shown in Figure 3. The outer gate length of the p-type Si-NTFET
device is varied from 60nm down to 14nm and the inner gate length is kept as 130nm.
For reduced gate length the device drivability is improving. It has been noticed that the
efficiency of drive current ratio is increasing as gate length is reducing(Yu & Cho,
2016). The reason is drain velocity increases at the drain side. High ION/IOFF is achieved
for outer gate length 14nm under VGS= -1.5V, VDS= -0.3V. The channel is lightly
doped; the decrease in the barrier height becomes significant as LG gets shorter because
of the higher growth of depletion region into source to channel interface. As the outer
gate length is scaling down subthreshold swing also reduced well below 80mV/dec. The
obtained ION and IOFF value for 14nm p-type Si-NTFET is-2.084×10-3 A/µm and
-2.457×10-12 A/µm respectively. Our simulated results are compared with the
experimental work reported in the paper(Fahad & Hussain, 2012) (Table 2). Comparing
the ION/IOFF ratio, the vertical p-type Si-NTFET (Our work) achieves ~103 times higher
than ION/IOFF ratio of the device reported in the paper(Fahad & Hussain, 2012).

Table 2. Comparison table of our work with the similar reported work

Ref ION/IOFF ION(A) VDS SS (mV/dec) LG

This work 1×109 2. 084×10-3 -0.3V 53 14nm
(Fahad & Hussain, 2012) 1×106 2.5×10-3 -1.0V 77 20nm

Figure 3.Transfer characteristics of p-type Si-NTFET for different outer gate

length (LG)

The output characteristics (ID-VDS) curves with different gate voltages are
plotted in Figure 4. The ID (drain current) increases as the drain to source voltage (VDS)
sweeps from 0V to -0.3V.For low voltage the barrier width is wider so low ION value is
obtained at linear regime. As gate voltage (VGS) increases from -1.1 to -1.5 V, the
barrier width is reduced so drive current is increasing gradually at saturation regime.
 Figure 4. ID-VDS characteristics of p-type Si-NTFET for gate voltage (VGS)varies
from -1.1V to -1.5V
The capacitance and voltage charactersticssuch as gate capacitance (CGG), gate
to drain capacitance (CGD) of the simulated p-type Si-NTFET are shown in Figure 5&
Figure 6respectively. The gate capacitance is extorted from the device and analysis has
been made for different drain voltage (VDS) which is varied from -0.5V to 0V. The gate
capacitance decreases slightly as gate voltage (VGS) is varied from -1.5V to 0V. This is
due to a limit in carrier density through the Schottky contacts. The gate-drain
capacitance (i.e. miller capacitance) is reverse transfer capacitance. The miller
capacitance effect removes the gate charge when drain voltage fall rapidly. This will
affect the switching of the device. Gate to drain capacitance and gate to source
capacitance contributes partly of the overall gate charge in linear region. During the
saturation region, miller capacitance becomes insignificant because of high potential
barrier between channel and drain region. As the gate voltage increases from -1.5 V to
0V, CGD reduces gradually (Mookerjea et al., 2009).
 Figure 5. C-V (CGG) characteristics as a function of VGS for VDS

Figure 6. C-V (CGD) characteristics as a function of VGS for different VDS

 Figure.7. Transconductance of p-type Silicon Nanotube FET for different outer gate
length (LG)

Figure.8. Cut off frequency (ft) of p-type Silicon Nanotube FET for different outer gate
length (LG)
 Figure7illustrates transconductance characteristics as a function gate voltage for
varies outer gate length at VDS=-0.3V. The transconductance is not a constant; it is the
ௗூವ
derivative of which depends linearly on VGS. The transconductance quantifies the
ௗ௏ಸೄ

drain current variation with the VGS variation while keeping the VDS constant. By
increase the control over gate i.e. increasing the gate voltage is enhancing the
transconductance. Maximum transconductance values are obtained between VGS=–0.95
V and VGS=–1.3 V and it describes high potential towards low power and high speed
applications. A figure 8 shows the cut off frequency curves as a function gate voltage
for varies outer gate length. Cut off frequency (ft) is directly proportional to
transconductance so as transconductance increases ft also increases. The high
transconductance of the (14nm outer gate length) p-type Si-NTFET device facilitates it
to attain the high cut off frequency. Cut off frequency can be expressed as (1)

gm
ft = (1)
2πC GG

4. Conclusion
In this paper, DC and RF performances of the 3D vertical p-type Si-NTFET
device are discussed. To improve the drivability of the device the analaysis
areperformed in p-type Si-NTFET with different outer gate length. The output
characterstics of the simulated device is studied. The gate capacitance as a function of
gate voltage has been studied.The miller capacitance (gate to drain capacitance) effect is
reduced. For the simulated p-type device the transconductance and cut off frequency
analysis have been done for different outer gate length.
Acknowledgement
We would like to thank the management and higher authorities of Karunya
Institute of Technology and Sciences for providing us very good VLSI lab facilities to
carry out this research work.
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