Microelectronics Journal 104 (2020) 104893

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Nanosheet FET: A new subthreshold current model caused by

interface-trapped-charge and its application for evaluation of subthreshold
logic gate
Te-kuang Chiang
Advanced Device Simulation Laboratory (ADSL), National University of Kaohsiung, Taiwan

A R T I C L E I N F O A B S T R A C T

Index Terms: Based on the quasi-3D potential approach, quasi-3D scaling theory, drift-diffusion model, and equivalent flat-band
Quasi-3D potential approach shift, a new subthreshold current model caused by the interface-trapped-charge is developed for the nanosheet
Quasi-3D scaling theory FET. With the subthreshold current Isub, the noise margin (NM) of the subthreshold logic gate composed of
Equivalent flat-band shift
nanosheet FET is thoroughly evaluated. It is found that the positive interface-trapped-charge can degrade the high
Subthreshold current
Subthreshold logic gate
noise margin (NMH) due to its increased/decreased subthreshold current of N-FET/P-FET. On the contrary, the
Scaling factor negative interface-trapped-charge can decrease/increase subthreshold current of N-FET/P-FET, which hence
Noise margin. deteriorates the low noise margin (NML). Both degradation of the subthreshold current and NM (i.e., ΔIsub and
ΔNM) caused by short-channel effects (SCEs) can be well-controlled by the properly selected scaling factor of α.
With the minimum scaling factor αmin that allows for the minimum noise margin degradation (ΔNM), the min-
imum channel length Lmin for the nanosheet FET can be obtained as it is readily applied for the subthreshold logic
gate.

1. Introduction the smaller scaling length to alleviate SCEs more effectively, the
QG-MOSFET provides more conducting channels than the TG-MOSFET in
AS the semiconductor node is down below 16 nm, the new device enhancing the driving capability for the high performance of ULSI. In
structure and materials are needed to continue the scaling performance. addition to being superior to TG-MOSFET, the scaling length of
Instead of highly doped poly-silicon-gate, the metal gate [1,2] is pro- QG-MOSFET can be smaller than it of the nanowire cylindrical
posed to improve the device performance due to eliminating the surrounding-gate MOSFET (CSRG-MOSFET) as both transistors are with
poly-gate depletion effects that induce the additional depletion capacitor the same cross sectional area of the channel. This implies that with the
and degrade the device switching speed. Meanwhile, the high-K insulator same current driving capability, the QG-MOSFET exhibits the better
makes the equivalent oxide thickness (EOT) much larger than the immunity to SCEs than its counterpart of the nanowire CSRG-MOSFET. It
thickness of silicon dioxide (SiO2), which hence effectively reduces gate is known that the subthreshold logic gate can be used to reduce the power
leakage current caused by the tunneling effects. The multiple-gate (MG) consumption as the tight power budget is the main concern of ULSI [5,6].
MOSFET outweighs the single-gate (SG) MOSFET in suppressing severe To utilize the QG-MOSFET in the subthreshold logic gate, there is a need
short-channel effects (SCEs) induced by the further scaling scheme to establish a feasibly analytical device model that can be applied for the
required for the high packing density of ULSI. Up to now, one of the MG circuit application. Several previous studies were proposed to model the
MOSFETs named for FinFET (i.e., triple-gate MOSFET: TG-MOSFET) has MG MOSFETs such as double-gate (DG) MOSTEFT [7], TG-MOSFET [8],
been utilized for the 5-nm technology in fabricating the IC attaining the and QG-MOSFET [9], but no papers have been proposed to model the
high performance and low-power consumption [3]. On the other hand, subthreshold current for the QG-MOSFET with the
the nanosheet FET (i.e., quadruple-gate MOSFET: QG-MOSFET) has been interface-trapped-charge (ITC). It is well-known that the
theoretically proposed as another alternate to TG-MOSFET when the interface-trapped-charge (ITC) may result in the threshold voltage shift
semiconductor node is further scaled down [4]. The QG-MOSFET is (i.e., ΔVth), which further degrades the device performance. In addition
better than the TG-MOSFET in suppressing SCEs because it provides a to degrading the device performance (i.e., inducing ΔVTH and ΔIsub), the
shorter scaling length of λ than the TG-MOSFET. In addition to offering interface-trapped-charge (ITC) can also deteriorate the circuit

E-mail address: tkchiang@nuk.edu.tw.

https://doi.org/10.1016/j.mejo.2020.104893
Received 28 May 2020; Received in revised form 9 August 2020; Accepted 27 August 2020
Available online 10 September 2020
0026-2692/© 2020 Elsevier Ltd. All rights reserved.
T.-k. Chiang Microelectronics Journal 104 (2020) 104893

performance like degrading the noise margin NM (i.e., inducing ΔNM), obtained as
which is not investigated by now. In this work, with both ITC effects
(ITCs) and SCEs included, both ΔIsub and ΔNM for the nanosheet FET are x2   
Φðx; y; zÞ ¼ ΦC ðzÞ þ Vgs  Vfb  ΦC ðzÞ
thoroughly investigated on the basis of the successfully developed sub- 2λ21
threshold current model. (3)
y2   
þ 2 Vgs  Vfb  ΦC ðzÞ
2λ2
2. Model derivation
where ΦC(z) is the central potential along with the channel direction.
2.1. Quasi-3D potential and scaling equation (More details regarding the derivation of (3) can be found in the ap-
pendix section). By substituting (3) into (1) and setting x ¼ 0 and y ¼ 0,
Fig. 1 demonstrates the schematic of the nanosheet FET including N- the following quasi-3D scaling equation for the bulk conduction mode
type and P-type transistors. In our case, only the N-type nanosheet FET is (BCM) of QG-MOSFET can be obtained.
accounted for in developing the model. The analytical model of P-type
8 2
nanosheet FET can also be secured by changing the polarity of the doping >
> d ΦC ðzÞ ΦC ðzÞ  φCL
>
< þ ¼0
type in source, channel, and drain of the N-type device. In the sub- dz2 λ2
threshold regime, the potential of Φ(x,y,z) should satisfy the following 3- (4)
>
> qN λ2
D Poisson’s equation: >
: φCL ¼ Vgs  Vfb  a
εsi
2 2 2
∂ Φðx; y; zÞ ∂ Φðx; y; zÞ ∂ Φðx; y; zÞ qNa
þ þ ¼ (1a) whereφCL is the long-channel central potential, λis the scaling length, and
∂x2 ∂y2 z2 εsi Vfb is the flat-band voltage caused by the interface-trapped-charge
inducing the equivalent oxide charge density that brings about the flat-
where Na is the channel doping density and εsi is the dielectric constant of
band voltage shift and caused by the work-function difference between
the silicon. According to the quasi-3D potential approach [10], the po-
gate material and silicon. The Vfb can be defined as
tential for the nanosheet FET can be assumed as
ΦM  ΦSI qNf
Φðx; y; zÞ¼ C1 ðzÞ þ C2 ðzÞx þ C3 ðzÞy þ C4 ðzÞx2 þ C5 ðzÞy2 (1b) Vfb ¼  (5)
q Cox
The boundary conditions to solve for (1b) can be given below:
where ΦM and ΦSI are the work-functions for gate and silicon, respec-
∂Φðx; y; zÞ tively. Nf is the interface-trapped-charge density per unit area. The
ðAÞ: Φðx ¼ 0; y ¼ 0Þ ¼ C1 ðzÞ; ðBÞ: jy¼0 ¼ 0
∂y scaling length of λin (4) can be expressed as
∂Φðx; y; zÞ
ðCÞ: jx¼0 ¼ 0; 1 1 1
∂x ¼ þ (6a)

 λ2 λ21 λ22
W
Vgs  Vfb  Φ x ¼  ; y ¼ 0; z (2)
∂Φðx; y ¼ 0; zÞ εox 2 whereλ1 and λ2 are the scaling lengths for double-gate MOSFET (DG-
ðDÞ: jx¼W ¼ 
∂x 2 εsi tox MOSFET) working in the x-z plane and y-z plane, respectively. They are


H expressed as follows:
Vgs  Vfb  Φ x ¼ 0; y ¼  ; z
∂Φðx ¼ 0; y; zÞ εox 2
ðEÞ: jy¼¼H ¼  81 8 Cox
∂y 2 εsi tox >
> 2 ¼ 2
> λ
> 1 H 4C þ Cox
>
>
H
Boundary conditions of (B) and (C) illustrate the potential symmetry >
<
of the device in y-z and x-z plane, respectively. Boundary conditions of 1 8 Cox
2 ¼
(6b)
>
> λ W 2
4C þ Cox
(D) and (E) demonstrate the continuity of electrical flux at the interface >
> 2 W
>
>
between silicon and gate oxide at x-z and y-z planes, respectively. By >
: εox εsi εsi
Cox ¼ ; CH ¼ ; CW ¼
substituting (1b) into (2), the quasi-3D potential for QG-MOSFET can be tox H W

where Cox, CW, and CH are the capacitance per unit area in the gate oxide,
channel width, and channel height, respectively.

2.2. Minimum central channel potential

Based on 1-D ordinary differential equation, the central potential in

the quasi-3D scaling equation of (4) can be obtained as
z z
ΦC ðzÞ ¼ Ae λ þ Beλ þ φCL (7)

With the boundary conditions of ΦC(z ¼ 0) ¼ Vbi, ΦC(z ¼ Lg) ¼ Vbi þ Vds,
where Vbi is the junction potential between source/drain and channel
and Vds is the drain voltage, the coefficients of A and B in (7) can be
obtained as
 Lg 
ðVbi  φCL Þ e λ  1  Vds
A¼
 ¼ α1 Vgs þ β1 (8a)
2Sinh λg
L
Fig. 1. Schematic of the typical nanosheet FET(i.e., quadruple-gate MOSFET.
Fig. (1a) is for N-type QG-MOSFET and Fig. (1b) is for P-type QG-MOSFET,
respectively. Both of the QG-MOSFETs are damaged by the positive/negative
interface-trapped-charge (ITC). The origin-point of 3-D coordinate system is
located at the center of the cuboid as shown in Fig. (1a)

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T.-k. Chiang Microelectronics Journal 104 (2020) 104893

0 1
QG-MOSFET can be obtained as
Vds  ðVbi  φCL Þ@e λ  1A
g L

Z y¼W2 Z x¼H2
dΦn ðzÞ
B¼
 ¼ α2 Vgs þ β2 (8b) Isub ðzÞ ¼ 2 2 qμn nm ðx; y; zÞ dxdy (11)
0 0 dz
2Sinh λg
L

:where Φn(z) is the quasi-Fermi potential and the carrier density distri-
with bution in the quasi-3D minimum central potential can be expressed as

8 

 n2i qΦmin ðx;yÞΦ

 Lg qNa λ2 n ðzÞ
nm ðx; y; zÞ ¼
Lg
>
>  eλ 1 Vbi þ Vfb þ 1  e λ þ Vds e kT (12)
>
> εi Na
>
> α1 ¼
; β1 ¼ 

>
>
>
> 2Sinh
Lg
2Sinh
Lg From (12) and (11), we may have
>
< λ λ


 (8c) Z Z Z y¼W2 Z x¼H2
>
>  qNa λ2
Lg Vds
>
>
L g
λ  1  þ þ
Lg
λ  1 Isub ðzÞdz ¼ 4 qμn nm ðx; y; zÞdΦn ðzÞdxdy (13)
>
> e V V V e
>
>
ds bi fb
ε 0 0 0 0
>
> α ¼
; β2 ¼
si
> 2
: Lg Lg By substituting (12) into (13), the subthreshold current for the QG-
2Sinh 2Sinh
λ λ MOSFET with the interface-trapped-charge (ITC) can be obtained as
Because the arithmetic average is not smaller than the geometrical
 


πμn n2i kT Vds ΦCmin H W
average for A and B, the minimum central potential in (7) can be ob- Isub ¼ 1  e VT e VT erf a erf b (14)
abNA Lg 2 2
tained as
pffiffiffiffiffiffi with
ΦCmin ðz ¼ zmin Þ ¼ 2 AB þ φCL (9a)
8 rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
>
> 1 ΦCmin  Vgs þ Vfb
with <a ¼ λ
>
2VT
1

 rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi (15)
λ A >
> 1 ΦCmin  Vgs þ Vfb
zmin ¼ ln (9b) >
:b ¼
2 B λ2 2VT

where Zmin is the location of the minimum central potential along with where erf(aH/2) and erf(bW/2) are the error functions and VT is the
the channel direction. thermal voltage. The degradation of subthreshold current caused by SCEs
for QG-MOSFET can be defined as
2.3. Threshold voltage ΔIsub ¼ Isub ðΦCmin Þ  Isub ðφCL Þ (16)

By setting ΦCmin ¼ 2ΦB, (ΦB ¼ KT/q  ln(NA/ni): bulk potential), the

threshold voltage for QG-MOSFET can be obtained as 2.5. Noise margin
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
B1  B21  4A1 C1 To derive NM model for the inverter shown in Fig. 2, the minimum
VTH ¼ (9c) central potential ΦCmin in (14) should be transformed into the expression
2A1
of gate voltage Vgs. In Fig. 3 that shows the relationship between the
with minimum central potential and gate voltage, due to the straight line with
8 the slope of η, the linear function of ΦCmin dependent of Vgs can be
>
> A1 ¼ ð1  4α1 α2 Þ expressed as
>
>
>
>
< B1 ¼ 2θ þ 4ðβ1 α2 þ α1 β2 Þ
>
   1
C1 ¼ θ2  4β1 β2 (9d) ΦCmin Vgs ¼ Vgs  VTH þ 2ΦB (17)
>
> η
>
>
>
> qN λ2
>
: θ ¼ Vfb þ a þ 2ΦB
εsi
From (8a), (8b), (8c), and (9a), the slope of the minimum central
potential with respect to the gate voltage (i.e., the inverse of subthreshold
slope) can be obtained as
   
dΦCmin α2 α1 Vgs þ β1 þ α1 α2 Vgs þ β2
¼ 1 þ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
   (9e)
dVgs α V þβ α V þβ2 gs 2 1 gs 1

According to (3), the quasi-3D minimum central channel potential

that varies with x and y can be further expressed as

x2   
Φmin ðx; yÞ ¼ Φðx; y; zmin Þ ¼ ΦCmin þ Vgs  Vfb  ΦCmin
2λ21
(10)
y2   
þ 2 Vgs  Vfb  ΦCmin
2λ2

2.4. Subthreshold current

Fig. 2. (a): Schematic of the inverter composed by P-type and N-type nanosheet
According to the drift-diffusion model, the subthreshold current for FETs (QG-MOSFETs), respectively. (b): Circuit symbol of the inverter.

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T.-k. Chiang Microelectronics Journal 104 (2020) 104893

8

> Vdd ηNM VT ηNM VT βp 2
>
> NM ¼   ln þ ln
>
>
H
2 2 2 βn ηNM
>
>

>
< Vdd ηNM VT ηNM VT βn 2
NML ¼   ln þ ln 21a-21c
>
> 2 2 2 βp ηNM
>
>

>
>
>
> 1 1 1 1
: ¼ þ
ηNM 2 ηn ηp

The NM for the inverter composed of QG-MOSFET can be selected as the

small value between NMH and NML, i.e.,

NM ¼ smallfNMH ; NML g (22)

Usually, NML is smaller than NMH because βn is larger than βp for the
mobility of electron that is greater than it of hole. The degradation of NM
caused by SCEs can be defined as

ΔNM ¼ NMðΦCmin Þ  NMðφCL Þ (23)

Fig. 3. Linear relationship between gate voltage and minimum channel poten- 3. RESULTS AND DISCUSSIONS
tial (i.e., ΦCmin), which illustrates ΦCmin can be expressed as (17). The points of
A, B, and C indicate the threshold voltage for the device with positive interface-
The 3-D device simulator “DESSIS” [12] is used to validate the pro-
trapped-charge, without interface-trapped-charge and with negative interface-
posed model. Fig. (4a) and (4b) plot Isub versus the gate voltage for
trapped-charge, respectively.
N-type and P-type transistors with/without interface-trapped-charge
(ITC). Due to the flat-band voltage shift caused by ITC (see Eq. (5)),
where η is the subthreshold slope and can be expressed as
Fig. (4a) shows that the positive/negative ITC can increase/decrease the

1 Isub for N-type device. As opposed to Fig. (4a), Fig. (4b) reveals that the
1 dΦCmin
¼ (18) positive/negative ITC can decrease/increase the Isub for P-type transistor.
η dVgs

and 2ΦB is the criterion for the QG-MOSFET to get into the strong
inversion as Vgs reaches the threshold voltage of VTH. Both of the equa-
tions in (17) and (18) can also be applied for P-MOSFET just by changing
the polarity of the parameters. (i.e., ΦCmin→-ΦCmin, ΦB→-ΦB. VTH→-VTH).
From (17), (18) and (14), the subthreshold current for QG-MOSFET can
be rewritten as
Vgs VTH Vgs
Isub ¼ Io e ηVT ¼ βeηVT (19)

with
8



>
> πμ n2 kT Vds H W 2ΦB
>
< Io ¼ n i 1  e VT erf a erf b e VT
abNA Lg 2 2 (20)
>
>
>
: β ¼ I eVηVTH
T
o

where Io is the initial subthreshold current at the gate voltage

equivalent to the threshold voltage and β is the transistor strength. The
device parameters for N-type device can be applied for P-type device just
by changing the polarity of the device parameters. Table 1 lists the key
parameters such as Io, β,VTH and η that are used to simulate the noise
margin NM. According to our previous paper [11], the high noise margin
(i.e., NMH) and low noise margin (i.e., NML) for the inverter composed of
QG-MOSFETs can be expressed as shown in (21), where Vdd is the supply
voltage and both βn and βp are the transistor strength for N-type and
P-type transistors, respectively.

Table 1
The parameters of VTH, Io, β, and η are used in simulating the inverter.
QG-MOSFET VTH(V) Io(A) β(А) η
N-type 0.389 1.15  107 1.02  1013 1.078
P-type 0.393 5.17  108 4.51  1014 1.080

Device parameters used in the simulation: (1): H–

– W¼tsi ¼ 10 nm, tox ¼ 1 nm, Lg Fig. 4. a: Isub versus the gate voltage for N-type QG-MOSFET with/without
¼ 30 nm (2): N-type: Na ¼ 1017cm3, Nd ¼ 1020cm3 (3): P-type: Nd ¼ 1017cm3, interface-trapped-charge. b: Isub versus the gate voltage for N-type QG-MOSFET
Na ¼ 1020cm3. with/without interface-trapped-charge.

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T.-k. Chiang Microelectronics Journal 104 (2020) 104893

Fig. 6. a: Isub versus the oxide thickness for P-type QG-MOSFET with/without
Fig. 5. a: Isub versus the oxide thickness for N-type QG-MOSFET with/without interface-trapped-charge. b: Isub versus the oxide thickness for P-type QG-
interface-trapped-charge. b: Isub versus the silicon thickness for N-type QG- MOSFET with/without interface-trapped-charge.
MOSFET with/without interface-trapped-charge.

Fig. (5a) plots Isub versus the oxide thickness tox for the N-type transistor Table 2
with/without ITC. Due to the increased tox, the enhanced short-channel Both SCEs and ITCEs can be affected by the increased tox and tsi for N-type/P-
effects (SCEs) and lessened interface-trapped-charge effects (ITCEs) can type QG-MOSFETs.
increase/decrease Isub. As the lessened ITCEs are larger than the
enhanced SCEs, the Isub will be decreased when the tox is further
increased, which is shown in the green line of Fig. (5a). Fig. (5b) plots Isub
versus the silicon thickness tsi for the N-type transistor with/without ITC.
Irrespective of the device with/without ITC, Isub will be increased fol-
lowed by the increased tsi. This is because SCEs dominate Isub and in-
crease Isub. Fig. (6a) and (6b) plot Isub versus tox and tsi for P-type
transistor with/without ITC. Fig. (6a) and (6b) are very similar to
Fig. (5a) and (5b) except that the decreased Isub caused by the increased
tox for the positive ITC (see the blue line in Fig. (6b)). How the increased
tox and tsi affect ITCEs and SCEs can be shown in Table 2. Note that in 59.9 mV) is caused by both transistors having the same type of negative
Table 2, the increased tsi takes no effect on ITCEs and only enhances ITC. This is because βp/βn in (21a) will become the largest as both
SCEs. Fig. (7a) and (7b) plot the ΔIsub versus the scaling factor for transistors have the same type of negative ITC, which hence degrades the
N-type/P-type transistors. In comparison with the fresh P-type/N-type most NMH. It is worthy to point out that the NML/NMH for both tran-
transistors, the positive ITC can slow down/speed up the ΔIsub for sistors having the different types of ITC will be almost the same as it for
P-type/N-type transistors. On the contrary, the negative ITC can slow both transistors that are free from ITC. Since both of the transistors
down/speed up ΔIsub for N-type/P-type transistors. Fig. 8 plots high noise having the same type of ITC dominate NM behavior, in the following
margin/low noise margin (i.e., NMH/NML) versus the N-type/P-type figures of (9a), (9b), (9c), and (9d), only both transistors having the same
devices with/without ITC. It indicates that the most degradation of NML type of ITC are accounted for when they are compared with the fresh
(NML ¼ 48.79 mV) is induced by both transistors having the same type of transistors. Fig. (9a) and (9b) plots the ratio of transistor strength be-
positive ITC. This is because βn/βp in (21b) becomes the largest as both tween N-MOSFET and P-MOSFET versus tox and tsi for both devices with
transistors have the same type of positive ITC, which hence decreases the positive ITC, with negative ITC, and without ITC, respectively. It in-
most NML. In comparison to NML, the most degradation of NMH (NMH ¼ dicates that the ratio for both transistors with the positive ITC is the

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T.-k. Chiang Microelectronics Journal 104 (2020) 104893

Fig. 8. High noise margin/low noise margin (i.e., NMH/NML) versus N-type and
P-type transistors with/without positive/negative interface-trapped-charge
(ITC). (The simulated device parameters are ΦM ¼ 4.64eV, Lg ¼ 30 nm, tox ¼
1 nm, H– – W¼t ¼ 10 nm, N ¼ 1012cm2, V ¼ 0.25V, N ¼ 1017cm3 and N
si f dd a d
¼ 10 cm3 for P-type device, Nd ¼ 1017cm3and Na ¼ 1020cm3 for N-
20

type device.)

NM. Fig. 10 plots the noise margin degradation ΔNM caused by SCEs
versus the scaling factor for the devices with/without ITC. It reveals that
the scaling factor of Lg/2λ can control the NM degradation very well.
Although the transistors with the negative ITC can produce a smaller NM
Fig. 7. a: ΔIsub versus the scaling factor for N-type QG-MOSFET with/without than the fresh transistors (see Figures of (9c) and (9d)), they will be
interface-trapped-charge. b: ΔIsub versus the scaling factor for P-type QG- better than the fresh transistors in reducing a smaller ΔNM caused by
MOSFET with/without interface-trapped-charge. SCEs, which is shown in the green line of the figure. To ensure the
minimum ΔNM, the minimum scaling factor should be carefully selected.
largest among the three cases. The ratio for devices with the negative ITC In terms of the minimum scaling factor of 3 corresponding to the mini-
is next to it. The devices without ITC exhibit the smallest ratio among the mum noise margin degradation of ΔNM ¼ 5 mV for the fresh transistors,
three cases. Note that the larger ratio of transistor strength will bring Fig. 11 plots the minimum channel length versus oxide thickness for
about the more NM degradation followed by the increased tox and tsi, different silicon thicknesses. It indicates that when the QG-MOSFETs are
which will be shown in the following figures of (9c) and (9d). Figure (9c) readily applied for the subthreshold logic circuits, both of the thinner tsi
plots NM versus tox for both transistors with/without ITC. In positive ITC, and tox will be required to achieve the shorter Lmin that fits the minimum
the increased tox will increase βn and decrease βp, which hence increases scaling factor shown in the red line of the figure.
βn/βp in (21b) and decrease more NM as shown in the blue line of the
figure. In negative ITC, the increased tox will decrease βn and increase βp, 4. Conclusion
which hence enlarge βp/βn in (21a) and decrease more NM as shown in
green line of the figure. Without ITCEs, there will be a slight NM A new subthreshold current model for nanometer QG-MOSFET with
degradation for both fresh transistors as tox is increased. Also, due to the interface-trapped-charge has been developed based on quasi-3D po-
ITCEs, the damaged transistors will provide the smaller NM than the tential approach and quasi-3D scaling theory. With the subthreshold
fresh transistors as shown in the figure. Figure (9d) plots NM versus tsi for current, the noise margin for the subthreshold logic gate can be thor-
both transistors with/without ITC. In positive ITC, the increased tsi can oughly evaluated. In terms of the minimum scaling factor that allows for
enhance SCEs, decrease βn/βp and increase ηNМ in (21b), which hence the minimum noise margin degradation, the minimum channel length
degrades NML. Similarly, in negative ITC, the increased tsi can enhance Lmin can be obtained accordingly.
SCEs, decrease βp/βn and increase ηNМ in (21a), which hence degrades
NMH. How the increased tox and tsi affect the transistor strength for Declaration of competing interest
N-type/P-type transistors can be shown in Table 3. From the view-point
of optimum design, the maximum NM can be fulfilled when both tran- The authors declare that they have no known competing financial
sistor strengths are balanced (i.e., βn ¼ βp). Unfortunately, both of ITCES interests or personal relationships that could have appeared to influence
and SCEs can deteriorate transistor strength balance (TSB) and pull down the work reported in this paper.

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T.-k. Chiang Microelectronics Journal 104 (2020) 104893

Fig. 9. a: The ratio of transistor strength between P-MOSFET and N-MOSFET versus tox for the devices with/without ITC. b: the ratio of transistor strength between P-
MOSFET and N-MOSFET versus tsi for the devices with/without ITC. c: NM versus the oxide thickness for both transistors with/without ITC. d: NM versus the silicon
thickness for both transistors with/without ITC.

Table 3
The transistor strength can be affected by the increased tox and tsi for N-type/P-
type QG-MOSFETs.

Fig. 11. The minimum channel length versus the oxide thickness for different
silicon thicknesses in the criterion of α≧αmin ¼ 3 for fresh QG-MOSFET.

V. Appendix

The equation of (3) can be developed as follows:

By substituting (1b) into (2), one can obtain

C1 ðzÞ ¼ Φðx ¼ 0; y ¼ 0; zÞ ¼ ΦC ðzÞ (1A)

C2 ðzÞ ¼ C3 ðzÞ ¼ 0 (2A)

1 Cox  
C4 ðzÞ ¼ Vgs  Vfb  ΦS;xz ðzÞ (3A)
H 2 CH
Fig. 10. Noise margin degradation ΔNM versus the scaling factor for the device
with/without ITC.

7
T.-k. Chiang Microelectronics Journal 104 (2020) 104893

1 Cox  
C5 ðzÞ ¼ Vgs  Vfb  ΦS;yz ðzÞ (4A)
W 2 CW

whereΦC ðzÞis the central potential along with the channel direction and ΦS;xz ðzÞ and ΦS;xz ðzÞ are defined as


W
ΦS;yz ðzÞ ¼ Φ x ¼ 0; y ¼ ; z (5A)
2


H
ΦS;xz ðzÞ ¼ Φ x ¼ ; y ¼ 0; z (6A)
2
By substituting (5A) and (1A) into (1b), one can obtain
 
4CW ΦC ðzÞ þ Cox Vgs  Vfb
ΦS;yz ðzÞ ¼ (7A)
4CW þ Cox
Similarly, by substituting (6A) and (1A) into (1b), one can obtain
 
4CH ΦC ðzÞ þ Cox Vgs  Vfb
ΦS;xz ðzÞ ¼ (8A)
4CH þ Cox

where the capacitance per unit area in the x-z and y-z planes are defined as
εsi εsi
CW ¼ ; CH ¼ (9A)
W H
By substituting (8A) into (3A), C4(z) can be rewritten as


   
4Cox Vgs  Vfb  ΦC z
C4 z ¼ 2 (10A)
H 4CH þ Cox
Similarly, by substituting (7A) into (4A), C5(z) can be rewritten as


   
4Cox Vgs  Vfb  ΦC z
C5 z ¼ 2 (11A)
W 4CW þ Cox
By substituting both (10A) and (11A) into (1b), the quasi-3D potential of QG-MOSFET can be obtained as

x2   
Φðx; y; zÞ ¼ ΦC ðzÞ þ Vgs  Vfb  ΦC ðzÞ
2λ21
(12A)
y2   
þ 2 Vgs  Vfb  ΦC ðzÞ
2λ2

where λ1 and λ2 are defined as

81 8 Cox
>
> ¼
>
< λ21 H 2 4CH þ Cox
(13A)
>
> 1 8 Cox
>
: 2¼ 2
λ2 W 4CW þ Cox

Author statement

Based on the quasi-3D potential approach, quasi-3D scaling theory, drift-diffusion model, and equivalent flat-band shift, a new subthreshold current
model caused by the interface-trapped-charge is developed for the nanosheet FET With the subthreshold current Isub, the noise margin (NM) of the
subthreshold logic gate composed of nanosheet FET is thoroughly evaluated. It is found that the positive interface-trapped-charge can degrades the high
noise margin (NMH) due to its increased/decreased subthreshold current of N-FET/P-FET. On the contrary, the negative interface-trapped-charge can
decrease/increase subthreshold current of N-FET/P-FET, which hence deteriorates the low noise margin (NML). Both degradation of the subthreshold
current and NM (i.e., ΔIsub and ΔNM) caused by SCEs can be well-controlled by the properly selected scaling factor of α. With the minimum scaling
factor αmin that allows for the minimum ΔNM, the minimum channel length Lmin for the nanosheet FET can be obtained as it is readily applied for the
subthreshold logic gate.

8
T.-k. Chiang Microelectronics Journal 104 (2020) 104893

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