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Summary of Lec1

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25 views8 pages

Summary of Lec1

Uploaded by

ahmedabdelnasser1337
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Lec1

Monday, October 23, 2023 4:02 PM

(i) Control Unit (CU) and the Arithmetic and Logic Unit (ALU) constitute
the Central Processing Unit (CPU)
(ii) Data and instructions need to get into the system and results need to
get out
o Input/output (I/O module)
(iii) Temporary storage of code and results is needed
o Main memory (RAM)
(iv) Program Concept
o Hardwired systems are inflexible
o General purpose hardware can do different tasks, given correct
control signals
o Instead of re-wiring, supply a new set of control signals

A brief History of the Computers

Si is more preferred than Ge because it has the ability to deal with high volt

To help software manage hardware, you need Computer Architecture

Chapter one Page 1


Screen clipping taken: 10/23/2023 10:31 PM

The reasons why we need to design for performance

Chapter one Page 2


It's part of computer organization

The processor has no address

Computer Architecture give you three layers:


1. Instruction set - responsible of software instructions.
2. Microarchitecture - responsible of the implementations
happen in hardware.
3. System Design - schema (Don't care if it works or not)

Chapter one Page 3


Note:
In Registers we put
Note : Num of flip-flop (as flags) equal the capability
Multicore - is more than one processor Of the Register.
On one shape

Compatibility
Has two types -
1. If the hardware is old but has the ability to Note:
adapt with Cache : consists of [flip-flop] -
New software. serves as an intermediary between
2. If the software could run on multiple the CPU(near to it) and the main
hardware. (like openness in distributed memory (RAM) by efficiently storing
system ) frequently accessed data and
instructions

Note: Pipeline : try to maximize (not optimize)


Transistors : ‫ب ستق ل الداتا و ضعها ال‬ resource usage.
capacitor : ‫ ال ب تح م عمل ة ال‬refrech , ‫وتخ نه مؤقت للداتا‬

Processor introduce some functions - Fetch - Execute cycle


- (Fetch , Decode): 1. The CPU fetches the instructions one at a time
PC register - has the next instruction . from the main memory into the registers. One
IR register - has the current instruction. register is the program counter (pc). ‫ق مته مش ب تغ‬
- (execute): the result of the instruction . ‫ اﻻ لما حصل عمل ة‬execute.
2. The pc holds the memory address of the next
instruction to be fetched from main memory.
Note : 3. The CPU decodes the instruction.
Buffer more suitable than stack as it can 4. The CPU executes the instruction.
deal with the different speed in memory
5. Repeat until there are no more instructions .
and CPU.

Chapter one Page 4


DRAM is organized in banks, each of which contains matrices of cells. Each cell consists of an access
transistor and a storage capacitor. only one row can be buffered (opened) per bank and actively service
requests at a time, while the row must be deactivated (closed) before a new row is stored into the row
buffers

…….
Commonly, the access latency is improved by employing row buffers that store the most recently accessed
row data. However, if a new request tries to access a different row address from that in the row buffer,
which is a row buffer conflict, the access latency is significantly increased. In a heterogeneous multi-core
system, row buffer conflicts occur frequently because various types of processors with different access
patterns share the main memory.
…….

Dynamic memory capability depends on the capacitor as it stores the data. It's very important that
the capacitor charge each 64 ms. At this time the data holds each 64 ms and also the processor.

Each row consists of capacitor and transistor

Chapter one Page 5


Practical Section

Solve this equation using one register

𝐴+𝐵
(⎯⎯⎯⎯⎯ /𝐷)^𝐸
𝐶
𝑋 = ⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
𝐹

- It's important to transfer the data from RAM to the register cause it will be more easier and
fast to access them , so you need to use LOAD
- You also will need to use STORE to store them in the register.
- After that you will need to use the other operations used in the equation as: ADD, DIV, POW
AC is accumulator
M[] is any memory location
M[T] is temporary location

LOAD A AC <--- M[A]


ADD B AC <--- AC+M[B] : AC <-- A+B
DIV C AC <-- AC / M[C] : AC <-- A+B/C
DIV D AC <-- AC/M[D] : AC <-- A+B/C/D
POW E AC <-- AC**M[E] : AC <-- A+B/C/D ^E
DIV F AC<-- AC /M[F] : AC <- A+B/C/D ^E/F
STORE X X <-- AC

Solve this equation using TWO register

𝑋 = (𝐴 + 𝐵) ∗ (𝐶 + 𝐷)

Chapter one Page 6


Register consists of num of Flip - Flop equal to the capability of it.
Flip - Flop Store only one bit [0 or 1] - Consists of 4 NAND and 4 NOR.
The information stored within these registers can be transferred with the help of shift
registers.

Types of flip-flops:
1. SR Flip Flop
2. JK Flip Flop (Have many options)
3. D Flip Flop
4. T Flip Flop

S = 1 : Set to 1
SR R = 0 : Reset to 0
S = 1 & R = 1 : Invalid status

Shift Register is a group of flip flops used to store multiple bits of data.
• The bits stored in such registers can be made to move within the registers and
in/out of the registers by applying clock pulses.
• The registers which will shift the bits to the left are called “Shift left registers”.

Types of Shift Registers


• Serial In Serial Out shift register - SISO ( take one bit after the other - only one bit output )
• Serial In parallel Out shift register - SIPO
• Parallel In Serial Out shift register - PISO
• Parallel In parallel Out shift register - PIPO

1 1

SISO example : 0101


0 0

0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1

SISO
Serial input

Chapter one Page 7


SISO
Serial input

PISO

Chapter one Page 8

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