Shyam Sundar R

22BLC1187

RISC-V ISA & RV32I

RTL coding
INDUSTRY COMPLETE ADDRESS & CONTACT PERSONS
WITH PHONE NUMBERS

Address: 21/1A, III Floor, Marudhar Avenue, Gottigere Uttarahalli Hobli,

South Taluk, Bannerghatta Main Rd, Bengaluru, Karnataka 560076

Contact: 080 6909 6300

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Certificat
e

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 Agend
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 About the company
 Objective of the Training
 Overview of the Project
 Proposed system
 Read and Write Transfers
 Results and discussions
 Conclusion
 References

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 About the Company
• Maven Silicon is a distinguished company in the domain of VLSI (Very Large Scale Integration) design and
semiconductor technology. It has established itself as a leading institution that offers a wide array of services and
training programs related to VLSI design and verification.

• One of the standout features of Maven Silicon is its comprehensive VLSI training programs. These programs cover
a wide spectrum of topics, from the fundamentals of digital design to advanced concepts such as ASIC and FPGA
design. This ensures that students are not only taught theoretical concepts but also gain insights into the latest
industry trends and best practices

• Maven Silicon's commitment to quality education is underscored by its industry-recognized certifications, which
serve as a testament to the skills and knowledge acquired during the training programs.
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 Objective of the Training
The VLSI Design Methodologies Course by MAVEN SILICON provided an overview of VLSI and
explains various VLSI technology.Following project assignment, each student received project-specific
training. In this case, detailed concepts of

Instruction Set Architecture (ISA): Understand the fundamental principles of how instructions are encoded,
decoded, and executed.

Pipeline Design: Learn how to design efficient pipelines to improve processor performance.

Control Unit Design: Grasp the design of control units to generate control signals for the data path.

Data Path Design: Understand the components of the data path, such as registers, ALU, and memory
interface.

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Overview of the
Project
The RISC-V RV32I ISA is a 32-bit base integer instruction set architecture. It provides a simple
and efficient instruction set, making it suitable for various applications from embedded systems to
high-performance computing.

The goal of the project is to:

Design the processor's datapath and control unit using a hardware description language like
Verilog or VHDL.

Design the register file, ALU, and memory interface.

Implement the instruction decoder to recognize and decode different instructions.

Design the control unit to generate control signals for the datapath.

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RISC V 32I
Instruction Types
R type -> Register to Register
I type -> Register Immediate ,Load ,JLR
S type -> Store
B type -> Branch
J type -> Jump and Link
U type -> Load / Add upper immediate

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RISC V ISA Instruction format

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RISC V R-type I type

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RISC V L-type S-type

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RISC V B-type J-type

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RISC V ISA Immediates

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 RISC V ISA Immediates
I- Type Load and S type Store
R-type: No immediates

I type

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B type
RISC V ISA Immediates

J type

U type

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RV 32I Register File
.

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Instruction MUX

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 Instruction MUX
The MUX extracts specific bit fields from the instr_in wire based on their known locations within the MIPS RV32
instruction format and assigns them to the corresponding output registers:
 opcode_out: Captures the opcode bits (bits 6:0) of the instruction.
 funct7_out: Captures the funct7 bits (bits 31:25) of the instruction. (Might be unused depending on the
implementation)
 funct3_out: Captures the funct3 bits (bits 14:12) of the instruction.
 csr_addr_out: Captures the CSR address bits (bits 31:20) of the instruction. (Only used for CSR
instructions)
 rs1_addr_out: Captures the register address bits for the first source operand (RS1) (bits 19:15).
 rs2_addr_out: Captures the register address bits for the second source operand (RS2) (bits 24:20).
 rd_addr_out: Captures the register address bits for the destination register (RD) (bits 11:7).
 instr_31_7_out: Captures the remaining bits of the instruction from bit 31 to bit 7 (25 bits). This might be
used for immediate value extraction or other instruction-specific purposes.

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RISC V PC mux

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 Pc mux
Internal Signals
 i_addr_out (reg, 32 bits): The internal register for the instruction address.
 Pc_mux_out (wire, 32 bits): The calculated next PC value based on branching.
Misaligned Instruction Detection:
o misaligned_instr_out is set if next_pc is misaligned (i.e., if the least significant bit is 1) and branch_taken_in is
high.
PC Increment:
o pc_plus_4_out is calculated as the current pc_in plus 4, which is the address of the next sequential instruction.
Next PC Calculation:
o next_pc is calculated as:
 {iaddr_in, 1'b0} if branch_taken_in is high (indicating a branch),
 pc_plus_4_out otherwise.

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 Pc mux
PC Multiplexer:
o The pc_mux_out value is selected based on pc_src_in:
 2'b00: pc_mux_out is set to BOOT_ADDRESS.
 2'b01: pc_mux_out is set to epc_in.
 2'b10: pc_mux_out is set to trap_address_in.
 2'b11: pc_mux_out is set to next_pc.

Instruction Address Update:

o The i_addr register is updated:
 To BOOT_ADDRESS if rst_in is high (indicating a reset).
 To pc_mux_out if ahb_ready_in is high (indicating that the AHB is ready).

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RISC V Integer file

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 Integer file
Register File:
o The module uses an array of 32 registers (reg_file) to store 32-bit integer values. Each register is
identified by its address (0 to 31).
Read Operations:
o The rs_1_addr_in and rs_2_addr_in signals specify the addresses of the registers to be read for
the first and second source operands (RS1 and RS2), respectively.
o The module uses these addresses to access the corresponding registers in reg_file and assign the
read data to the rs_1_out and rs_2_out outputs.
Write Operations:
o The wr_en_in signal controls write operations to the register file.
o If wr_en_in is high (active) and rd_addr_in is valid (not zero), the data provided by rd_in is
written to the register specified by the address rd_addr_in.

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Load unit

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 Load unit
Load Size:
o The load_size_in signal specifies the size of the data to be loaded.
o Based on this value, the module selects the appropriate portion of the data_in for the output.
Byte Address Offset:
o The iadder_1_to_0_in signal indicates the byte offset within the loaded word (data_in) based on
the base address used for the load instruction. This helps select the specific byte or half-word to
be extracted.
Sign Extension:
o The load_unsigned_in signal determines whether sign extension is performed during the load
operation.
o If load_unsigned_in is high (active), the module performs zero extension for byte and half-word
loads. This means the sign bit (bit 7 for bytes and bit 15 for half-words) is replicated to fill the
higher-order bits of the output.
o If load_unsigned_in is low (inactive), the sign bit from the loaded data is replicated to extend the
sign for signed byte or half-word loads.
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Store uint

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 Store unit
Address Calculation:
o The d_addr_out is assigned the base address from iadder_in with the two least significant bits
cleared to ensure alignment for byte or halfword stores.
Data Formatting (always blocks):
 byte_dout: This register stores the rs2_in value shifted and padded with zeros depending on
the byte address within the word
 halfword_dout: This register stores the rs2_in value shifted and padded with zeros
depending on the halfword address within the word (
Output Selection and Bus Signals (always blocks):
 If ahb_ready_in is high (bus ready), the block selects the appropriate data (byte_dout,
halfword_dout, or rs2_in) based on funct3_in for writing. If ahb_ready_in is low (bus not
ready), the block sets ahb_htrans_out to 0 (no transfer).
Memory Write Request:
o The wr_req_out is simply assigned the same value as mem_wr_req_in. This module doesn't
modify the memory write request itself.
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Write back mux

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 Write back mux
ALU Second Source Mux (always block assignment):
o This assignment selects the second operand for the ALU based on the alu_source_reg_in signal.
It's done outside the main always block for efficiency.
 If alu_source_reg_in is high, it selects the value from the second source register
(rs2_reg_in).
 If alu_source_reg_in is low, it selects the immediate value (imm_reg_in).

Write-back Mux Selection (always block):

o The always@* block selects the data source for writing back to the register file based on the
wb_mux_sel_reg_in control signal.
o It uses a case statement to compare the control signal with predefined constants (WB_ALU,
WB_LU, etc.). These constants represent different stages or results within the pipeline that can
provide data for writing back.
o Depending on the matched case, the block assigns the corresponding data input (e.g.,
alu_result_in for ALU output, lu_output_in for Load Unit output, etc.) to the wb_mux_out
register.
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Write enable generator

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 Write enable generator
This module uses a simple assignment strategy to generate the write enable signals based on the flush_in signal and the
corresponding register file write enable signals from the pipeline (rf_wr_en_reg_in and csr_wr_en_reg_in).
 Flush Signal Priority:
o The flush_in signal is an active high signal, likely used for pipeline flushes or other events where writes need
to be disabled.
o The assignments prioritize the flush_in signal. If flush_in is high, both output write enables
(wr_en_integer_file_out and wr_en_csr_file_out) are set to low (writes disabled), regardless of the original
write enable signals from the pipeline.
 Normal Operation:
o If flush_in is low (inactive), the module assigns the respective register file write enable signals
(rf_wr_en_reg_in and csr_wr_en_reg_in) to the outputs (wr_en_integer_file_out and wr_en_csr_file_out).
This allows writes to proceed based on the pipeline's write enable signals when there's no flush condition.

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Instruction Decoder

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 Instruction Decoder
Opcode Decoding:
o Decodes opcode_in[6:2] to determine the type of instruction and sets corresponding flags (e.g., is_branch, is_jal,
is_jalr).
Function Code Evaluation:
o Evaluates the funct3_in field to determine specific operations for immediate ALU instructions and sets
corresponding flags (is_addi, is_slti, is_sltiu, is_andi, is_ori, is_xori)..
Memory Load/Store Handling:
o load_size_out and load_unsigned_out are set based on funct3_in.
o mem_wr_req_out is set for store instructions unless there's a misalignment or a trap.
Immediate Address Handling:
o Sets iadder_src_out for load, store, and jump register instructions.
o Determines misaligned load/store conditions based on funct3_in and iadder_1_to_0_in.

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 Instruction Decoder
Control Signal Generation:
o csr_wr_en_out and csr_op_out are set for CSR instructions.
o rf_wr_en_out is set for instructions that require writing back to the register file.
o wb_mux_sel_out and imm_type_out are set based on the type of instruction.
o illegal_instr_out is set if the instruction is not implemented or has an invalid opcode.
Trap Handling:
o Misalignment checks (misaligned_load_out, misaligned_store_out) ensure proper handling of memory alignment
issues

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Immediate generator

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 Immediate generator
 R-Type (imm_type_in = 000): These instructions (e.g., add, sub) don't use an immediate value. The module sets
imm_out to zero by replicating the sign bit (bit 31) of the instruction 20 times and concatenating it with the instruction
bits 31:20.
 I-Type (imm_type_in = 001): These instructions (e.g., addi, lw, sw) use a sign-extended immediate value in the range
of -2^12 to 2^12-1..
 S-Type (imm_type_in = 010): These instructions (e.g., sw, addi) use a sign-extended immediate value in the range of -
2^12 to 2^12-1 for memory access..
 B-Type (imm_type_in = 011): These instructions (e.g., beq, jal) use a branch offset. The module creates a 32-bit
immediate value by replicating the sign bit (bit 31) 19 times, concatenating it with bits 31, 7, 30:25, 11:8, and a 0 bit at
the least significant position. This sign-extends the branch offset based on the branch target location.
 U-Type (imm_type_in = 100): These instructions (e.g., lui) use a 20-bit unsigned immediate value. The module takes
instruction bits 31:12 and concatenates them with 12 zero bits, forming a 32-bit unsigned immediate value.
 J-Type (imm_type_in = 101): These instructions (e.g., jal) use a jump offset. The module replicates the sign bit (bit
31) 11 times, concatenates it with bits 31, 19:12, 20, 30:21, and a 0 bit, forming a 32-bit immediate value for the jump
target address.
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Alu block

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 Arithmetic:
Alu block
o Addition: op_1_in + op_2_in (or op_1_in - op_2_in if the most significant bit of opcode_in is 1)
 Logical:
o AND: op_1_in & op_2_in
o OR: op_1_in | op_2_in
o XOR: op_1_in ^ op_2_in
 Shift:
o Left Shift Logical: op_1_in << op_2_in[4:0]
o Right Shift Logical: op_1_in >> op_2_in[4:0]
o Right Shift Arithmetic: op_1_in >>> op_2_in[4:0] (sign-extended shift)
 Comparison:
o Set Less Than: op_1_in < op_2_in (sets the least significant bit of the result to 1 if op_1_in is less than op_2_in, otherwise 0)
o Set Less Than Unsigned: op_1_in < op_2_in (unsigned comparison)
 .
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Branch unit

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
Branch unit
Opcode Decoding:
o Determines the instruction type (branch, jump) based on the opcode_6_to_2_in input.
o Sets corresponding flags is_jal, is_jalr, or is_branch accordingly.
 Branch Condition Evaluation:
o For branch instructions, evaluates the branch condition based on funct3_in and rs1_in, rs2_in values.
o Sets the take flag to indicate whether the branch should be taken.
 Jump Condition:
o For jump instructions, sets the pc_mux_sel flag to indicate that the PC should be updated with the jump target.
 Branch Taken Output:
o Combines the pc_mux_sel_en and pc_mux_sel signals to determine the final branch_taken_out value.

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TOP module

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REG block 1

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 REG block 1
The module uses a positive edge-triggered clock (posedge clk_in) to synchronize its
operation with the system clock.
It includes an always block that executes on every positive clock edge.
Inside the always block, there's an if-else statement to control the value written to the pc_out
register.
• If rst_in is high (active reset), the pc_out is reset to the BOOT_ADDRESS.
This ensures the program starts from the beginning when the system is reset.
• If rst_in is low (reset inactive), the pc_out is updated with the value provided
by the pc_mux_in input. This allows the program counter to change based on the program
execution flow.

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REG block 2

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 REG block 2
The module uses a positive edge-triggered clock (posedge clk_in) to synchronize its
operation with the system clock.
It includes an always block that executes on every positive clock edge.
Inside the always block, there's an if-else statement to control the value written to the pc_out
register.
• If rst_in is high (active reset), the pc_out is reset to the BOOT_ADDRESS.
This ensures the program starts from the beginning when the system is reset.
• If rst_in is low (reset inactive), the pc_out is updated with the value provided
by the pc_mux_in input. This allows the program counter to change based on the program
execution flow.

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 TOP module
Integration: It integrates and connects all the lower-level modules of the design, establishing the
overall system's architecture.
Interface Definition: It defines the external interface of the design, including input and output
ports, clock signals, and reset signals.
Configuration: It includes parameters and settings that configure the entire design, such as clock
frequencies, memory sizes, and other system-level parameters.
Control Logic: It may contain control logic that orchestrates the interactions between different
modules, ensuring proper sequencing and data flow.
Testbench Connection: In simulation, it connects to the testbench, allowing the design to be
verified and validated.

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 Conclusion

The RISC-V 32I RTL implementation project was successfully completed, featuring a 5-stage
pipelined architecture that ensures efficient instruction execution.

The design handled critical challenges such as data and control hazard management,
optimizing performance while maintaining reliability.

Implemented in Verilog HDL, the processor demonstrated fundamental capabilities, including

instruction fetching, decoding, execution, memory access, and write-back, providing a robust
and scalable solution for modern VLSI applications.

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 Learning Outcome
Digital Design: A deep understanding of digital design principles, including logic gates, Boolean algebra, and
sequential logic.

Verilog HDL: Proficiency in writing and simulating Verilog code, a crucial skill for hardware design.

Computer Architecture: Knowledge of processor architecture, instruction set design, pipelining, and memory
systems.

VLSI Design Flow: Familiarity with the complete VLSI design flow, from RTL design to physical synthesis and
layout.

Testing and Verification: Experience in writing testbenches, simulating designs, and debugging issues.

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 Future Scope
AI and Machine Learning: Custom RISC-V cores can be designed to accelerate specific AI and ML workloads,
improving performance and efficiency.

Automotive and Aerospace: RISC-V's open-source nature and potential for customization make it attractive for
safety-critical applications in these industries.

Advanced Microarchitectures: Continued research and development in microarchitecture techniques, such as out-
of-order execution and speculative execution, will enhance the performance of RISC-V processors.

The future of RISC-V RV32 processors looks bright. Its flexibility, open-source nature, and growing ecosystem
make it a compelling choice for a wide range of applications. As the technology continues to mature, we can
expect to see even more innovative and powerful RISC-V-based products in the years to come.

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References

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Thank You
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