IRUNGATTUKOTTAI, CHENNAI-602117

ELECTRONICS AND COMMUNICATION ENGINEERING

EC3561-VLSI LABORATORY

V- SEMESTER - ECE

LAB OBSERVATION

ACADAMIC YEAR 2023-2024

Name :…………………………………………….

Register No. :………………………………………

Department :…………………………………………….
LAB Code/Name:…………………………………………….

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1
 SYLLABUS
EC3561 VLSI LABORATORY LTPC0 04 2
COURSE OBJECTIVES:
● To learn Hardware Descriptive Language (Verilog/VHDL).
● To learn the fundamental principles of Digital System Desing using HDL and FPGA.
● To learn the fundamental principles of VLSI circuit design in digital domain
● To learn the fundamental principles of VLSI circuit design in analog domain
● To provide hands on design experience with EDA platforms.
LIST OF EXPERIMENTS:
1. Design of basic combinational and sequential (Flip-flops) circuits using HDL. Simulate it using
Xilinx/Altera Software and implement by Xilinx/Altera FPGA.
2. Design an Adder ; Multiplier (Min 8 Bit) using HDL. Simulate it using Xilinx/Altera Software and implement
by Xilinx/Altera FPGA.
3. Design and implement Universal Shift Register using HDL. Simulate it using Xilinx/AlteraSoftware.
4. Design Memories using HDL. Simulate it using Xilinx/Altera Software and implement by Xilinx/Altera
FPGA.
5. Design Finite State Machine (Moore/Mealy) using HDL. Simulate it using Xilinx/Altera Software and
implement by Xilinx/Altera FPGA.
6. Design 3-bit synchronous up/down counter using HDL. Simulate it using Xilinx/AlteraSoftware and implement
by Xilinx/Altera FPGA.
7. Design 4-bit Asynchronous up/down counter using HDL. Simulate it using Xilinx/AlteraSoftware and implement
by Xilinx/Altera FPGA.
8. Design and simulate a CMOS Basic Gates & Flip-Flops. Generate Manual/AutomaticLayout.
9. Design and simulate a 4-bit synchronous counter using a Flip-Flops. GenerateManual/Automatic Layout.
10. Design and Simulate a CMOS Inverting Amplifier.
11. Design and Simulate basic Common Source, Common Gate and Common Drain Amplifiers.
12. Design and simulate simple 5 transistor differential amplifier.

COURSE OUTCOMES:
On completion of the course, students will be able to:
CO1: Write HDL code for basic as well as advanced digital integrated circuit
CO2: Import the logic modules into FPGA Boards
CO3: Synthesize Place and Route the digital Ips
CO4: Design, Simulate and Extract the layouts of Digital & Analog IC Blocks using EDAtools
CO5: Test and Verification of IC design
TOTAL: 60 PERIODS
CO’s-PO’s & PSO’s MAPPING
C PO PO PO PO PO PO PO PO PO PO1 PO1 PO1 PSO PSO PSO
1 2 - - - - - - - - - - - 2 3 2
2 3 3 1 1 - - - - - - - - 2 1 2
3 1 2 2 2 - - - - - - 1 1 2 2 2
4 - 1 3 3 1 - - - - - 1 1 2 2 2
5 3 3 3 3 1 - - - - - 1 1 2 2 2
C 2.2 2.2 2.2 2.2 1 - - - - - 1 1 2 2 2

1 - low, 2 - medium, 3 - high, ‘-' - no correlation

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XILINX 8.2i WORKING PROCEDURE:
1. Open Xilinx window by double clicking Xilinx 8.2i in the desktop. And close the Tip of the
window.

2. Go to file and click new project, Choose location by clicking on (…) Browse and Enter project
Name, and click next
3. Select the family name is Spartan 3E, speed is -4 and simulator is Verilog, select ISE simulator
click next and click finish.
4. Next--- new source ---Enter File name and select Verilog module ----Next--- enter Port
name input output variables and change the direction as input or output – Next --- Next---
Next---Next---Finish.
5. Type the program save and Expand + symbol in synthesis ----- run check syntax---run
synthesis-XST
6. Double click on View synthesis report and write final report till timing details;
7. Right click on V file in the source window, select test bench wave form and give test bench
wave file name and finish.
8. In initial timing and clock wizard: change Selection from single clock into combinational and
check selection in GSR(FPGA) and click in Finish.. (Initial length of timing can be increased)
9. Now set the input values according to the truth table in the waveforms.
10. In source window change Synthesis into Behavioral simulation and select Clock file and
click on clock file.
11. In process window expand + symbol on Xilinx ISE Simulator and run Generate Expected
Simulation result.
12. Click on Yes & get the output wave form and check the input and output using truth table.

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 INDEX
EXPT. NAME OF THE EXPERIMENT PAGE SIGN.
NO NO.
Experiments using Xilinx

1 Simulation and FPGA implementation of Half Adder and Full Adder 5

2 Simulation and FPGA implementation of Half Subtractor and Full Subtractor 11
Simulation and FPGA implementation of MULTIPLEXER and
3 DEMULTIPLEXER 17

4 Simulation and FPGA implementation of ENCODER and DECODER 25

5 Simulation and verification of Flip-Flops: SR-FF, JK-FF, D-FF & T-FF. 33
6 Simulation and FPGA implementation of 4-bit/8-bit Ripple Carry Adder 39
7 Simulation and FPGA implementation of 8-bit Serial Adder 47
8 Simulation and FPGA implementation of 4-bit BRAWN MULTIPLIER 51
Simulation and FPGA implementation of 4-Bit Bough-Wolley Array
9 Multiplier 55

10 Simulation and FPGA implementation of Universal Shift Register 59

11 Simulation of Memories 63
12 Simulation of Finite State Machine: MEALY and MOORE Circuits 67
13 Simulation and verification of Synchronous and Asynchronous Counters 71
Experiments using TANNER EDA TOOL
1 Simulation for Schematic of CMOS Inverter using S-Edit 79
2 Simulation for Schematic of CMOS NAND and NOR Gateusing S-Edit 81
Simulation for Schematic of CMOS AND and OR Gate using
3. 85
S-Edit
4 Simulation for Schematic of 5 transistor differential amplifierusing S-Edit 89

5 Design and simulation of 4-Bit counter 91

6 Design and Simulation of Common Source Amplifier 95

7 Design and Simulation of Common Drain Amplifier 99

8 Design and Simulation of Common Gate Amplifier 101

9 LAY OUT DESIGN OF CMOS INVERTER 103

CONTENT BEYOND THE SYLLABUS
1 Simulation and FPGA implementation of 8-bit ALU 107

2 Simulation of Accumulator 111

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HALF ADDER:

TRUTH TABLE:

Inputs Outputs
a b carry sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

LOGIC DIAGRAM:

FPGA PIN DETAILS for Half Adder:

Half Adder input a b

Input Switches SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8
FPGA Pin P6 P18 P24 P36 P38 P41 P69 P78
Output LED L3 L4 L5 L6 L7 L8 L9 L10
FPGA Pin P33 P34 P35 P39 P43 P44 P2 P50
Half Adder output sum carry

HALF ADDER OUTPUT WAVE FORM:

5
Aim: To write a program for the functional verification of the half adder and full adder in
verilog HDL using gate level, data flow & behavioral level modeling and implementing it in
FPGA.
Apparatus required:

1. Personal computer
2. Xilinx ISE 8.2i software
3. FPGA kit

Algorithm:
i. Open Xilinx ISE 8.2i project navigator
ii. Create new project and define the specifications and initialize the design.
iii. Write the functional module program
iv. Check the syntax and debug the errors if found
v. Synthesize the program to obtain RTL Schematic & to obtain the synthesis is report.
vi. Create a test bench waveform
vii. Verify the output by simulating the source code.

Theory:
HALF ADDER:
A half-adder is a combinational circuit that can be used to add two binary bits. It has two inputs
that represent the two bits to be added and two outputs, with one producing the SUM output and the
other producing the CARRY.

FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of three input bits. It
consists of 3 inputs and 2 outputs. Two of the input variables, represent the significant bits to be added.
The third input represents the carry from previous lower significant position. The two outputs are SUM
and CARRY.
PROGRAM: (HALF ADDER)
GATE LEVEL DATA FLOW BEHAVIORAL
module HA(sum,carry,a,b); module HA(sum,carry,a,b); module HA(sum,carry,a,b);
output sum,carry; output sum,carry; output sum,carry;
input a,b; input a,b; input a,b;
xor (sum,a,b); assign sum = a^b; reg sum,carry;
and (carry,a,b); assign carry = a&b; always@(a,b)
endmodule endmodule begin
sum = a^b;
carry = a&b;
end
endmodule
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FULL ADDER:

TRUTH TABLE:

Inputs Outputs
A B Cin Sum (S) Carry (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

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PROGRAM:(FULL ADDER)
GATE LEVEL DATA FLOW BEHAVIORAL
module FA(sum,carry,a,b,c); module FA(sum,carry,a,b,c); module FA(sum,carry,a,b,c);
output sum,carry; output sum,carry; output sum,carry;
input a,b,c; input a,b,c; input a,b,c;
wire w1,w2,w3; assign sum = a^b^c; reg sum,carry;
xor (w1,a,b); assign carry = (a&b)|(c&(a^b)); always@(a,b,c)
and (w2,a,b); endmodule begin
xor (sum,w1,c); sum = a^b^c;
and (w3,w1,c); carry = (a&b)|(c&(a^b));
or (carry,w2,w3); end
endmodule endmodule
HALF ADDER SYNTHESIS REPORT:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : HA.ngr
Top Level Output File Name : HA
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 4
Cell Usage :
# BELS 2
# LUT2 2
# IO Buffers 4
# IBUF 2
# OBUF 2
=========================================================================
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 1 out of 960 0%
Number of 4 input LUTs: 2 out of 1920 0%
Number of IOs: 4
Number of bonded IOBs: 4 out of 108 3%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING
INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.047ns
Timing Detail: All values displayed in nanoseconds (ns)

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FPGA PIN DETAILS for Full Adder:

Full Adder input a b c

Input Switches SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8
FPGA Pin P6 P18 P24 P36 P38 P41 P69 P78
Output LED L3 L4 L5 L6 L7 L8 L9 L10
FPGA Pin P33 P34 P35 P39 P43 P44 P2 P50
Full Adder output sum carry

FULL ADDER OUTPUT WAVEFORM:

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FULL ADDER SYNTHESIS REPORT:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : FA.ngr
Top Level Output File Name : FA
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 5
Cell Usage :
# BELS 2
# LUT3 2
# IO Buffers 5
# IBUF 3
# OBUF 2
=========================================================================
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 1 out of 960 0%
Number of 4 input LUTs: 2 out of 1920 0%
Number of IOs: 5
Number of bonded IOBs: 5 out of 108 4%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.FOR ACCURATE TIMING
INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.047ns
Timing Detail:

All values displayed in nanoseconds (ns)

RESULT:
Thus the logic circuit for the half adder and full adder was designed in Verilog HDL and the output is
verified in simulated waveform and it is implemented in FPGA.

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HALF SUBTRACTOR:

TRUTH TABLE:

Input Output
a b difference borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

LOGIC DIAGRAM:

FPGA PIN DETAILS for Half Subtractor:

Half Subtractor input a b

Input Switches SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8
FPGA Pin P6 P18 P24 P36 P38 P41 P69 P78
Output LED L3 L4 L5 L6 L7 L8 L9 L10
FPGA Pin P33 P34 P35 P39 P43 P44 P2 P50
Half Subtractor output difference borrow

HALF SUBTRACTOR OUTPUT WAVE FORM:

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 Aim: To write a program for the functional verification of the half subtractor and full subtractor
in verilog HDL using gate level, data flow & behavioral level modeling and implementing it in
FPGA.
Apparatus required:
1. Personal computer
2. Xilinx ISE 8.2i software
3. FPGA kit
Algorithm:
I. Open Xilinx ISE 8.2i project navigator
II. Create new project and define the specifications and initialize the design.
III. Write the functional module program
IV. Check the syntax and debug the errors if found
V. Synthesize the program to obtain RTL Schematic & to obtain the synthesis is report.
VI. Create a test bench waveform
VII. Verify the output by simulating the source code.
Theory:
HALF SUBTRACTOR:
A half-subtractor is a combinational circuit that can be used to subtract one binary digit
from another to produce a DIFFERENCE output and a BORROW output. The BORROW
output here specifies whether a ‘1’ has been borrowed to perform the subtraction.
FULL SUBTRACTOR:
A full subtractor performs subtraction operation on two bits, a minuend and a
subtrahend, and also takes into consideration whether a ‘1’ has already been borrowed by the
previous adjacent lower minuend bit or not.
As a result, there are three bits to be handled at the input of a full subtractor, namely the two
bits to be subtracted and a borrow bit designated as B in. There are two outputs, namely the
DIFFERENCE output D and the BORROW output Bo. The BORROW output bit tells whether
the minuend bit needs to borrow a ‘1’ from the next possible higher minuend bit.
PROGRAM: (HALF SUBTRACTOR)
GATE LEVEL DATA FLOW BEHAVIORAL
module HS(difference,borrow,a,b); module HS(difference,borrow,a,b); module HS(difference,borrow,a,b);
output difference,borrow; output difference,borrow; output difference,borrow;
input a,b; input a,b; input a,b;
wire w1; assign difference = a^b; reg difference,borrow;
xor (difference,a,b); assign borrow= (~a&b); always@(a,b)
not (w1,a); endmodule begin
and (borrow,w1,b); difference = a^b;
endmodule borrow= (~a&b);
end
endmodule
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FULL SUBTRACTOR:

TRUTH TABLE:

Inputs Outputs
a b c difference borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

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 PROGRAM :( FULL SUBTRACTOR)
GATE LEVEL DATA FLOW BEHAVIORAL
module FS(difference,borrow,a,b,c); module FS(difference,borrow,a,b,c); module FS(difference,borrow,a,b,c);
output difference,borrow; output difference,borrow; output difference,borrow;
input a,b,c; input a,b,c; input a,b,c;
wire w1,w2,w3,w4,w5; assign difference = a^b^c; reg difference,borrow;
xor (w1,a,b);
assign borrow = (~a&b)|(c&~(a^b)); always@(a,b,c)
xor (sum,w1,c);
not (w2,a);
endmodule begin
not (w4,w1); difference = a^b^c;
and (w3,w2,b); borrow = (~a&b)|(c&~(a^b));
and (w5,w4,c); end
or (borrow,w5,w3); endmodule
endmodule
HALF SUBTRACTOR SYNTHESIS REPORT:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : HS.ngr
Top Level Output File Name : HS
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 4
Cell Usage :
# BELS 2
# LUT2 2
# IO Buffers 4
# IBUF 2
# OBUF 2
=========================================================================
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 1 out of 960 0%
Number of 4 input LUTs: 2 out of 1920 0%
Number of IOs: 4
Number of bonded IOBs: 4 out of 108 3%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE
REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.047ns

Timing Detail:

All values displayed in nanoseconds (ns)

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FPGA PIN DETAILS for Full Subtractor:

Full Subtractor input a b c

Input Switches SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8
FPGA Pin P6 P18 P24 P36 P38 P41 P69 P78
Output LED L3 L4 L5 L6 L7 L8 L9 L10
FPGA Pin P33 P34 P35 P39 P43 P44 P2 P50
Full Subtractor output difference borrow

FULL SUBTRACTOR OUTPUT WAVEFORM:

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FULL SUBTRACTOR SYNTHESIS REPORT:

=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : FS.ngr
Top Level Output File Name : FS
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 5
Cell Usage :
# BELS 2
# LUT3 2
# IO Buffers 5
# IBUF 3
# OBUF 2
=========================================================================
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 1 out of 960 0%

Number of 4 input LUTs: 2 out of 1920 0%
Number of IOs: 5
Number of bonded IOBs: 5 out of 108 4%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING
INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.047ns
Timing Detail:

All values displayed in nanoseconds (ns)

RESULT:
Thus the logic circuit for the half subtractor and full subtractor was designed in Verilog HDL and the
output is verified in simulated waveform and it is implemented in FPGA.

16
MULTIPLEXER:

FPGA PIN DETAILS for Multiplexer:

Multiplexer inputs S0 S1 D0 D1 D2 D3
Input Switches SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8
FPGA Pin P6 P18 P24 P36 P38 P41 P69 P78
Output LED L3 L4 L5 L6 L7 L8 L9 L10
FPGA Pin P33 P34 P35 P39 P43 P44 P2 P50
Multiplexer output Y

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Aim: To write programs for the functional verification of the multiplexer and demultiplexer in verilog
HDL using gate level, data flow & behavioral modeling and implementing it in FPGA.

Apparatus required:

i. Personal computer
ii. Xilinx ISE 8.2i software
iii. FPGA kit

Algorithm:

iv. Open Xilinx ISE 8.2i project navigator

v. Create new project and define the specifications and initialize the design.
vi. Write the functional module program
vii. Check the syntax and debug the errors if found
viii. Synthesize the program to obtain RTL Schematic & to obtain the synthesis is report.
ix. Create a test bench waveform
x. Verify the output by simulating the source code.

THEOTY:

MULTIPLEXER:
A multiplexer or MUX, is a combinational circuit with more than one input line(2n), one output
line and more than one selection line(n). A multiplexer selects binary information present from one of
many input lines, depending upon the logic status of the selection inputs, and routes it to the output line.
Normally, there are 2n input lines and n selection lines whose bit combinations determine which input is
selected. The multiplexer is often labeled as MUX in block diagrams.
A multiplexer is also called a data selector, since it selects one of many inputs and steers
the binary information to the output line.

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DEMULTIPLEXER:

FPGA PIN DETAILS for DeMultiplexer:

Multiplexer inputs S0 S1 D
Input Switches SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8
FPGA Pin P6 P18 P24 P36 P38 P41 P69 P78
Output LED L3 L4 L5 L6 L7 L8 L9 L10
FPGA Pin P33 P34 P35 P39 P43 P44 P2 P50
DeMultiplexer output Y0 Y1 Y2 Y3

19
 DEMULTIPLEXER:

Demultiplex means one into many. Demultiplexing is the process of taking information
from one input and transmitting the same over one of several outputs.
A demultiplexer is a combinational logic circuit that receives information on a single
input and transmits the same information over one of several (2n) output lines.

The block diagram of a demultiplexer which is opposite to a multiplexer in its operation

is shown above. The circuit has one input signal, ‘n’ select signals and 2n output signals. The
select inputs determine to which output the data input will be connected. As the serial data is
changed to parallel data, i.e., the input caused to appear on one of the n output lines, the
demultiplexer is also called a “data distributer” or a “serial-to-parallel converter”.

PROGRAM: (MULTIPLEXER)

GATE LEVEL DATA FLOW BEHAVIORAL

module MUX(Y,S0,S1,D0,D1,D2,D3); module MUX(Y,S0,S1,D0,D1, module MUX(Y,S0,S1,D0,D1,
output Y; D2,D3); D2,D3);
input S0,S1, D0,D1,D2,D3; output Y; output Y;
wire W0,W1,W2,W3,W4,W5; input S0,S1, D0,D1,D2,D3; input S0,S1, D0,D1,D2,D3;
not(W0,S0); assign Y=(~S1&~S0&D0)+ reg Y;
not(W1,S1); (~S1&S0&D1)+ always @(S1,S0, D0,D1,D2, D3)
case({S1,S0})
and(W2,W0,W1,D0); (S1&~S0&D2)+ 2'd0:Y=D0;
and(W3,W1,S0,D1); (S1&S0&D3); 2'd1:Y=D1;
and(W4,S1,W0,D2); endmodule 2'd2:Y=D2;
and(W5,S1,S0,D3); 2'd3:Y=D3;
or(Y,W2,W3,W4,W5); endcase
endmodule
endmodule

20
MULTIPLEXER: (OUTPUT WAVEFORM)

SYNTHESIS REPORT: (MULTIPLEXER)

=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : MUX.ngr
Top Level Output File Name : MUX
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 7
Cell Usage :
# BELS 3
# LUT3 2
# MUXF5 1
# IO Buffers 7
# IBUF 6
# OBUF 1
=========================================================================
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 1 out of 960 0%
Number of 4 input LUTs: 2 out of 1920 0%
Number of IOs: 7
Number of bonded IOBs: 7 out of 108 6%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.368ns

Timing Detail:

All values displayed in nanoseconds (ns)

21
 PROGRAM: (DEMULTIPLEXER)
GATE LEVEL DATA FLOW BEHAVIORAL
module DEMUX(Y0,Y1,Y2,Y3,S0,S1,D); DEMUX(Y0,Y1,Y2,Y3,S0,S1,D); module DEMUX(D,S1,S0,Y0,Y1,Y2,Y3);
output Y0,Y1,Y2,Y3; output Y0,Y1,Y2,Y3; input D,S1,S0;
input S0,S1, D; input S0,S1, D; output Y0,Y1,Y2,Y3;
wire W0,W1; assign Y0=(~S1&~S0&D); reg Y0,Y1,Y2,Y3;
not(W0,S0); assign Y1= (~S1&S0&D) ; always@(D,S1,S0)
not(W1,S1); assign Y2=(S1&~S0&D); case({S1,S0})
and(Y0,W1,W0,D); assign Y3=(S1&S0&D); 2'b00:begin Y0=D;Y1=0;Y2=0;Y3=0; end
and(Y1,W1,S0,D); endmodule 2'b01:begin Y0=0;Y1=D;Y2=0;Y3=0; end
and(Y2,S1,W0,D); 2'b10:begin Y0=0;Y1=0;Y2=D;Y3=0; end
and(Y3,S1,S0,D); 2'b11:begin Y0=0;Y1=0;Y2=0;Y3=D; end
endmodule endcase
endmodule
SYNTHESIS REPORT: DEMULTIPLEXER
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : DEMUX.ngr
Top Level Output File Name : DEMUX
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 7
Cell Usage :
# BELS 4
# LUT3 4
# IO Buffers 7
# IBUF 3
# OBUF 4
=========================================================================
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 2 out of 960 0%
Number of 4 input LUTs: 4 out of 1920 0%
Number of IOs: 7
Number of bonded IOBs: 7 out of 108 6%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.087ns

Timing Detail:

All values displayed in nanoseconds (ns)

22
DEMULTIPLEXER: (OUTPUT WAVEFORM)

23
RESULT:
Thus the logic circuit for the multiplexer and demultiplexer was designed in Verilog HDL and the
output is verified in simulated waveform and it is implemented in FPGA.

24
8 to 3 ENCODER :( LOGIC CIRCUIT)

TRUTH TABLE:

Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

FPGA PIN DETAILS for Encoder:

Encoder inputs D0 D1 D2 D3 D4 D5 D6 D7
Input Switches SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8
FPGA Pin P6 P18 P24 P36 P38 P41 P69 P78
Output LED L3 L4 L5 L6 L7 L8 L9 L10
FPGA Pin P33 P34 P35 P39 P43 P44 P2 P50
Encoder output Y2 Y1 Y0

25
Aim: To write programs for the functional verification of the encoder and decoder in verilog HDL using
gate level, data flow & behavioral modeling and implementing it in FPGA.

Apparatus required:

1. Personal computer
2. Xilinx ISE 8.2i software
3. FPGA kit

Algorithm:

i. Open Xilinx ISE 8.2i project navigator

ii. Create new project and define the specifications and initialize the design.
iii. Write the functional module program
iv. Check the syntax and debug the errors if found
v. Synthesize the program to obtain RTL Schematic & to obtain the synthesis is report.
vi. Create a test bench waveform
vii. Verify the output by simulating the source code.

THEOTY:

ENCODER:

An encoder is a combinational circuit that converts binary information from 2n input

lines to a maximum of ‘n’ unique output lines.
The general structure of encoder circuit is –

General structure of Encoder

It has 2n input lines, only one which 1 is active at any time and ‘n’ output lines. It
encodes one of the active inputs to a coded binary output with ‘n’ bits. In an encoder, the
number of outputs is less than the number of inputs.
26
ENCODER: (OUTPUT WAVEFORM)

SYNTHESIS REPORT: ENCODER

=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : ENCODER.ngr
Top Level Output File Name : ENCODER
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 11
Cell Usage :
# BELS 3
# LUT4 3
# IO Buffers 10
# IBUF 7
# OBUF 3
=========================================================================
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 2 out of 960 0%
Number of 4 input LUTs: 3 out of 1920 0%
Number of IOs: 11
Number of bonded IOBs: 10 out of 108 9%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.077ns
Timing Detail:

All values displayed in nanoseconds (ns)

27
 DECODER:

A decoder is a combinational circuit that converts binary information from ‘n’ input lines to a
maximum of ‘2n’ unique output lines. The general structure of decoder circuit is –

General structure of decoder

The encoded information is presented as ‘n’ inputs producing ‘2n’ possible outputs. The
2n output values are from 0 through 2n-1. A decoder is provided with enable inputs to activate
decoded output based on data inputs. When any one enable input is unasserted, all outputs of
decoder are disabled.

PROGRAM: (ENCODER)

GATE LEVEL DATA FLOW

module ENCODER(Y2,Y1,Y0,D0,D1,D2,D3,D4,D5,D6,D7); module ENCODER(Y2,Y1,Y0,D0,D1,D2,D3,D4,D5,D6,D7);
output Y2,Y1,Y0; output Y2,Y1,Y0;
input D0,D1,D2,D3,D4,D5,D6,D7; input D0,D1,D2,D3,D4,D5,D6,D7;
or(Y2, D4,D5,D6,D7); assign Y2= (D4|D5|D6|D7);
or(Y1, D2,D3,D6,D7); assign Y1=(D2|D3|D6|D7);
or(Y0, D1,D3,D5,D7); assign Y0 = (D1|D3|D5|D7);
endmodule endmodule

BEHAVIORAL LEVEL
module ENCODER(Y2,Y1,Y0,D0,D1,D2,D3,D4,D5,D6,D7);
output Y2,Y1,Y0;
input D0,D1,D2,D3,D4,D5,D6,D7;
reg Y2,Y1,Y0;
always@(D0,D1,D2,D3,D4,D5,D6,D7)
begin
Y2= (D4|D5|D6|D7);
Y1=(D2|D3|D6|D7);
Y0 = (D1|D3|D5|D7);
end
endmodule

28
2 to 4 DECODER:

TRUTH TABLE:

Inputs Outputs
Enable A B Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

FPGA PIN DETAILS for Decoder:

Decoder inputs A B
Input Switches SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8
FPGA Pin P6 P18 P24 P36 P38 P41 P69 P78
Output LED L3 L4 L5 L6 L7 L8 L9 L10
FPGA Pin P33 P34 P35 P39 P43 P44 P2 P50
Decoder output Y3 Y2 Y1 Y0

29
 PROGRAM: (DECODER)

GATE LEVEL DATA FLOW

module DECODER(Y3,Y2,Y1,Y0,A,B,E); module DECODER(Y3,Y2,Y1,Y0,A,B,E);
output Y3,Y2,Y1,Y0; output Y3,Y2,Y1,Y0;
input A,B,E; input A,B,E;
wire W1,W2; assign Y0=~A&~B&E;
not(W1,A); assign Y1=~A&B&E;
not(W2,B); assign Y2=A&B&E;
and(Y0,W1,W2,E); assign Y3=A&B&E;
and(Y1,W1,B,E); endmodule
and(Y2,A,W2,E);
and(Y3,A,B,E);
endmodule

BEHAVIORAL LEVEL

module DECODER(Y3,Y2,Y1,Y0,A,B,E);
output Y3,Y2,Y1,Y0;
input A,B,E;
reg Y3,Y2,Y1,Y0;
always@(A,B,E)
begin
Y0=~A&~B&E;
Y1=~A&B&E;
Y2= A&B&E;
Y3= A&B&E;
end
endmodule

30
OUTPUT WAVEFORM: (DECODER)

=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : DECODER.ngr
Top Level Output File Name : DECODER
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 7
Cell Usage :
# BELS 4
# LUT3 4
# IO Buffers 7
# IBUF 3
# OBUF 4
=========================================================================
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 2 out of 960 0%
Number of 4 input LUTs: 4 out of 1920 0%
Number of IOs: 7
Number of bonded IOBs: 7 out of 108 6%
=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.087ns
Timing Detail:

All values displayed in nanoseconds (ns)

31
RESULT:
Thus the logic circuit for the encoder and decoder was designed in Verilog HDL and the output is
verified in simulated waveform and it is implemented in FPGA.
32
33
Aim: To write programs and simulate it for the functional verification of the Flip Flops in Verilog HDL
using behavioral modeling.

Apparatus required:

1. Personal computer
2. Xilinx ISE 8.2i software

Algorithm:

i. Open Xilinx ISE 8.2i project navigator

ii. Create new project and define the specifications and initialize the design.
iii. Write the functional module program
iv. Check the syntax and debug the errors if found
v. Synthesize the program to obtain RTL Schematic & to obtain the synthesis is report.
vi. Create a test bench waveform
vii. Verify the output by simulating the source code.

THEOTY:

Flip flops are actually an application of logic gates. With the help of Boolean logic you can
create memory with them. Flip flops can also be considered as the most basic idea of a Random Access
Memory [RAM]. When a certain input value is given to them, they will be remembered and executed, if
the logic gates are designed correctly. A higher application of flip flops is helpful in designing better
electronic circuits.

The most commonly used application of flip flops is in the implementation of a feedback circuit. As a
memory relies on the feedback concept, flip flops can be used to design it.

There are mainly four types of flip flops that are used in electronic circuits. They are

1. The basic Flip Flop or S-R Flip Flop

2. Delay Flip Flop [D Flip Flop]
3. J-K Flip Flop
4. T Flip Flop

34
OUTPUT WAVEFORM: (D-FF)

OUTPUT WAVEFORM: (T-FF)

35
PROGRAM:

SR-FLIP FLOP JK-FLIP FLOP

module SRFF(q, s, r, clk); module jkf(q,j,k,clk);
output q; input j;
input s; input k;
input r; input clk;
input clk; output q;
reg q=0; reg q=0;
always @ (posedge clk) always@ (posedge clk)
begin begin
case ({s,r}) case({j,k})
2'b00: q=q; 2'b00:q=q;
2'b01: q=0; 2'b01:q=0;
2'b10: q=1; 2'b10:q=1;
2'b11: q=1'bx; 2'b11:q=~q;
endcase endcase
end end
endmodule endmodule
Synthesis report: Final Report Synthesis report Final Report
RTL Top Level Output File Name : ff1.ngr RTL Top Level Output File Name : jkf.ngr
Top Level Output File Name : ff1 Top Level Output File Name : jkf
Output Format : NGC Output Format : NGC
Optimization Goal : Speed Optimization Goal : Speed
Keep Hierarchy : NO Keep Hierarchy : NO
Design Statistics Design Statistics
# IOs 4 # IOs 4
Cell Usage : Cell Usage :
# BELS 1 # BELS 1
# GND 1 # LUT3 1
# FlipFlops/Latches 1 # FlipFlops/Latches 1
# FDSE 1 # FD 1
# Clock Buffers 1 # Clock Buffers 1
# BUFGP 1 # BUFGP 1
# IO Buffers 3 # IO Buffers 3
# IBUF 2 # IBUF 2
# OBUF 1 # OBUF 1
Device utilization summary: Device utilization summary:
Selected Device : 3s400pq208-4 Selected Device : 3s400pq208-4
Number of Slices: 0 out of 3584 0% Number of Slices: 1 out of 3584 0%
Number of Slice Flip Flops: 1 out of 7168 0% Number of Slice Flip Flops: 1 out of 7168 0%
Number of IOs: 4 Number of 4 input LUTs: 1 out of 7168 0%
Number of bonded IOBs: 4 out of 141 2% Number of IOs: 4
IOB Flip Flops: 1 Number of bonded IOBs: 4 out of 141 2%
Number of GCLKs: 1 out of 8 12% Number of GCLKs: 1 out of 8 12%
TIMING REPORT TIMING REPORT
Clock Information: Clock Information:
+ + + + + +
Clock Signal | Clock buffer(FF name) | Load | Clock Signal | Clock buffer(FF name) | Load
+ + + |
clk | BUFGP |1 | -----------------------------------+------------------------+-------+
Timing Summary: clk | BUFGP |1 |
Speed Grade: -4 -----------------------------------+------------------------+-------+
Timing Detail: Timing Summary:
All values displayed in nanoseconds (ns) Speed Grade: -4
Timing Detail:
All values displayed in nanoseconds (ns)
36
37
 D-FLIP FLOP T-FLIP FLOP
module DFF(clk, din, dout); module TFF(q, t, clk);
input clk; output q;
input din; input t;
output dout; input clk;
reg dout; reg q=0;
always@(posedge clk,din) always@(posedge clk)
begin begin
if(clk==1) case({t})
dout=din; 1'b0: q=q;
else 1'b1: q=~q;
dout=0; end endcase
endmodule end
endmodule
Synthesis Report Synthesis report
Final Report Final Report
Final Results Final Results
RTL Top Level Output File Name : dflip.ngr RTL Top Level Output File Name : ff3.ngr
Top Level Output File Name : dflip Top Level Output File Name : ff3
Output Format : NGC Output Format : NGC
Optimization Goal : Speed Optimization Goal : Speed
Keep Hierarchy : NO Keep Hierarchy : NO
Design Statistics Design Statistics
# IOs 3 # IOs 3
Cell Usage : Cell Usage :
# FlipFlops/Latches 1 # BELS 1
# FD 1 # INV 1
# Clock Buffers 1 # FlipFlops/Latches 1
# BUFGP 1 # FDE 1
# IO Buffers 2 # Clock Buffers 1
# IBUF 1 # BUFGP 1
# OBUF 1 # IO Buffers 2
Device utilization summary: # IBUF 1
Selected Device : 3s50pq208-4 # OBUF 1
Number of Slices: 0 out of 768 0% Device utilization summary:
Number of Slice Flip Flops: 1 out of 1536 0% Selected Device : 3s400pq208-4
Number of IOs: 3 Number of Slices: 1 out of 3584 0%
Number of bonded IOBs: 3 out of 124 2% Number of Slice Flip Flops: 1 out of 7168 0%
IOB Flip Flops: 1 Number of 4 input LUTs: 1 out of 7168 0%
Number of GCLKs: 1 out of 8 12% Number of IOs: 3
TIMING REPORT Number of bonded IOBs: 3 out of 141 2%
Clock Information: Number of GCLKs: 1 out of 8 12%
+ + + TIMING REPORT
Clock Signal | Clock buffer(FF name) | Load | Clock Information:
+ + + + + +
clk | BUFGP |1 | Clock Signal | Clock buffer(FF name) | Load |
Timing Summary: -----------------------------------+------------------------+-------+
Speed Grade: -4 clk | BUFGP |1 |
Minimum period: No path found -----------------------------------+------------------------+-------+
Minimum input arrival time before clock: 1.825ns Timing Summary:
Maximum output required time after clock: 7.165ns Speed Grade: -4
Maximum combinational path delay: No path found Timing Detail:
Timing Detail: All values displayed in nanoseconds (ns)
All values displayed in nanoseconds(ns).

RESULT:
Thus the flip-flops (SR,JK,D,&T) was designed in Verilog HDL using behavioral modeling and the outputis verified
in simulated waveform.

38
4-BIT RIPPLE CARRY ADDER:

Let the 4-bit words to be added be represented by,

A3A2A1A0= 1111 and B3B2B1B0= 0011.

8- BIT RIPPLE CARRY ADDER:

Let the 8-bit words to be added be represented by,

A7A6A5A4A3A2A1A0= 11111111 and B7B6B5B4B3B2B1B0= 01100011.

39
Aim: To write programs for the functional verification of the 8bit/4bit ripple carry adder in verilog HDL
using structural modeling and implementing it in FPGA.

Apparatus required:

4. Personal computer
5. Xilinx ISE 8.2i software
6. FPGA kit

Algorithm:

i. Open Xilinx ISE 8.2i project navigator

ii. Create new project and define the specifications and initialize the design.
iii. Write the functional module program
iv. Check the syntax and debug the errors if found
v. Synthesize the program to obtain RTL Schematic & to obtain the synthesis is report.
vi. Create a test bench waveform
vii. Verify the output by simulating the source code.

Theory: (4-bit/8-bit ripple carry adder)

The 4-bit/8-bit binary adder using full adder circuits is capable of adding two 4-bit/8-bit numbers
resulting in a 4-bit/8-bit sum and a carry output.
Since all the bits of augend and addend are fed into the adder circuits simultaneously and the
additions in each position are taking place at the same time, this circuit is known as parallel adder.
The bits are added with full adders, starting from the least significant position, to form
the sum it and carry bit. The input carry C0 in the least significant position must be 0. The carry output
of the lower order stage is connected to the carry input of the next higher order stage. Hence this type of
adder is called ripple-carry adder.

40
4-BIT RIPPLE CARRY ADDER OUTPUT WAVEFORM:

FPGA PIN DETAILS for 4-Bit ripple carry adder Adder:

4-Bit inputs a0 a1 a2 a3 b0 b1 b2 b3
Input Switches SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8
FPGA Pin P6 P18 P24 P36 P38 P41 P69 P78
Output LED L3 L4 L5 L6 L7 L8 L9 L10
FPGA Pin P33 P34 P35 P39 P43 P44 P2 P50
Sum & carry output cout s3 s2 s1 s0

41
Program:

4-bit Ripple carry adder 8-bit Ripple carry adder

module pa4bit (s, cout, a,b,cin); module pa4bit (s, cout, a,b,cin);
output [3:0]s; output [7:0]s;
output cout; output cout;
input [3:0]a; input [7:0]a;
input [3:0]b; input [7:0]b;
input cin; input cin;
wire c1,c2,c3; wire c1,c2,c3,c4,c5,c6,c7;
FA fa1(s[0],c1,a[0],b[0], cin); FA fa1(s[0],c1,a[0],b[0], cin);
FA fa2(s[1],c2,a[1],b[1],c1); FA fa2(s[1],c2,a[1],b[1],c1);
FA fa3(s[2],c3,a[2],b[2],c2); FA fa3(s[2],c3,a[2],b[2],c2);
FA fa4(s[3],cout,a[3],b[3],c3); FA fa4(s[3],c4 ,a[3],b[3],c3);
endmodule FA fa5(s[4],c5,a[4],b[4],c4);
module FA(sum,carry,d,e,f); FA fa6(s[5],c6,a[5],b[5],c5);
output sum,carry; FA fa7(s[6],c7,a[6],b[6],c6);
input d,e,f; FA fa8(s[7],cout,a[7],b[7],c7);
wire w1,w2,w3; endmodule
xor (w1,d,e); module FA(sum,carry,d,e,f);
and (w2,d,e); output sum,carry;
xor (sum,w1,f); input d,e,f;
and (w3,w1,f); wire w1,w2,w3;
or (carry,w2,w3); xor (w1,d,e);
endmodule and (w2,d,e);
xor (sum,w1,f);
and (w3,w1,f);
or (carry,w2,w3);
endmodule

SYNTHYSIS REPORT: (4-BIT RIPPLE CARRY ADDER)

=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : pa4bit.ngr
Top Level Output File Name : pa4bit
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 14
Cell Usage :
# BELS 8
# LUT3 8
# IO Buffers 14
# IBUF 9
# OBUF 5
=========================================================================
42
8-BIT RIPPLE CARRY ADDER OUTPUT WAVEFORM:

43
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 4 out of 960 0%

Number of 4 input LUTs: 8 out of 1920 0%
Number of IOs: 14
Number of bonded IOBs: 14 out of 108 12%
=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 12.027ns

Timing Detail:

All values displayed in nanoseconds (ns)

44
45
SYNTHYSIS REPORT: (8-BIT RIPPLE CARRY ADDER)
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : pa4bit.ngr
Top Level Output File Name : pa4bit
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 26
Cell Usage :
# BELS 16
# LUT3 16
# IO Buffers 26
# IBUF 17
# OBUF 9
=========================================================================

Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 9 out of 960 0%
Number of 4 input LUTs: 16 out of 1920 0%
Number of IOs: 26
Number of bonded IOBs: 26 out of 108 24%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING
INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 18.667ns

Timing Detail:

All values displayed in nanoseconds (ns)

RESULT:
Thus the logic circuit for the 4-bit/8bit ripple carry adder was designed in Verilog HDL and the
output is verified in simulated waveform and it is implemented in FPGA.

46
8- BIT SERIAL ADDER OUTPUT WAVEFORM:

47
Aim: To write programs for the functional verification of the 8bit serial adder in verilog HDL using
behavioral modeling and implementing it in FPGA.

Apparatus required:

1. Personal computer
2. Xilinx ISE 8.2i software
3. FPGA kit

Algorithm:

i. Open Xilinx ISE 8.2i project navigator

ii. Create new project and define the specifications and initialize the design.
iii. Write the functional module program
iv. Check the syntax and debug the errors if found
v. Synthesize the program to obtain RTL Schematic & to obtain the synthesis is report.
vi. Create a test bench waveform
vii. Verify the output by simulating the source code.

THEOTY:

The serial binary adder or bit-serial adder is a digital circuit that performs binary addition bit by bit.
The serial full adder has three single-bit inputs for the numbers to be added and the carry in. There are
two single-bit outputs for the sum and carry out. The carry-in signal is the previously calculated carry-
out signal. The addition is performed by adding each bit, lowest to highest, one per clock cycle.

Serial binary addition is done by a flip-flop and a full adder. The flip-flop takes the carry-out signal on
each clock cycle and provides its value as the carry-in signal on the next clock cycle. After all of the bits
of the input operands have arrived, all of the bits of the sum have come out of the sum output.

48
49
PROGRAM for serial ADDER:

module serial(a0, a1, s, carry, sum);

input [7:0] a0;
input [7:0] a1;
output [7:0] s;
output carry;
output [8:0] sum;
reg[7:0]s;
reg carry;
reg [8:0] sum;
reg [1:0]b0,b1,b2,b3,b4,b5,b6,b7;
always @(a0,a1)
begin
b0= a0[0]+a1[0];
b1= a0[1]+a1[1]+b0[1];
b2= a0[2]+a1[2]+b1[1];
b3= a0[3]+a1[3]+b2[1];
b4= a0[4]+a1[4]+b3[1];
b5= a0[5]+a1[5]+b4[1];
b6= a0[6]+a1[6]+b5[1];
b7= a0[7]+a1[7]+b6[1];
s= ({ b7[0],b6[0],b5[0],b4[0],b3[0],b2[0],b1[0],b0[0]});
carry = b7[1];
sum = ({carry,s});
end
endmodule

SYNTHESIS REPORT:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : serial.ngr
Top Level Output File Name : serial
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO

50
51
Design Statistics
# IOs : 34
Cell Usage :
# BELS : 15
# LUT2 :1
# LUT3 : 12
# LUT4 :2
# IO Buffers : 34
# IBUF : 16
# OBUF : 18
=========================================================================
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 9 out of 960 0%

Number of 4 input LUTs: 15 out of 1920 0%
Number of IOs: 34
Number of bonded IOBs: 34 out of 108 31%
=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 16.959ns

Timing Detail:

All values displayed in nanoseconds (ns)

RESULT:
Thus the logic circuit for the 8bit serial adder was designed in Verilog HDL and the output is verified
in simulated waveform and it is implemented in FPGA.

52
LOGIC DIAGRAM: 4-Bit BRAWN MULTIPLIER

53
 Aim: To write program for the functional verification of the 4bit Brawn Multiplier in verilog HDL
using structural modeling and implementing it in FPGA.

Apparatus required:

1. Personal computer
2. Xilinx ISE 8.2i software
3. FPGA kit

Algorithm:

i. Open Xilinx ISE 8.2i project navigator

ii. Create new project and define the specifications and initialize the design.
iii. Write the functional module program
iv. Check the syntax and debug the errors if found
v. Synthesize the program to obtain RTL Schematic & to obtain the synthesis is report.
vi. Create a test bench waveform
vii. Verify the output by simulating the source code.

THEORY:

A binary multiplier is an electronic circuit used in digital electronics, such as a computer,

to multiply two binary numbers. It is built using binary adders.

A variety of computer arithmetic techniques can be used to implement a digital multiplier. Most techniques
involve computing a set of partial products, and then summing the partial products together. This process is
similar to the method taught to primary schoolchildren for conducting long multiplication on base-10
integers, but has been modified here for application to a base-2 (binary) numeral system.

Simple Program: 8-Bit Multiplier

module multiplier(a,b,out);
input [7:0]a,b;
output [15:0]out;
assign out= a*b;
endmodule

54
4- BIT BRAUN MULTIPLIER OUTPUT WAVEFORM:

FPGA PIN DETAILS for 4-Bit Brawn Multiplier:

4-Bit inputs a0 a1 a2 a3 b0 b1 b2 b3
Input Switches SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8
FPGA Pin P6 P18 P24 P36 P38 P41 P69 P78
Output LED L3 L4 L5 L6 L7 L8 L9 L10
FPGA Pin P33 P34 P35 P39 P43 P44 P2 P50
Product output P7 P6 P5 P4 P3 P2 P1 P0

55
PROGRAM: (4-Bit Brawn SYNTHESIS REPORT- 4-Bit Brawn Multiplier
Multiplier)
module fourbitmul(p,a,b); =====================================================
input [3:0]a,b; * Final Report *
output [7:0]p; =====================================================
wire e; Final Results
wire [15:1]t; RTL Top Level Output File Name : fourbitmul.ngr
wire [10:0]f; Top Level Output File Name : fourbitmul
wire s1,s2,s4,s5,s7,s8; Output Format : NGC
assign e= 1'b0; Optimization Goal : Speed
and Keep Hierarchy : NO
a01(p[0],a[0],b[0]), Design Statistics
a02(t[1],a[1],b[0]), # IOs 16
a03(t[2],a[2],b[0]), Cell Usage :
a04(t[3],a[3],b[0]), # BELS 27
a05(t[4],a[0],b[1]), # LUT2 4
a06(t[5],a[1],b[1]), # LUT3 2
a07(t[6],a[2],b[1]), # LUT4 21
a08(t[7],a[3],b[1]), # IO Buffers 16
a09(t[8],a[0],b[2]), # IBUF 8
a10(t[9],a[1],b[2]), # OBUF 8
a11(t[10],a[2],b[2]), =====================================================
a12(t[11],a[3],b[2]), Device utilization summary:
a13(t[12],a[0],b[3]), ---------------------------
a14(t[13],a[1],b[3]), Selected Device : 3s100etq144-4
a15(t[14],a[2],b[3]), Number of Slices: 16 out of 960 1%
a16(t[15],a[3],b[3]); Number of 4 input LUTs: 27 out of 1920 1%
fa Number of IOs: 16
fa1(t[4],e,t[1],p[1],f[0]), Number of bonded IOBs: 16 out of 108 14%
fa2(t[5],e,t[2],s1,f[1]), =====================================================
fa3(t[6],e,t[3],s2,f[2]), TIMING REPORT
fa4(t[8],f[0],s1,p[2],f[3]), NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR
fa5(t[9],f[1],s2,s4,f[4]), ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE
fa6(t[10],f[2],t[7],s5,f[5]), REPORT GENERATED AFTER PLACE-and-ROUTE.
fa7(t[12],f[3],s4,p[3],f[6]), Clock Information:
fa8(t[13],f[4],s5,s7,f[7]), ------------------
fa9(t[14],f[5],t[11],s8,f[8]), No clock signals found in this design
fa10(e,f[6],s7,p[4],f[9]), Asynchronous Control Signals Information:
fa11(f[9],f[7],s8,p[5],f[10]), ----------------------------------------
fa12(f[10],f[8],t[15],p[6],p[7]); No asynchronous control signals found in this design
endmodule Timing Summary:

module fa(a,b,c,s,carry); Speed Grade: -4

output s,carry; Minimum period: No path found
input a,b,c; Minimum input arrival time before clock: No path found
wire x1,x2,x3; Maximum output required time after clock: No path found
xor G1(x1,a,b); Maximum combinational path delay: 15.953ns
xor G2(s,x1,c); Timing Detail:
and G3(x2,a,b); --------------
and G4(x3,x1,c); All values displayed in nanoseconds (ns)
or G5(carry,x2,x3);
endmodule

RESULT:

Thus a Verilog code for a 4-bit Brawn Multiplier using structural modeling was written and their
responses for different inputs are checked in simulated output waveform and also implemented in FPGA.

56
LOGIC DIAGRAM: 4-BIT BOUGH-WOLLEY MULTIPLIER

OUTPUT WAVEFORM – Bough Wolley Array Multiplier:

FPGA PIN DETAILS for 4-Bit Bough Wolley Array Multiplier:

4-Bit inputs a0 a1 a2 a3 b0 b1 b2 b3
Input Switches SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8
FPGA Pin P6 P18 P24 P36 P38 P41 P69 P78
Output LED L3 L4 L5 L6 L7 L8 L9 L10
FPGA Pin P33 P34 P35 P39 P43 P44 P2 P50
Product output P7 P6 P5 P4 P3 P2 P1 P0

57
Aim: To write program for the functional verification of the 4bit Bough-Wolley Array Multiplier in
verilog HDL using structural modeling and implementing it in FPGA.

Apparatus required:

1. Personal computer
2. Xilinx ISE 8.2i software
3. FPGA kit

Algorithm:

i. Open Xilinx ISE 8.2i project navigator

ii. Create new project and define the specifications and initialize the design.
iii. Write the functional module program
iv. Check the syntax and debug the errors if found
v. Synthesize the program to obtain RTL Schematic & to obtain the synthesis is report.
vi. Create a test bench waveform
vii. Verify the output by simulating the source code.

THEORY:

A binary multiplier is an electronic circuit used in digital electronics, such as a computer, to multiply
two binary numbers. It is built using binary adders.

A variety of computer arithmetic techniques can be used to implement a digital multiplier. Most techniques
involve computing a set of partial products, and then summing the partial products together. This process is
similar to the method taught to primary schoolchildren for conducting long multiplication on base-10 integers,
but has been modified here for application to a base-2 (binary) numeral system.

58
SYNTHESIS REPORT- 4-Bit Brawn Multiplier:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : BWm_4bit.ngr
Top Level Output File Name : BWm_4bit
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 16
Cell Usage :
# BELS 27
# LUT2 4
# LUT3 2
# LUT4 21
# IO Buffers 16
# IBUF 8
# OBUF 8
=========================================================================
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 16 out of 960 1%
Number of 4 input LUTs: 27 out of 1920 1%
Number of IOs: 16
Number of bonded IOBs: 16 out of 108 14%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 15.705ns
Timing Detail:

All values displayed in nanoseconds (ns)

59
PROGRAM: (4-Bit Bough-Wolley Array Multiplier)

module BWM_4bit(
input signed[3:0] a,b,
output signed[7:0] P
);
wire [18:1]w;
supply0 zero;
supply1 one;
assign P[0]=a[0]&b[0];
fa fa0((a[1]&b[0]),(a[0]&b[1]),zero,P[1],w[1]);
fa fa1((a[2]&b[0]),(a[1]&b[1]),zero,w[2],w[3]);
fa fa2(~(a[3]&b[0]),(a[2]&b[1]),zero,w[5],w[7]);
fa fa3((a[0]&b[2]),w[2],w[1],P[2],w[4]);
fa fa4((a[1]&b[2]),w[5],w[3],w[6],w[8]);
fa fa5(~(a[3]&b[1]),(a[2]&b[2]),w[7],w[10],w[12]);
fa fa6(~(a[0]&b[3]),w[6],w[4],P[3],w[9]);
fa fa7(~(a[1]&b[3]),w[10],w[8],w[11],w[13]);
fa fa8(~(a[3]&b[2]),~(a[2]&b[3]),w[12],w[15],w[16]);
fa fa9(w[11],w[9],one,P[4],w[14]);
fa fa10(w[15],w[13],w[14],P[5],w[17]);
fa fa11((a[3]&b[3]),w[16],w[17],P[6],w[18]);
assign P[7]=~w[18];
endmodule
module fa(a,b,c,s,carry);
output s,carry;
input a,b,c;
wire x1,x2,x3;
xor G1(x1,a,b);
xor G2(s,x1,c);
and G3(x2,a,b);
and G4(x3,x1,c);
or G5(carry,x2,x3);
endmodule

RESULT:

Thus a Verilog code for a 4-bit Bough-Wolley Array Multiplier using structural modeling was
written and their responses for different inputs are checked in simulated output waveform and also
implemented in FPGA.
60
 BLOCK DIAGRAM OF UNIVERSAL SHIFT REGISTER:

FUNCTIONAL TABLE:

61
Aim: To write program for the functional verification of the Universal Shift Register in Verilog HDL
and implementing it in FPGA.

Apparatus required:

1. Personal computer
2. Xilinx ISE 8.2i software
3. FPGA kit

Algorithm:

i. Open Xilinx ISE 8.2i project navigator

ii. Create new project and define the specifications and initialize the design.
iii. Write the functional module program
iv. Check the syntax and debug the errors if found
v. Synthesize the program to obtain RTL Schematic & to obtain the synthesis is report.
vi. Create a test bench waveform
vii. Verify the output by simulating the source code.

THEORY:

A Universal shift register is a register which has both the right shift and left shift with parallel load
capabilities. Universal shift registers are used as memory elements in computers. A Unidirectional shift
register is capable of shifting in only one direction. A bidirectional shift register is capable of shifting in
both the directions. The Universal shift register is a combination design of bidirectional shift register
and a unidirectional shift register with parallel load provision.

62
OUTPUT WAVEFORM: UNIVERSAL SHIFT REGISTER

63
 PROGRAM
module USR(O,I,clk,reset,s,SINR,SINL);
input [3:0]I;
input [1:0]s;
input clk;
input reset,SINR,SINL;
output[3:0]O;
wire [3:0]w;
reg [27:0]count=0;
// MUX moduaal calling
mux4to1 m1(w[0],s[1],s[0],I[0],SINL,O[1],O[0]);
mux4to1 m2(w[1],s[1],s[0],I[1],O[0],O[2],O[1]);
mux4to1 m3(w[2],s[1],s[0],I[2],O[1],O[3],O[2]);
mux4to1 m4(w[3],s[1],s[0],I[3],O[2],SINR,O[3]);
// D Flip Flop Modual Calling
Dff d1(O[0],w[0],clk,reset);
Dff d2(O[1],w[1],clk,reset);
Dff d3(O[2],w[2],clk,reset);
Dff d4(O[3],w[3],clk,reset);
// increment count on every clock
endmodule

// sub module for D flip-flop

module Dff(q,d,clk,reset);
output reg q;
input d,clk,reset;
always@(posedge clk)
if(reset ==1'b1)
q<= 1'b0;
else
q<=d;
endmodule

// submodule for 4 to 1 MUX

module mux4to1(y,s1,s0,i3,i2,i1,i0);
output reg y;
input i3,i2,i1,i0;
input s1,s0;
always@(s1,s0,i3,i2,i1,i0)
begin
if (s0==0&s1==0)
y=i0;
else if (s0==0&s1==1)
y=i1;
else if (s0==1&s1==0)
y=i2;
else if (s0==1&s1==1)
y=i3;
end
endmodule

RESULT:

Thus a Verilog code for a Universal Shift Register was written and their responses for different inputs are
checked in simulated output waveform and also implemented in FPGA.

64
SINGLE-PORT RAM WITH ASYNCHRONOUS READ:

Verilog CODE:

Following is the Verilog code for a single-port RAM with asynchronous read.
module raminfr (clk, we, a, di, do);

input clk;
input we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];

always @(posedge clk) begin

if (we)
ram[a] <= di;
end
assign do = ram[a];
endmodule

65
Aim: To write programs for the functional verification of the RAM in verilog HDL

Apparatus required:

1. Personal computer
2. Xilinx ISE 8.2i software
3. FPGA kit

Algorithm:

i. Open Xilinx ISE 8.2i project navigator

ii. Create new project and define the specifications and initialize the design.
iii. Write the functional module program
iv. Check the syntax and debug the errors if found
v. Synthesize the program to obtain RTL Schematic & to obtain the synthesis is report.
vi. Create a test bench waveform
vii. Verify the output by simulating the source code.

THEOTY:

There are two main types of RAM: Dynamic RAM (DRAM) and Static RAM (SRAM). DRAM
(pronounced DEE-RAM), is widely used as a computer's main memory. Each DRAM memory cell is
made up of a transistor and a capacitor within an integrated circuit, and a data bit is stored in the
capacitor.

66
SINGLE-PORT RAM WITH "FALSE" SYNCHRONOUS READ:

VERILOG CODE:

Following is the Verilog code for a single-port RAM with "false" synchronous read.
module raminfr (clk, we, a, di, do);

input clk;
input we;
input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
reg [3:0] do;

always @(posedge clk) begin

if (we)
ram[a] <= di;
do <= ram[a];
end

endmodule

http://www.csit-
sun.pub.ro/courses/Masterat/Xilinx%20Synthesis%20Technology/toolbox.xilinx.com/docs
an/xilinx4/data/docs/xst/hdlcode14.html

67
RESULT:

Thus programs for the functional verification of the RAM in verilog HDL written and its read operation
was tested in simulated waveform.

68
MOORE FSM:

State Diagram:( MOORE FSM)

State Diagram:( MEALY FSM)

69
Aim: To write programs for the functional verification of the Mealy and Moore design in verilog HDL

Apparatus required:

1. Personal computer
2. Xilinx ISE 8.2i software
3. FPGA kit

Algorithm:

i. Open Xilinx ISE 8.2i project navigator

ii. Create new project and define the specifications and initialize the design.
iii. Write the functional module program
iv. Check the syntax and debug the errors if found
v. Synthesize the program to obtain RTL Schematic & to obtain the synthesis is report.
vi. Create a test bench waveform
vii. Verify the output by simulating the source code.

THEOTY:

Moore FSM:
The state vector (also current state, or just state) is the value currently stored by the state memory. The
next state of the machine is a function of the state vector in Moore;
Consider the case of a circuit to detect a pair of 1's or 0's in the single bit input. That is, input will be a
series of one's and zero's. If two one's or two zero's comes one after another, output should go high.
Otherwise output should be low.
Here is a Moore type state transition diagram for the circuit. When reset, state goes to 00; If input is 1,
state will be 01 and if input is 0, state goes to 10. State will be 11 if input repeats. After state 11, goes to
10 state or 01 depending on the inp, since overlapping pair should not be considered. That is, if 111
comes, it should consider only one pair.

MEALY FSM:
. Output depends on both state and input. When reset, state becomes idle, that is 00. Next, if 1 comes,
state becomes 01 and if 0 comes state becomes 10 with output 0. We have showed input 1, output 0 as
1/0. If input bit repeats, output becomes 1 and state goes to 00.

70
71
Verilog Code for Moore FSM: Verilog Code for Mealy FSM:
module fsm( clk, rst, inp, outp); module mealy( clk, rst, inp, outp);
input clk, rst, inp; input clk, rst, inp;
output outp; output outp;
reg [1:0] state; reg [1:0] state;
reg outp; reg outp;
always @( posedge clk, posedge rst ) always @( posedge clk, posedge rst ) begin
begin if( rst ) begin
if( rst ) state <= 2'b00;
state <= 2'b00; outp <= 0;
else end
begin else begin
case( state ) case( state )
2'b00: 2'b00: begin
begin if( inp ) begin
if( inp ) state <= 2'b01; state <= 2'b01;
else state <= 2'b10; outp <= 0;
end end
2'b01: else begin
begin state <= 2'b10;
if( inp ) state <= 2'b11; outp <= 0;
else state <= 2'b10; end
end end
2'b10: 2'b01: begin
begin if( inp ) begin
if( inp ) state <= 2'b01; state <= 2'b00;
else state <= 2'b11; outp <= 1;
end end
2'b11: else begin
begin state <= 2'b10;
if( inp ) state <= 2'b01; outp <= 0;
else state <= 2'b10; end
end end
endcase 2'b10: begin
end if( inp ) begin
end state <= 2'b01;
always @(posedge clk, posedge rst) outp <= 0;
begin end
if( rst ) else begin
outp <= 0; state <= 2'b00;
else if( state == 2'b11 ) outp <= 1;
outp <= 1; end
else outp <= 0; end
end default: begin
endmodule state <= 2'b00;
outp <= 0;
end
endcase
end
end
endmodule

RESULT:
Thus the logic circuit for the Moore and Mealy was designed in Verilog HDL and the output is
verified in simulated waveform.

72
LOGIC DIAGRAM:

SYNCHRONOUS COUNTER: (UP COUNTER)

ASYNCHRONOUS COUNTER: ( DOWN COUNTER)

73
AIM:
To develop the source code for synchronous and asynchronous counter by using VERILOG and obtain
the simulation output.

Apparatus required:

1. Personal computer
2. Xilinx ISE 8.2i software
Algorithm:

i. Open Xilinx ISE 8.2i project navigator

ii. Create new project and define the specifications and initialize the design.
iii. Write the functional module program
iv. Check the syntax and debug the errors if found
v. Synthesize the program to obtain RTL Schematic & to obtain the synthesis is report.
vi. Create a test bench waveform
vii. Verify the output by simulating the source code.

THEORY:
In electronics, counters can be implemented quite easily using register-type circuits such as the flip-flop,
and a wide variety of classifications exist:

• Asynchronous (ripple) counter – changing state bits are used as clocks to subsequent state flip-
flops
• Synchronous counter – all state bits change under control of a single clock
• Decade counter – counts through ten states per stage
• Up/down counter – counts both up and down, under command of a control input
• Ring counter – formed by a shift register with feedback connection in a ring
• Johnson counter – a twisted ring counter
• Cascaded counter
• Modulus counter.
Each is useful for different applications. Usually, counter circuits are digital in nature, and count in natural
binary. Many types of counter circuits are available as digital building blocks, for example a number of
chips in the 4000 series implement different counters.

Occasionally there are advantages to using a counting sequence other than the natural binary sequence
such as the binary coded decimal counter, a linear feedback shift register counter, or a Gray-code counter.
Counters are useful for digital clocks and timers, and in oven timers, VCR clocks, etc.

74
SIMULATION OUTPUT: (Synchronous up counter)

SIMULATION OUTPUT: (Asynchronous down counter)

75
 PROGRAM:

SYNCHRONOUS COUNTER: ASYNCHRONOUS COUNTER:

module upcounter(clear, clk, q); module downcounter(clear,clk,q);
input clear; nput clear;
nput clk; input clk;
output [3:0] q; output [3:0] q;
reg [3:0] q; reg [3:0] q;
reg [3:0]z=4'b0000; reg [3:0] z;
always@(clk) always@(clk)
begin begin
if(clk==1'b1) if(clear==1'b1)
if(clear==1'b1) begin
z=4'b0000; z=4'b0000;
else end
z=z+4'b0001; else if(clk==1'b1)
q=z; begin
end z=z-"0001";
endmodule end
q=z;
end
endmodule
SYNTHESIS REPORT: SYNTHESIS REPORT:

Device utilization summary: Device utilization summary:

Selected Device : 3s400tq144-5 Selected Device : 3s400tq144-5
Number of Slices: 5 out of 3584 0% Number of Slices: 5 out of 3584 0%
Number of Slice Flip Flops: 8 out of 7168 0% Number of Slice Flip Flops: 8 out of 7168 0%
Number of 4 input LUTs: 3 out of 7168 0% Number of 4 input LUTs: 3 out of 7168 0%
Number of bonded IOBs: 5 out of 97 5% Number of bonded IOBs: 5 out of 97 5%
Number of GCLKs: 1 out of 8 12% Number of GCLKs: 1 out of 8 12%
Clock Information:
+ + + Timing Detail:
Clock Signal | Clock buffer(FF name) | Load | All values displayed in nanoseconds (ns)
-----------------------------------+------------------------+-------+ Timing constraint: Default period analysis for Clock 'clk'
clk | BUFGP |8 | Clock period: 2.670ns (frequency: 374.574MHz)
-----------------------------------+------------------------+-------+ Total number of paths / destination ports: 14 / 8
Timing Detail: Delay: 2.670ns (Levels of Logic = 1)
All values displayed in nanoseconds (ns) Source: d_0 (LATCH)
Timing constraint: Default period analysis for Clock 'clk' Destination: d_0 (LATCH)
Clock period: 2.670ns (frequency: 374.574MHz) Source Clock: clk falling
Total number of paths / destination ports: 14 / 8 Destination Clock: clk falling
Delay: 2.670ns (Levels of Logic = 1)
Source: d_0 (LATCH)
Destination: d_0 (LATCH)
Source Clock: clk falling
Destination Clock: clk falling

76
MOD-10 SYNCHRONOUS COUNTER

4 BIT ASYNCHRONOUS UP/DOWN COUNTER:

77
MOD-10 COUNTER: 4 BIT UPDOWN COUNTER:
module mod(clk,d,q); module updown(m,clk,i,a, b, c,d);
input clk,d; input clk;
output [3:0]q; input i,m;
wire p; output a,b,c,d;
not a(p,q[3]); wire p;
jkff a1(d,d,q[0],clk); not(p,m);
jkff a2(d&p&q[0],d&q[0],q[1],clk); jkff aa(clk,i,i,d);
jkff a3(d&q[1]&q[0],d&q[1]&q[0],q[2],clk); jkff bb((m&d)|(p&(~d)),i,i,c);
jkff a4(d&q[2]&q[1]&q[0],d&q[0],q[3],clk); jkff cc((m&c&d)|(p&(~c)&(~d)),i,i,b);
endmodule jkff dd((m&d&c&b)|(p&(~d)&(~c)&(~b)),i,i,a);
endmodule
module jkff(j,k,q,clk);
input j,k,clk; module jkff(clk,j,k,q);
output q; input clk,j,k;
reg q=0; output q;
always @(posedge clk) reg q=0;
begin always @(negedge clk )
if(j==0 && k==0) begin
q=q; if(j==0 & k==0)
else if(j==0 && k==1) q=q;
q=0; else if (j==0 & k==1)
else if(j==1 && k==0) q=0;
q=1; else if(j==1 & k==0)
else q=1;
q=~q; else q=~q;
end end
endmodule endmodule

RESULT:
Thus, the SYNCHRONOUS AND ASYNCHRONOUS COUNTER are simulated and synthesized
withVERILOG program.

78
79
Experiments using
TANNER EDA
TOOL

80
SCHEMATIC ENTRY AND SPICE SIMULATION OF CMOS INVERTER

SCHEMATIC DIAGRAM:

OUTPUT:

81
 AIM:
To perform the functional verification of the CMOS Inverter through schematic entry.

a) THEORY: (CMOS NOT)

• Inverter consists of nMOS and pMOS transistor in series connected between VDD and GND.
• The gate of the two transistors are shorted and connected to the input. When the input to the inverter A =0,
nMOS transistor is OFF and pMOS transistor is ON. The output is pull- up to VDD.When the input A=1,
nMOS transistor is ON and pMOS transistor is OFF. The Output is Pull-down to GND.

RESULT:
Thus the inverter through schematic entry was simulated and the output also verified successfully.
82
Schematic of CMOS NAND:

SIMULATION OUTPUT: (NAND GATE)

83
AIM:
To perform the functional verification of the universal gate through schematic entry.

84
Schematic of CMOS NOR:

SIMULATION OUTPUT: (NOR GATE)

85
RESULT:
Thus the NAND& NOR Gate through schematic entry was simulated and the output also verified
successfully.
86
SCMATIC Of AND GATE:

OUTPUT WAVE: (AND GATE)

87
AIM:
To perform the functional verification of the AND and OR gate through schematic entry.

88
SCHEMATIC OF CMOS OR GATE:

OUTPUT WAVE: (OR GATE)

89
RESULT:
Thus the of the AND& OR Gates through schematic entry was simulated and the output also verified
successfully.

90
DIFFERENTIAL AMPLIFIER:

OUTPUT WAVEFORM:

91
AIM:
To implement Differential amplifier using tanner EDA tool.

SOFTWARE REQUIRED:
Tanner EDA S-Edit Software.

RESULT:
Thus the differential amplifier is simulated in S-Edit and verified its functionality.

92
 4-BIT COUNTER

SCHEMATIC DIAGRAM:

93
 AIM:
To perform the functional verification of the 4-bit counter circuit through schematic entry.

FACILITIES REQUIRED AND PROCEDURE

a) Facilities required for doing the experiment

S.No. SOFTWARE REQUIREMENTS QUANTITY

1 S-Edit, W-Edit, T-Edit using Tanner Tool. 1

b) Procedure for doing the experiment

S.NO DETAILS OF THE STEP

1 Draw the schematic of 4-bit counter using S-edit

2 Perform Transient Analysis of the 4-bit counter

3 Obtain the spice code using T-edit

4 Obtain the output wave form from W-edit

c) THEORY: (COUNTER)

A counter that can change state in either direction, under the control of an up or down selector input, is
known as an up/down counter. When the selector is in the up state, the counter increments its value. When
the selector is in the down state, the counter decrements the count. Likewise the counter counts in both the
directions continuously until attaining the end of the count. The count is init iated by the positive clock
pulse. The counter counts from 0000 to 1111 for up count and 1111 to 0000 for down count.

94
OUTPUT WAVEFORM:

95
RESULT:

Thus, the functional verification of the 4-bit counter circuit through schematic entry was verified.
96
SCHEMATIC ENTRY: (Common Source Amplifier)

OUTPUT WAVEFORM:

97
 AIM:
To perform the Design and Simulation of Common Source Amplifier circuit through
schematic entry.

FACILITIES REQUIRED AND PROCEDURE

a) Facilities required to do the experiment

S.No. SOFTWARE REQUIREMENTS QUANTITY

1 S-Edit, W-Edit, T-Edit using Tanner Tool. 1

b) Procedure for doing the experiment

S.NO DETAILS OF THE STEP

1 Draw the schematic of Common Source Amplifier using S-edit

2 Perform Transient Analysis of Common Source Amplifier circuit

3 Obtain the spice code using T-edit

4 Obtain the output wave form from W-edit

c) THEORY:
In electronics, a common-source amplifier is one of three basic single-stage field-effect transistor
(FET) amplifier topologies, typically used as a voltage or transconductance amplifier. The easiest
way to tell if a FET is common source, common drain, orcommon gate is to examine where the
signal enters and leaves. The remaining terminal is what is known as "common". In this example,
the signal enters the gate, and exits the drain. The only terminal remaining is the source. This is a
common-source FET circuit. The analogous bipolar junction transistor circuit is the common-emitter
amplifier.

The common-source (CS) amplifier may be viewed as a transconductance amplifier or as a voltage

amplifier. (See classification of amplifiers). 98
99
 As a transconductance amplifier, the input voltage is seen as modulating the current going to the load.
As a voltage amplifier, input voltage modulates the amount of current flowing through the FET,
changing the voltage across the output resistance according to Ohm's law. However, the FET device's
output resistance typically is not high enough for a reasonable transconductance amplifier (ideally
infinite), nor low enough for a decent voltage amplifier (ideally zero). Another major drawback is the
amplifier's limited high- frequency response.

RESULT:
Thus, The Common Source Amplifier circuit was designed through schematic entry and performance
was verified in the Simulation.
.

100
 SCHEMATIC ENTRY: (Common Drain Amplifier)

OUTPUT WAVEFORM:

101
 AIM:
To perform the Design and Simulation of Common drain amplifier circuit through schematic entry.
FACILITIES REQUIRED AND PROCEDURE
a) Facilities required to do the experiment.

S.No. SOFTWARE REQUIREMENTS QUANTITY

1 S-Edit, W-Edit, T-Edit using Tanner Tool. 1

b) Procedure for doing the experiment

S.NO DETAILS OF THE STEP

1 Draw the schematic of Common drain amplifier using S-edit

2 Perform Transient Analysis of Common drain amplifier circuit

3 Obtain the spice code using T-edit

4 Obtain the output wave form from W-edit

THEORY:
Common drain amplifier is a source follower or buffer amplifier circuit using a MOSFET.
The output is simply equal to the input minus about 2.2V. The advantage of this circuit is that the
MOSFET can provide current and power gain; the MOSFET draws no current from the input. It
provides low output impedance to any circuit using the output of the follower, meaning that the
output will not drop under load.Its output impedance is not as low as that of an emitter follower
using a bipolar transistor (as you can verify by connecting a resistor from the output to -15V), but it
has the advantage that the input impedance is infinite. The MOSFET is in saturation, so the current
across it is determined by the gate-source voltage. Since a current source keeps the current constant,
the gate-source voltage is also constant.
RESULT:
Thus, The Common Drain Amplifier circuit was designed through schematic entry and performance
was verified in the Simulation.

102
 SCHEMATIC ENTRY: (Common Gate Amplifier)

OUTPUT WAVEFORM:

103
 AIM:
To perform the Design and Simulation of Common Gate amplifier circuit through schematic entry.
FACILITIES REQUIRED AND PROCEDURE
c) Facilities required to do the experiment.

S.No. SOFTWARE REQUIREMENTS QUANTITY

1 S-Edit, W-Edit, T-Edit using Tanner Tool. 1

d) Procedure for doing the experiment

S.NO DETAILS OF THE STEP

1 Draw the schematic of Common drain amplifier using S-edit

2 Perform Transient Analysis of Common drain amplifier circuit

3 Obtain the spice code using T-edit

4 Obtain the output wave form from W-edit

THEORY:
In common source amplifier and source follower circuits, the input signal are applied to the gate of a
MOSFET. It is also possible to apply the input signal to the source terminal by keeping common gate
terminal. This type of amplifier is called as common gate amplifier.

Figure below shows the CG amplifier in which the input signal is sensed at the source terminal and
the output is produced at the drain terminal. The gate terminal is connected to VB i.e. dc potential
which will maintain the proper operating conditions.

RESULT:
Thus, The Common Gate Amplifier circuit was designed through schematic entry and
performance was verified in the Simulation.
104
LAYOUT DIAGRAM:

OUTPUT WAVEFORM:

105
AIM:
To design and simulate CMOS inverter layout.

SOFTWARE REQUIRED:

TANNER EDA L-EDIT -1

Personal Computer -1

zRESULT:
Thus CMOS inverter layout diagram was drawn using Tanner EDA L-Edit and its response is verified in
output waveform.

106
107
CONTENT BEYOND THE
SYLLABUS

108
LOGIC DIAGRAM:

109
Aim: To write program for the functional verification of the 8-bit ALU in Verilog HDL using
behavioural modeling and implementing it in FPGA.

Apparatus required:

1. Personal computer
2. Xilinx ISE 8.2i software
3. FPGA kit

Algorithm:

i. Open Xilinx ISE 8.2i project navigator

ii. Create new project and define the specifications and initialize the design.
iii. Write the functional module program
iv. Check the syntax and debug the errors if found
v. Synthesize the program to obtain RTL Schematic & to obtain the synthesis is report.
vi. Create a test bench waveform
vii. Verify the output by simulating the source code.

THEORY:

An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic operations. It
represents the fundamental building block of the central processing unit (CPU) of a computer. Modern
CPUs contain very powerful and complex ALUs. In addition to ALUs, modern CPUs contain a control
unit (CU).

110
OUTPUT WAVEFORM: 8-Bit ALU

111
PROGRAM: 8-Bit ALU
module alu(
input [7:0] A,B, // ALU 8-bit Inputs
input [3:0] ALU_Sel,// ALU Selection
output [7:0] ALU_Out, // ALU 8-bit Output
output CarryOut // Carry Out Flag
);
reg [7:0] ALU_Result;
wire [8:0] tmp;
assign ALU_Out = ALU_Result; // ALU out
assign tmp = {1'b0,A} + {1'b0,B};
assign CarryOut = tmp[8]; // Carryout flag
always @(*)
begin
case(ALU_Sel)
4'b0000: // Addition
ALU_Result = A + B ;
4'b0001: // Subtraction
ALU_Result = A - B ;
4'b0010: // Multiplication
ALU_Result = A * B;
4'b0011: // Division
ALU_Result = A/B;
4'b0100: // Logical shift left
ALU_Result = A<<1;
4'b0101: // Logical shift right
ALU_Result = A>>1;
4'b0110: // Rotate left
ALU_Result = {A[6:0],A[7]};
4'b0111: // Rotate right
ALU_Result = {A[0],A[7:1]};
4'b1000: // Logical and
ALU_Result = A & B;
4'b1001: // Logical or
ALU_Result = A | B;
4'b1010: // Logical xor
ALU_Result = A ^ B;
4'b1011: // Logical nor
ALU_Result = ~(A | B);
4'b1100: // Logical nand
ALU_Result = ~(A & B);
4'b1101: // Logical xnor
ALU_Result = ~(A ^ B);
4'b1110: // Greater comparison
ALU_Result = (A>B)?8'd1:8'd0 ;
4'b1111: // Equal comparison
ALU_Result = (A==B)?8'd1:8'd0 ;
default: ALU_Result = A + B ;
endcase
end
endmodule

RESULT:

Thus a Verilog code for a 8-bit ALU using behavioural modeling was written and their responses for
different inputs are checked in simulated output waveform and also implemented in FPGA.

112
ACCUMULATOR:

113
AIM:
To implement accumulator using structural simulation in Xilinx ISE.

Apparatus required:

1. Personal computer
2. Xilinx ISE 8.2i software

Algorithm:

i. Open Xilinx ISE 8.2i project navigator

ii. Create new project and define the specifications and initialize the design.
iii. Write the functional module program
iv. Check the syntax and debug the errors if found
v. Synthesize the program to obtain RTL Schematic & to obtain the synthesis is report.
vi. Create a test bench waveform
vii. Verify the output by simulating the source code.

PROGRAM:

Behavioural:
module accumulator (clk,clr,d,q);
input clr,clk;
input [0:3]d;
output [0:3]q;
reg [3:0]temp;
always @ (posedge clk or clr )
begin
if (clr)
temp=4'b0000;
else
temp= temp+d;
end
assign q=temp;
endmodule

114
WAVEFORM:

115
RESULT:
Thus a Verilog code for an accumulator using behavioral modeling was written and their
responses for different inputs are verified.

116
STEPS TO FOLLOW IN XILINX 8.2i:

1. Open Xilinx window by double clicking Xilinx 8.2i in the desktop. And close the Tip of the window.

2. File--- New project----

Choose location by clicking on (…) Browse and Enter project Name,

3. Then clock Next and set FPGA device properties

117
4. Next--- new source ---Enter File name and select Verilog module ----Next--- enter Port name
input output variables and change the direction as input or output – Next --- Next---Next---Next--
-Finish.

5. Type the program in program window. Expand + symbol in synthesis ----- run check syntax---
run synthesis-XST

118
 6. Double click on View synthesis report and write final report till timing details;

7. To create test bench waveform: Write click on .v file ----- new source

8. Assign file name and select Test bench wave form --- Next --- Next ---- Finish

119
 9. In initial timing and clock wizard: change Selection from single clock into combinational and
check selection in GSR(FPGA) and click in Finish.. (Initial length of timing can be increased)

10. Set the input wave forms according to truth table the save it and close this waveform window.

11. In source window change Synthesis into Behavioral simulation and select Clock file as shown
below.

12. In process window expand + symbol on Xilinx ISE Simulator and run Generate Expected
Simulation result.

120
13. Click on Yes & get the output wave form and check the input and output using truth table.

121
Steps to use Tanner tool:
i. SCHEMATIC (S-edit):
Start the tanner EDA by using the desktop shortcut or by using the

➢ Start → Programs → tanner EDA →tanner tool v13.0 →S-edit.

122
123
124
125
126
127
128
129
 ii) Layout (L-edit):
Start → Programs → tanner EDA →tanner tool v13.0 →L-edit

130
131
132
133
134
135
136
137
138
139
140
141
HALF ADDER SYNTHESIS REPORT:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : HA.ngr
Top Level Output File Name : HA
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 4
Cell Usage :
# BELS 2
# LUT2 2
# IO Buffers 4
# IBUF 2
# OBUF 2
=========================================================================
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 1 out of 960 0%
Number of 4 input LUTs: 2 out of 1920 0%
Number of IOs: 4
Number of bonded IOBs: 4 out of 108 3%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING
INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.047ns
Timing Detail: All values displayed in nanoseconds (ns)

HALF ADDER OUTPUT WAVE FORM:

142
143
FULL ADDER SYNTHESIS REPORT:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : FA.ngr
Top Level Output File Name : FA
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 5
Cell Usage :
# BELS 2
# LUT3 2
# IO Buffers 5
# IBUF 3
# OBUF 2
=========================================================================
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 1 out of 960 0%
Number of 4 input LUTs: 2 out of 1920 0%
Number of IOs: 5
Number of bonded IOBs: 5 out of 108 4%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.FOR ACCURATE TIMING INFORMATION PLEASE
REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.047ns
Timing Detail:

All values displayed in nanoseconds (ns)

FULL ADDER OUTPUT WAVEFORM:

144
145
HALF SUBTRACTOR SYNTHESIS REPORT:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : HS.ngr
Top Level Output File Name : HS
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 4
Cell Usage :
# BELS 2
# LUT2 2
# IO Buffers 4
# IBUF 2
# OBUF 2
=========================================================================
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 1 out of 960 0%
Number of 4 input LUTs: 2 out of 1920 0%
Number of IOs: 4
Number of bonded IOBs: 4 out of 108 3%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE
REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.047ns
Timing Detail:

All values displayed in nanoseconds (ns)

HALF SUBTRACTOR OUTPUT WAVE FORM:

146
147
FULL SUBTRACTOR SYNTHESIS REPORT:

=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : FS.ngr
Top Level Output File Name : FS
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 5
Cell Usage :
# BELS 2
# LUT3 2
# IO Buffers 5
# IBUF 3
# OBUF 2
=========================================================================
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 1 out of 960 0%
Number of 4 input LUTs: 2 out of 1920 0%
Number of IOs: 5
Number of bonded IOBs: 5 out of 108 4%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE
REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.047ns
Timing Detail:

All values displayed in nanoseconds (ns)

FULL SUBTRACTOR OUTPUT WAVEFORM:

148
149
SYNTHYSIS REPORT: (4-BIT RIPPLE CARRY ADDER)
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : pa4bit.ngr
Top Level Output File Name : pa4bit
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 14
Cell Usage :
# BELS 8
# LUT3 8
# IO Buffers 14
# IBUF 9
# OBUF 5
=========================================================================
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 4 out of 960 0%

Number of 4 input LUTs: 8 out of 1920 0%
Number of IOs: 14
Number of bonded IOBs: 14 out of 108 12%
=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4

Minimum period: No path found

Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 12.027ns

Timing Detail:

All values displayed in nanoseconds (ns)

150
151
4-BIT RIPPLE CARRY ADDER OUTPUT WAVEFORM:

152
153
SYNTHYSIS REPORT: (8-BIT RIPPLE CARRY ADDER)
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : pa4bit.ngr
Top Level Output File Name : pa4bit
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 26
Cell Usage :
# BELS 16
# LUT3 16
# IO Buffers 26
# IBUF 17
# OBUF 9
=========================================================================

Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 9 out of 960 0%
Number of 4 input LUTs: 16 out of 1920 0%
Number of IOs: 26
Number of bonded IOBs: 26 out of 108 24%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING
INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 18.667ns

Timing Detail:

All values displayed in nanoseconds (ns)

154
155
8-BIT RIPPLE CARRY ADDER OUTPUT WAVEFORM:

156
157
SYNTHESIS REPORT:
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : serial.ngr
Top Level Output File Name : serial
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 34
Cell Usage :
# BELS 15
# LUT2 1
# LUT3 12
# LUT4 2
# IO Buffers 34
# IBUF 16
# OBUF 18
=========================================================================
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 9 out of 960 0%
Number of 4 input LUTs: 15 out of 1920 0%
Number of IOs: 34
Number of bonded IOBs: 34 out of 108 31%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 16.959ns
Timing Detail:

All values displayed in nanoseconds (ns)

8-BIT SERIAL ADDER OUTPUT WAVEFORM:

158
159
LOGIC DIAGRAM: 4-Bit BRAWN MULTIPLIER

4-BIT BRAUN MULTIPLIER OUTPUT WAVEFORM:

160
161
SYNTHESIS REPORT- 4-Bit Brawn Multiplier:
=====================================================
* Final Report *
=====================================================
Final Results
RTL Top Level Output File Name : fourbitmul.ngr
Top Level Output File Name : fourbitmul
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs 16
Cell Usage :
# BELS 27
# LUT2 4
# LUT3 2
# LUT4 21
# IO Buffers 16
# IBUF 8
# OBUF 8
=====================================================
Device utilization summary:

Selected Device : 3s100etq144-4

Number of Slices: 16 out of 960 1%
Number of 4 input LUTs: 27 out of 1920 1%
Number of IOs: 16
Number of bonded IOBs: 16 out of 108 14%
=====================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING
INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.
Clock Information:

No clock signals found in this design

Asynchronous Control Signals Information:

No asynchronous control signals found in this design

Timing Summary:

Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 15.953ns
Timing Detail:

All values displayed in nanoseconds (ns)

162
163
OUTPUT WAVEFORM – Bough Wolley Array Multiplier:

OUTPUT WAVEFORM: 8-Bit ALU

164
165
OUTPUT WAVEFORM: UNIVERSAL SHIFT REGISTER

OUTPUT WAVEFORM: (D-FF)

OUTPUT WAVEFORM: (T-FF)

166
167
Synthesis report: Final Report (SR-FF) Synthesis report Final Report(JK-FF)
RTL Top Level Output File Name : ff1.ngr RTL Top Level Output File Name : jkf.ngr
Top Level Output File Name : ff1 Top Level Output File Name : jkf
Output Format : NGC Output Format : NGC
Optimization Goal : Speed Optimization Goal : Speed
Keep Hierarchy : NO Keep Hierarchy : NO
Design Statistics Design Statistics
# IOs 4 # IOs 4
Cell Usage : Cell Usage :
# BELS 1 # BELS 1
# GND 1 # LUT3 1
# FlipFlops/Latches 1 # FlipFlops/Latches 1
# FDSE 1 # FD 1
# Clock Buffers 1 # Clock Buffers 1
# BUFGP 1 # BUFGP 1
# IO Buffers 3 # IO Buffers 3
# IBUF 2 # IBUF 2
# OBUF 1 # OBUF 1
Device utilization summary: Device utilization summary:
Selected Device : 3s400pq208-4 Selected Device : 3s400pq208-4
Number of Slices: 0 out of 3584 0% Number of Slices: 1 out of 3584 0%
Number of Slice Flip Flops: 1 out of 7168 0% Number of Slice Flip Flops: 1 out of 7168 0%
Number of IOs: 4 Number of 4 input LUTs: 1 out of 7168 0%
Number of bonded IOBs: 4 out of 141 2% Number of IOs: 4
IOB Flip Flops: 1 Number of bonded IOBs: 4 out of 141 2%
Number of GCLKs: 1 out of 8 12% Number of GCLKs: 1 out of 8 12%
TIMING REPORT TIMING REPORT
Clock Information: Clock Information:
+ + + + + +
Clock Signal | Clock buffer(FF name) | Load | Clock Signal | Clock buffer(FF name) | Load
+ + + |
clk | BUFGP |1 | -----------------------------------+------------------------+-------+
Timing Summary: clk | BUFGP |1 |
Speed Grade: -4 -----------------------------------+------------------------+-------+
Timing Detail: Timing Summary:
All values displayed in nanoseconds (ns) Speed Grade: -4
Timing Detail:
All values displayed in nanoseconds (ns)

168
169
Synthesis Report(D-FF) Synthesis report(T-FF)
Final Report Final Report
Final Results Final Results
RTL Top Level Output File Name : dflip.ngr RTL Top Level Output File Name : ff3.ngr
Top Level Output File Name : dflip Top Level Output File Name : ff3
Output Format : NGC Output Format : NGC
Optimization Goal : Speed Optimization Goal : Speed
Keep Hierarchy : NO Keep Hierarchy : NO
Design Statistics Design Statistics
# IOs 3 # IOs 3
Cell Usage : Cell Usage :
# FlipFlops/Latches 1 # BELS 1
# FD 1 # INV 1
# Clock Buffers 1 # FlipFlops/Latches 1
# BUFGP 1 # FDE 1
# IO Buffers 2 # Clock Buffers 1
# IBUF 1 # BUFGP 1
# OBUF 1 # IO Buffers 2
Device utilization summary: # IBUF 1
Selected Device : 3s50pq208-4 # OBUF 1
Number of Slices: 0 out of 768 0% Device utilization summary:
Number of Slice Flip Flops: 1 out of 1536 0% Selected Device : 3s400pq208-4
Number of IOs: 3 Number of Slices: 1 out of 3584 0%
Number of bonded IOBs: 3 out of 124 2% Number of Slice Flip Flops: 1 out of 7168 0%
IOB Flip Flops: 1 Number of 4 input LUTs: 1 out of 7168 0%
Number of GCLKs: 1 out of 8 12% Number of IOs: 3
TIMING REPORT Number of bonded IOBs: 3 out of 141 2%
Clock Information: Number of GCLKs: 1 out of 8 12%
+ + + TIMING REPORT
Clock Signal | Clock buffer(FF name) | Load | Clock Information:
+ + + + + +
clk | BUFGP |1 | Clock Signal | Clock buffer(FF name) | Load |
Timing Summary: -----------------------------------+------------------------+-------+
Speed Grade: -4 clk | BUFGP |1 |
Minimum period: No path found -----------------------------------+------------------------+-------+
Minimum input arrival time before clock: 1.825ns Timing Summary:
Maximum output required time after clock: 7.165ns Speed Grade: -4
Maximum combinational path delay: No path found Timing Detail:
Timing Detail: All values displayed in nanoseconds (ns)
All values displayed in nanoseconds(ns).

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SCHEMATIC ENTRY AND SPICE SIMULATION OF CMOS INVERTER

SCHEMATIC DIAGRAM:

OUTPUT:

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Schematic of CMOS NAND:

OUTPUT WAVE: (NAND GATE)

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SCHEMATIC OF AND GATE:

OUTPUT WAVE: (AND GATE)

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SCHEMATIC OF OR GATE:

OUTPUT WAVE: (OR GATE)

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SCHEMATIC OF NOR GATE:

OUTPUT WAVE: NOR GATE

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DIFFERENTIAL AMPLIFIER:

OUTPUT WAVEFORM:

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 4-BIT COUNTER

SCHEMATIC DIAGRAM:

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OUTPUT WAVEFORM: (COUNTER)

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187
SCHEMATIC ENTRY: (Common Source Amplifier)

OUTPUT WAVEFORM:

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189
 SCHEMATIC ENTRY: (Common Drain Amplifier)

OUTPUT WAVEFORM:

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191
 SCHEMATIC ENTRY: (Common Gate Amplifier)

OUTPUT WAVEFORM:

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LAYOUT DIAGRAM: (CMOS INVERTER)

OUTPUT WAVEFORM:

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 OUTPUT WAVEFORM: 8-Bit ALU

LOGIC DIAGRAM:

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 ACCUMULATOR:

WAVEFORM:

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