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Future of dynamic random-access memory as main memory

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 Future of dynamic random-access
memory as main memory
Seong Keun Kim and Mihaela Popovici
Dynamic random-access memory (DRAM) is the main memory in most current computers.
The excellent scalability of DRAM has significantly contributed to the development of modern
computers. However, DRAM technology now faces critical challenges associated with further
scaling toward the ∼10-nm technology node. This scaling will likely end soon because of the
inherent limitations of charge-based memory. Much effort has been dedicated to delaying
this. Novel cell architectures have been designed to reduce the cell area, and new materials
and process technologies have been extensively investigated, especially for dielectrics and
electrodes related to charge storage. In this article, the current issues, recent progress in and
the future of DRAM materials, and fabrication technologies are discussed.

Introduction materials such as Si-based dielectrics (SiO2 and SiNx) and

Dynamic random-access memory (DRAM) has served as the electrodes (poly-Si). This excellent scalability of DRAM has
main memory in modern computers since it was introduced by led to its long-lasting success. Today, much effort is devoted
Intel Corporation in 1972. DRAM is widely used in modern to accelerating the scaling of DRAM cells further to the ∼10-nm
computers owing to characteristics such high-speed operation, technology node2 (Figure 1b).
large integration density, and excellent reliability. DRAM is a charge-based RAM that requires a certain cell
A DRAM cell has a simple structure comprising one capacitance value (∼10 f F/cell) to secure the minimum volt-
capacitor (1C) connected by one transistor (1T) (1T-1C) to age difference detectable by the sense amplifier, regardless
the bit line (the line through which information is written to/ of cell size. The ever-shrinking dimension of the capacitor in
read from the memory cell) (Figure 1a). The access transistor DRAM cells will eventually result in failure to meet this cell
is connected to the word line and acts as a switch. The capaci- capacitance requirement. Hence, advancing capacitor technol-
tor stores each bit of data as a negative or positive electrical ogy is essential for continued scaling of DRAM. The scaling
charge. The memory state is read by sensing the stored charge of the DRAM cells also raises problems in the access tran-
on the capacitor via the bit line, which is set to Vcc/2, (Vcc: sistor. Without major innovations in structure, materials, and
operating voltage of the chip) with the transistor closed. When processing, scaling of DRAM will end soon.
the access transistor is on, the stored charge carriers flow into
the bit line, which changes its potential. This voltage change Transistor technology in DRAM
is detected and amplified by the sense amplifier connected to Unlike the transistor in performance-oriented logic devices,
the bit line. the access transistor in DRAM requires a high ON/OFF cur-
During the past several decades, exponential growth in rent ratio (∼108) to prevent substantial loss of the charges
the number of memory cells per chip has occurred. Perpetual stored in the capacitor and to write the data within a short time
memory cell scaling has been the major strategy for realizing (less than a few tens of a nanosecond). As the DRAM cell
rapid increases in memory density.1 DRAM is amenable to shrinks, obtaining sufficient data retention time becomes more
scaling because of its simple structure, and scaling of DRAM challenging. The increase in the channel doping concentration
down to a ∼100-nm technology node (specific manufacturing with scaling of the feature size results in increased electrical
process and its design rule) is easily achieved with traditional field and junction leakage current. A simple and effective way

Seong Keun Kim, Center for Electronic Materials, Korea Institute of Science and Technology, South Korea; s.k.kim@kist.re.kr
Mihaela Popovici, Semiconductor Technology and Systems Unit, IMEC, Belgium; mihaela.ioana.popovici@imec.be
doi:10.1557/mrs.2018.95

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 Future of dynamic random-access memory as main memory

the DRAM cell (< ∼80-nm technology node)

has resulted in conversion from 8 F2 to 6 F2
cell design architecture with an open bit line,
because the 6 F2 design provides a 25%
improvement in DRAM cell area. However,
the open bit-line architecture is vulnerable to
array noise because of the high bit-line capaci-
tance. A buried word line (Figure 2a), which
is placed below the Si surface, is currently
used to relieve this noise vulnerability.9 A new
4 F2 cell architecture—the most compact cell
structure (Figure 2b) with a vertical pillar
transistor—has also been proposed to facili-
Figure 1. (a) Structure of a 1-transistor-1-capacitor (1T-1C) dynamic random-access
tate further DRAM cell scaling.10 The shift of
memory (DRAM) cell. (b) Timing of DRAM technology nodes reported in the International cell architecture from 6 F2 to 4 F2 results in
Technology Roadmap for Semiconductors (ITRS).1 a 33% cell-area reduction. In the 4 F2 cell
design, the transistor and capacitor lie at every
crosspoint of the word lines and bit lines. The
to overcome this detrimental short-channel effect is to increase vertical pillar transistor is placed on the buried bit line and
the channel length. Three-dimensional (3D) structured tran- beneath the storage node (Figure 2b). This cell design is
sistors such as recess-channel-array transistors (RCATs) highly favorable to lower the bit-line capacitance, due to the
have been used to increase the effective channel length in distinct arrangement of the buried bit line, aside from the
this restricted dimension (Figure 2a).3 Further increase in the capacitor. However, transiting from 6 F2 to 4 F2 DRAM cell
channel length has been achieved by using modified RCAT design is still challenging. For further scaling of DRAM cells,
structures such as sphere-shaped RCAT4 and U-shaped RCAT5 severe technological challenges such as the floating body
(Figure 2a). Below a technology node of ∼50 nm, saddle-fin effect of the channel in the vertical transistor (the channel in
transistors, which combine fin-shaped field-effect transistor the vertical transistor is isolated from the Si substrate), struc-
with a RCAT, have been utilized to obtain superior current- tural vulnerability of the pillar channel, and high resistance of
driving capability and sufficient data retention time.6,7 the bit line remain.
An 8 F2 (where F is the minimum feature size) cell design
architecture with a folded bit-line structure8 has been tradi- Capacitor technology in DRAM
tionally used in DRAM because of reliable operations for the For successful DRAM cell operation, the capacitor in the
cell architecture. However, the demand for further scaling of DRAM cell should meet two requirements—sufficient capaci-
tance (∼10 f  F/cell) and ultralow leakage cur-
rent (Jg < 10–7 A/cm2 at the operating voltage)
irrespective of the cell size. The cell capaci-
tance is expressed by:

A
C = ε0 k , (1)
tphys 

where C, ε0, k, A, and tphys are the capacitance,

vacuum permittivity, dielectric constant, effec-
tive capacitor area, and the physical thickness
of the dielectric layer, respectively. Scaling of
the DRAM cell has continuously reduced the
area allocated to the capacitor in the cell, such
that a 3D structured capacitor is used to obtain
Figure 2. (a) Channel structure evolution of the cell transistor in dynamic random-access the necessary capacitance in the limited area,
memory.4,5,7,9 Transmission electron microscope (TEM) images of (i) RCAT, (ii) S-RCAT, and as shown in Figure 3a.11 The aspect ratio of
(iii) U-RCAT. (iv) (Middle) Schematic of a saddle-fin transistor with TEM cross-section images
of the (left) x- and (right) y-axes of the transistor. (v) Cross-sectional image of a buried word line the capacitor has sharply increased and will
with a saddle-fin channel configuration. (b) (Upper) Layout of a 4 F2 cell and (lower) schematic reach ∼100 shortly because of the aggressive
of a 4 F2 cell with vertical pillar transistor.10 Note: F, minimum feature size; RCAT, recess- scaling of DRAM. However, further increase
channel-array transistor; S-RCAT, sphere-shaped RCAT; U-RCAT, U-shaped RCAT; D, drain;
S, source; BL, bit line; CC, cell capacitor; WL, word line; VPT, vertical pillar transistor. in the aspect ratio is impossible because of the
structural vulnerability of the storage node.

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 Future of dynamic random-access memory as main memory

capacitors to maximize the effective capaci-

tor area. For sub-20-nm technology nodes,
however, the cylindrical structure is no longer
valid and pillar capacitors are utilized because
of their small feature size (F < 20–40 nm)
(Figure 3a). The tphys of the dielectric is strin-
gently limited below ∼5 nm, even in the
pillar structure, because the sum of 2 × tphys,
width of the bottom electrode, and the thick-
ness of the top electrode should not exceed
2 × F (Figure 3b). A new high-k material
for future DRAM capacitors should achieve
both ultralow Jg (10–7 A/cm2 at the operating
voltage) and a low EOT of <0.5 nm at a low
thickness of <5 nm.

Dielectrics in DRAM capacitors

The dielectric layer should be conformally
formed over the 3D capacitor structure.
Figure 3. (a) Summary of dynamic random-access memory (DRAM) capacitor technology A better step coverage is necessary at a lower
evolution.11 (b) Schematic of pillar-type capacitors. (c) Jg at ±1 V as a function tphys and tphys, because the electric field at a thinner layer
EOT (nm) values for SrTiO3 (denoted STO) (●),17,48 and nanolaminates: TiO2/ZrO2/TiO2 can be significantly influenced by even a tiny
(denoted TZT) and TiO2/ZrO2/Al2O3/ZrO2/TiO2 (denoted (TZAZT) (◀ ),49 ZrO2/HfLaO/ZrO2
(denoted Z/HL/Z)(▼) and ZrO2/SrO(or Al2O3)/ZrO2 (ZSrZ or ZAZ) (◆). In the case of
50 20 difference in the tphys. Atomic layer deposition
ATO( ■ )41 and Si:HZO(▲)51 (Si doped Zr60Hf40 oxide), Jg is reported at 0.8 V. ZrO2-based (ALD), known to achieve exceptional step
dielectrics remain the most promising path toward the envisaged EOT-Jg values at ≤5 nm coverage, is appropriate for the growth of
tphys. Note: SIS, silicon–insulator–silicon; MIS, metal–insulator–silicon; MIM, metal–
insulator–metal; ATO, Al-doped TiO2; Jg, leakage current; tphys, physical thickness of the the dielectric layer over the 3D capacitor.
dielectric layer; EOT, equivalent oxide thickness; F, minimum feature size. In addition, ALD can grow high-quality films
at a relatively low temperature. Consequently,
the ALD technique has been extensively used
Thinning of the dielectric layer is also not an eventual solu- for studies on the dielectric in DRAM capacitors.
tion to acquire large capacitance as the electric field applied to DRAM capacitor technology has relied on the ZrO2
the dielectric increases with decreasing tphys, which leads to a dielectric for a decade as it enabled attainment of the 25-nm
significant rise in the Jg. technology node. The trilayer structure of tetragonal (or cubic
Therefore, a higher-k material must be used as the dielectric ZrO2 (k ≈ 40))/amorphous Al2O3 (k ≈ 9)/tetragonal (or cubic
in the DRAM capacitor. The tphys value can be increased to some ZrO2), called ZAZ, in combination with TiN electrodes has
extent owing to the high-k value, reducing the effective electric replaced Hf  O2 for the capacitors required for the ≤45-nm tech-
field at the operating voltage. The figure of merit used by DRAM nology node.21 Nevertheless, it is generally agreed that a Jg of
capacitor technology is the electrical performance of the dielec- 10–7 A/cm2 at ±1 V cannot be maintained with the ZAZ nano-
tric material as compared to SiO2, known as the equivalent oxide laminate stack for a sub-20-nm technology node with smaller
thickness (EOT). The EOT of the dielectric is given by: surface areas that involves reducing tphys of the dielectric.2
Robertson22 showed that the k of oxides tends to vary
3.9 × tphys inversely with the bandgap, which limits the choice of high-
EOT = , (2)
k  k oxides to several candidates comprising TiO2 and SrTiO3.
Their bandgap is rather small (3.2–3.3 eV); however, their
where 3.9 is the dielectric constant of SiO2. In the last decade, k values are more than 100. Although the allowable cation
extensive investigations have focused on identifying high-k nonstoichiometry range of bulk SrTiO3 is narrow and off-
dielectrics in conjunction with specific metal electrodes to stoichiometric SrTiO3 thin films usually show decreased
reduce the EOT value.11–20 k value, its perovskite structure could be maintained in a rea-
DRAM capacitor technology is more seriously challenged sonable range of Sr:Ti ratios around stoichiometric SrTiO3.14,23
than ever. Sub-20-nm DRAM technology nodes require a low Significant efforts have been devoted to the development of
EOT value of <0.5 nm, which is difficult to achieve. A signifi- SrTiO314,16,17,23–33 and TiO212,13,18,34,35 by ALD. High-k values of
cant challenge is the limit in tphys of the dielectric and electrode SrTiO3 while preserving low Jg could be achieved by control-
layers. For >40-nm technology nodes, the lateral size of the ling the stoichiometry (Sr enrichment)16,17 or the grain size.27,30
capacitor is incomparably larger than the tphys of the layers. TiO2 crystallizes as anatase (k ≈ 40) or rutile (k ≈ 80)
This large technology node enables the use of cylindrical phases. Rutile, a high-temperature phase,36 is incompatible

336
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 Future of dynamic random-access memory as main memory

with the thermal budget required in the DRAM fabrication relatively high work function (∼4.8 eV), and the ease with
process (<600°C). However, when grown on RuO2 conduc- which Ru can be dry etched is also advantageous for pat-
tive oxide, rutile TiO2 phase with similar lattice parameters terning the electrodes. The use of Ru as the electrode has
crystallizes at deposition temperatures (i.e., 250°C) owing to shown possibilities of lowering Jg.54–56 Forming a continu-
the template effect displayed by the substrate,12,13,37,38 thus ous and smooth Ru layer on oxides at a low Ru thickness
reducing both the EOT and Jg.12,15,34 Nevertheless, the scalabil- of <5 nm is difficult because of its high surface energy.
ity of tphys is limited to 10–12 nm. Doping TiO2 with Al11,39–42 Morphological issues such as blisters, which often occur
could further reduce Jg, leading to further reduction in tphys to on ALD Ru on oxides, must also be addressed for electrode
∼7 nm.39,41 application of Ru.57
A doping approach could also be considered for other Conducting oxides such as RuO2 and SrRuO3 have also
dielectrics (e.g., HfO2 and ZrO2). Dopants with lower elec- attracted attention as potential electrodes. The work func-
tronegativities and larger ionic radii than those correspond- tion of RuO2 and SrRuO3 is even higher than that of Ru,
ing to the host oxide led to higher-k and a reduction of Jg which is favorable for low Jg. In particular, the structural
for HfO243–45 and ZrO2.46,47 Higher symmetry phases are coherency with promising high-k materials (e.g., rutile
formed via doping (such as tetragonal or cubic) leading to TiO2/RuO213,58,59 and SrTiO3/SrRuO360,61) provides concur-
larger k, while the lower Jg was attributed to the shift of the rent decreases in EOT and Jg. However, these conducting
charge states of the oxygen vacancies into the conduction oxides have not yet been practically used in DRAM capaci-
bands.47 tors. Those Ru-containing oxides are easily reduced during
As previously described, continued downscaling of DRAM the back-end process, because of the weak bonding between
technology toward the sub-20-nm technology node will require ruthenium and oxygen. Ta-doped SnO2 has recently been sug-
a low tphys of ≤5 nm. At such a low thickness, other character- gested as a reduction-resistant oxide electrode for DRAM
istics of the capacitors become important, including electrode capacitors.62 Capacitors composed of rutile TiO2/Ta-doped
and dielectric surface roughness, lattice mismatch, and chemi- SnO2 stack showed both excellent dielectric properties and
cal compatibility of electrode/dielectric. A summary of the thermal stability in experiments.
lowest EOT – Jg – tphys at ±1 V for ALD dielectrics is given
in Figure 3c.17,20,41,48–51 This shows that the nanolaminates’ Summary and outlook
approach combining a high bandgap with a high-k dielectric DRAM is the representative memory used in modern com-
leads to the lowest Jg when thinning the dielectric. However, puters, but it appears to be facing serious challenges for
for tphys ≤ 5 nm, the nanolaminate approach is less likely to be further scaling toward the ∼10-nm technology node. Much
an option because of intermixing of the layers under the thermal effort has been dedicated to prolonging its scaling. Structural
budget applied to the capacitor. modification of cell transistors has been attempted to suppress
Comprehensive ab initio calculations of the bandgap and Jg and lower the bit-line capacitance. Transition of the cell
k52 (namely the generalized gradient approximation for band- architecture to 4 F2 has also been suggested for further DRAM
gap and local density approximation for k) showed that cubic scaling. To satisfy the stringent requirements of capacitors in
BeO can display the highest-k (∼300) and bandgap values ∼10-nm technology nodes, new higher-k dielectrics and elec-
(>9 eV). However, the cubic rock-salt structure of BeO is a trodes have been extensively investigated. Although high-k
high-pressure phase; therefore, stabilization under ambient oxides such as TiO2 and SrTiO3 show potential for further
conditions is required. Efforts are being devoted to depositing scaling of DRAM, their large Jg has to be resolved at a low
a high-bandgap BeO by ALD;53 however, no high-k material thickness of <5 nm. A new dielectric material with both large
has yet been achieved. bandgap (over ∼5 eV) and large k (>50) should be designed
for the ∼10-nm technology node. Otherwise, downscaling
Electrodes in DRAM capacitor of DRAM might end at approximately the 15-nm technol-
Further reduction in Jg can also be attained by electrode ogy node.
engineering. The electrode in a DRAM capacitor should Although the scaling of DRAM will eventually end, DRAM
have a high work function and a sharp interface between might maintain its status as the main memory for a long
the electrode and dielectric for better dielectric perfor- time. The market for infrastructure such as servers, stor-
mance. TiN, grown by ALD using TiCl4 and NH3, currently age, and networking continues to grow rapidly. Bandwidth
functions as the electrode in DRAM capacitors. However, is the major challenge of DRAM for those applications.
the work function of TiN is insufficient to suppress Jg at the Although die stacking with conventional wire bonding has
thin dielectric thickness required in the ∼10-nm technol- limited data-transfer rates, the emergence of high-bandwidth
ogy node. Therefore, much effort has also been devoted to memory (HBM) through-silicon-via technology shows great
developing new electrodes, including noble metal and con- promise with much improved data rates and reduced power
ducting oxide electrodes. Among noble metals, ruthenium consumption. Die stacking of DRAM in the form of HBM
(Ru) is considered the most promising for DRAM capacitor could be the future of this long-standing main memory, fol-
electrodes. Ru is favorable for suppressing Jg because of its lowing the end of DRAM scaling.

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 Future of dynamic random-access memory as main memory

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338
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 Future of dynamic random-access memory as main memory

61. D. Popescu, B. Popescu, G. Jegert, S. Schmelzer, U. Boettger, P. Lugli, IEEE Mihaela Popovici has been a senior researcher
Trans. Electron Devices 61, 2130 (2014). in the Semiconductor Technology and Sys-
62. C.J. Cho, M.-S. Noh, W.C. Lee, C.H. An, C.-Y. Kang, C.S. Hwang, S.K. Kim, tems Unit at IMEC, Belgium, since 2007. She
J. Mater. Chem. C 5, 9405 (2017).  received her BSc and MSc degrees in chemi-
cal engineering and her PhD degree in materials
science and engineering in 2004 at Politehnica
University of Timisoara, Romania. She com-
pleted postdoctoral research at Philips Research,
Seong Keun Kim has been a principal researcher The Netherlands, in the Photonic Materials
in the Center for Electronic Materials at the and Devices Department. Her research focuses
Korea Institute of Science and Technology, on dielectric oxides and metal thin-film devel-
South Korea, since 2012. He received his BSc opment, physical and electrical characteriza-
degree in 2001 and PhD degree in 2007, both in tion, and design of complex materials stacks
materials science and engineering from Seoul with applications in microelectronic electronic
National University, South Korea. From 2007 to devices. She has an h-index of 15. Popovici can be reached by email at
2009, he worked as an Alexander von Humboldt mihaela.ioana.popovici@imec.be.
Research Fellow at Forschungszentrum Jülich,
Germany. In 2010, he joined Argonne National
Laboratory as a postdoctoral researcher. His
current research interests include high-k dielec-
trics and novel electrodes, atomic layer deposi-
tion of those materials, and thin-film transistors
utilizing oxides and two-dimensional metal chalcogenides. He has published
more than 120 papers. Kim can be reached by email at s.k.kim@kist.re.kr.

Calling all Early-Stage Materials Innovators!

2018
iMatSci How to Participate
To participate, innovators should be:
Innovation • Interested in commercializing their
technologies
Showcase November 25–30, 2018 | Boston, Massachusetts
• Able to propose a value proposition for their
technologies
• Able to effectively demonstrate the
Interested in being a part of iMatSci this year? commercial applications of their technologies

Submission Site Opens: June 1, 2018 • Actively seeking partners, funding and/or
paths for commercialization
The iMatSci Innovation Showcase at the 2018 MRS Fall Meeting will provide a platform for
technology leaders at universities, research labs and start-up companies to demonstrate the Online applications will be accepted
through August 1, 2018, and must be
practical applications of their innovative, materials-based technologies.
submitted through the iMatSci portal at
Each innovator will be provided with exhibit space at the Hynes Convention Center to present www.mrs.org/fall-2018-imatsci-submission
his/her technology or product using various forms of media such as tabletop demonstrations, For further information about submission
videos and prototypes. Demonstrations will be judged by experienced technology investors and guidelines, innovator packages, selection
industry professionals. criteria, sponsorship opportunities and more,
check out the complete iMatSci webpage.
By participating in iMatSci, innovators will be granted access to:
www.mrs.org/imatsci
• A full day of workshops, seminars and panel discussions, with topics specifically targeted
at the success of early-stage innovators
For more information or to
• One-on-one meeting space for interaction with potential partners, investors and collaborators
become a sponsor, please contact:
• Exclusive networking events, Q&A sessions and receptions
Natalie Larocco
• Exhibit Space to showcase and pitch their innovations to investors, strategic partners and Materials Research Society
industry technology scouts larocco@mrs.org
• And more! 724.779.2744

Connecting People and Ideas

“My experience at iMatSci was invaluable. Few opportunities can match what iMatSci provides by allowing
innovators to meet with other entrepreneurs to discuss their technology, pathways for funding, and strategies for
www.mrs.org/imatsci
commercialization. It was a richly stimulating experience.”
C. Wyatt Shields, IV iMatSci Innovator, Encapsio LLC;
Research Triangle, MRSEC Fellow

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