Combinational Logic Circuits

1- INTRODUCTION

The digital system consists of two types of circuits, namely:

- Combinational circuits
- Sequential circuits

A combinational circuit consists of logic gates, where outputs are at any instant and are
determined only by the present combination of inputs without regard to previous inputs or the
previous state of outputs. A combinational circuit performs a specific information-processing
operation assigned logically by a set of Boolean functions. Sequential circuits contain logic
gates as well as memory cells. Their outputs depend on the present inputs and also on the states
of memory elements. Since the outputs of sequential circuits depend not only on the present
inputs but also on past inputs, the circuit behavior must be specified by a time sequence of
inputs and memory states.

2- Binary Adder
The most basic arithmetic operation is addition. The circuit, which performs the addition
of two binary numbers is known as Binary adder. First, let us implement an adder, which
performs the addition of two bits.

- Half Adder: Half adder is a combinational circuit, which performs the addition of two
binary numbers A and B are of single bit. It produces two outputs sum, S & carry, C.
The Truth table of Half adder is shown below.

Inputs Outputs

A B C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

When we do the addition of two bits, the result sum can have the values ranging from 0 to 2 in
decimal. We can represent the decimal digits 0 and 1 with single bit in binary. But, we can’t
represent decimal digit 2 with single bit in binary. So, we require two bits for representing it in
binary.
Let, sum, S is the Least significant bit and carry, C is the Most significant bit of the result sum.
For first three combinations of inputs, carry, C is zero and the value of S will be either zero or one
based on the number of ones present at the inputs. But, for last combination of inputs, carry, C is
one and sum, S is zero, since the result sum is two.
From Truth table, we can directly write the Boolean functions for each output as
S=A⊕B, C=AB
We can implement the above functions with 2-input Ex-OR gate & 2-input AND gate. The circuit
diagram of Half adder is shown in the following figure.

In the above circuit, a two input Ex-OR gate & two input AND gate produces sum, S & carry, C
respectively. Therefore, Half-adder performs the addition of two bits.
- Full Adder
Full adder is a combinational circuit, which performs the addition of three bits A, B and
Cin. Where, A & B are the two parallel significant bits and Cin is the carry bit, which is
generated from the previous stage. This Full adder also produces two outputs sum, S &
carry, Cout, which are similar to Half adder. The Truth table of Full adder is shown below.

Inputs Outputs

A B Cin Cout S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

When we do the addition of three bits, the resultant sum can have the values ranging from 0 to 3
in decimal. We can represent the decimal digits 0 and 1 with single bit in binary. But, we can’t
represent the decimal digits 2 and 3 with single bit in binary. So, we require two bits for
representing those two decimal digits in binary.
Let, sum, S is the Least significant bit and carry, C out is the Most significant bit of resultant sum.
It is easy to fill the values of outputs for all combinations of inputs in the truth table. Just count
the number of ones present at the inputs and write the equivalent binary number at outputs. If
Cin is equal to zero, then Full adder truth table is same as that of Half adder truth table.
We will get the following Boolean functions for each output after simplification.
S=A⊕B⊕Cin
cout=AB+(A⊕B)cin
The sum, S is equal to one, when odd number of ones present at the inputs. We know that Ex-OR
gate produces an output, which is an odd function. So, we can use either two 2input Ex-OR gates
or one 3-input Ex-OR gate in order to produce sum, S. We can implement carry, C out using two 2-
input AND gates & one OR gate. The circuit diagram of Full adder is shown in the following
figure.

This adder is called as Full adder because for implementing one Full adder, we require two Half
adders and one OR gate. If Cin is zero, then Full adder becomes Half adder. We can verify it easily
from the above circuit diagram or from the Boolean functions of outputs of Full adder.
4-bit Binary Adder
The 4-bit binary adder performs the addition of two 4-bit numbers. Let the 4-bit binary
numbers, A=A3A2A1A0 and B=B3B2B1B0. We can implement 4-bit binary adder in one of the
two following ways.
 Use one Half adder for doing the addition of two Least significant bits and three
Full adders for doing the addition of three higher significant bits.
 Use four Full adders for uniformity. Since, initial carry C in is zero, the Full adder
which is used for adding the least significant bits becomes Half adder.
For the time being, we considered second approach. The block diagram of 4-bit binary adder is
shown in the following figure.

Here, the 4 Full adders are cascaded. Each Full adder is getting the respective bits of two parallel
inputs A & B. The carry output of one Full adder will be the carry input of subsequent higher order
Full adder. This 4-bit binary adder produces the resultant sum having at most 5 bits. So, carry out
of last stage Full adder will be the MSB.
In this way, we can implement any higher order binary adder just by cascading the required number
of Full adders. This binary adder is also called as ripple carry binary adder because the carry
propagates ripples from one stage to the next stage.

- Binary Subtractor
The circuit, which performs the subtraction of two binary numbers is known as Binary
subtractor. We can implement Binary subtractor in following two methods.

 Cascade Full subtractors

 2’s complement method
In first method, we will get an n-bit binary subtractor by cascading ‘n’ Full
subtractors. So, first you can implement Half subtractor and Full subtractor, similar to
Half adder & Full adder. Then, you can implement an n-bit binary subtractor, by
cascading ‘n’ Full subtractors. So, we will be having two separate circuits for binary
addition and subtraction of two binary numbers.
In second method, we can use same binary adder for subtracting two binary numbers
just by doing some modifications in the second input. So, internally binary addition
operation takes place but, the output is resultant subtraction. We know that the
subtraction of two binary numbers A & B can be written as,
A−B=A+(2′scomplimentofB) ⇒A−B=A+(1′scomplimentofB)+1⇒

- 4-bit Binary Subtractor:

 The 4-bit binary subtractor produces the subtraction of two 4-bit numbers. Let the 4bit
binary numbers, A=A3A2A1A0 and B=B3B2B1B0. Internally, the operation of 4-bit
Binary subtractor is similar to that of 4-bit Binary adder. If the normal bits of binary number
A, complemented bits of binary number B and initial carry borrow, C in as one are applied
to 4-bit Binary adder, then it becomes 4-bit Binary subtractor. The block diagram of 4-bit
binary subtractor is shown in the following figure.

This 4-bit binary subtractor produces an output, which is having at most 5 bits. If Binary number
A is greater than Binary number B, then MSB of the output is zero and the remaining bits hold the
magnitude of A-B. If Binary number A is less than Binary number B, then MSB of the output is
one. So, take the 2’s complement of output in order to get the magnitude of A-B.
In this way, we can implement any higher order binary subtractor just by cascading the required
number of Full adders with necessary modifications.

- Binary Adder / Subtractor

The circuit, which can be used to perform either addition or subtraction of two binary numbers at
any time is known as Binary Adder / subtractor. Both, Binary adder and Binary subtractor
contain a set of Full adders, which are cascaded. The input bits of binary number A are directly
applied in both Binary adder and Binary subtractor.
There are two differences in the inputs of Full adders that are present in Binary adder and Binary
subtractor.
 The input bits of binary number B are directly applied to Full adders in Binary adder,
whereas the complemented bits of binary number B are applied to Full adders in
Binary subtractor.
 The initial carry, C0 = 0 is applied in 4-bit Binary adder, whereas the initial
carry borrow, C0 = 1 is applied in 4-bit Binary subtractor. We know that a 2-input
Ex-OR gate produces an output, which is same as that of first input when other
input is zero. Similarly, it produces an output, which is complement of first input
when other input is one. Therefore, we can apply the input bits of binary number B,
to 2-input Ex-OR gates. The other input to all these Ex-OR gates is C 0. So, based
 on the value of C0, the Ex-OR gates produce either the normal or complemented
bits of binary number B.

- 4-bit Binary Adder / Subtractor

The 4-bit binary adder / subtractor produces either the addition or the subtraction of two 4-
bit numbers based on the value of initial carry or borrow, 𝐶0. Let the 4-bit binary
numbers, A=A3A2A1A0 and B=B3B2B1B0. The operation of 4-bit Binary adder /
subtractor is similar to that of 4-bit Binary adder and 4-bit Binary subtractor. Apply the
normal bits of binary numbers A and B & initial carry or borrow, C 0 from externally to a
4-bit binary adder. The block diagram of 4-bit binary adder / subtractor is shown in the
following figure.

If initial carry, 𝐶0 is zero, then each full adder gets the normal bits of binary numbers A & B. So,
the 4-bit binary adder / subtractor produces an output, which is the addition of two binary
numbers A & B. If initial borrow, 𝐶0 is one, then each full adder gets the normal bits of binary
number A & complemented bits of binary number B. So, the 4-bit binary adder / subtractor
produces an output, which is the subtraction of two binary numbers A & B.
Therefore, with the help of additional Ex-OR gates, the same circuit can be used for both addition
and subtraction of two binary numbers.
- Comparator is one of the useful combinational logic networks and has wide
applications. It compares two binary numbers and determines if one number is greater
than, less than, or equal to the other number. It is a multiple output combinational logic
circuit. If two binary numbers are considered as A and B, the magnitude comparator
gives three outputs for A > B, A < B, and A = B. For comparison of two n-bit numbers,
the classical method to achieve the Boolean expressions requires a truth table of 22n
entries and becomes too lengthy and cumbersome. It is also desired to have a digital
circuit possessing with a certain amount of regularity, so that similar circuits can be
applied for the comparison of any number of bits. Digital functions that follow an
inherent well-defined regularity can usually be developed by means of algorithmic
procedure if it exists. An algorithm is a process that follows a finite set of steps to arrive
at the solution to a problem. A method is illustrated here by deriving an algorithm to
design a 4-bit magnitude comparator. The algorithm is the direct application of the
procedure to compare the relative magnitudes of two binary numbers. Let us consider the
two binary numbers A and B are expanded in terms of bits in descending order as A = A4
A3 A2 A1 B = B4 B3 B2 B1 , where each subscripted letter represents one of the digits
in the number. It is observed from the bit contents of the two numbers that A = B when
A4 = B4 , A3 = B3 , A2 = B2 , and A1 = B1 . As the numbers are binary they possess the
value of either 1 or 0, the equality relation of each pair can be expressed logically by the
equivalence function as Xi = Ai Bi + Ai ′Bi ′ for i = 1, 2, 3, 4. Or, Xi = (A⊕B)′. Or, Xi ′
= A ⊕ B. Or, Xi = (Ai Bi ′ + Ai ′Bi )′. Xi is logic 1 when both Ai and Bi are equal i.e.,
either 1 or 0 at the same instant. To satisfy the equality condition of two numbers A and
B, it is necessary that all Xi must be equal to logic 1. This dictates the AND operation of
all Xi variables. In other words, we can write the Boolean expression for two equal 4-bit
numbers F (A = B) = X4 X3 X2 X1. To determine the relative magnitude of two numbers
A and B, the relative magnitudes of pairs of significant bits are inspected from the most
significant position. If the two digits of the most significant position are equal, the next
significant pair of digits are compared. The comparison process is continued until a pair
of unequal digits is found. It may be concluded that A>B, if the corresponding digit of A
is 1 and B is 0. On the other hand, AB) = A4 B4 ′ +X4 A3 B3 ′ +X4 X3 A2 B2 ′ +X4 X3
X2 A1 B1 ′ and F. This is a multilevel implementation and you may notice that the circuit
maintains a regular pattern. Therefore, an expansion of binary magnitude comparator of
higher bits can be easily obtained.
Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2 n output
lines. One of these outputs will be active High based on the combination of inputs
present, when the decoder is enabled. That means decoder detects a particular code.
The outputs of the decoder are nothing but the min terms of ‘n’ input variables lines,
when it is enabled.

2 to 4 Decoder
Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 & Y0. The block
diagram of 2 to 4 decoder is shown in the following figure.
One of these four outputs will be ‘1’ for each combination of inputs when enable, E is
‘1’. The Truth table of 2 to 4 decoder is shown below.

Enable Inputs Outputs

E A1 A0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

From Truth table, we can write the Boolean functions for each output as

Y3=E.A1.A0
Y2=E.A1.A0′
Y1=E.A1′.A0
Y0=E.A1′.A0′
Each output is having one product term. So, there are four product terms in total. We
can implement these four product terms by using four AND gates having three inputs
each & two inverters. The circuit diagram of 2 to 4 decoder is shown in the following
figure.
Therefore, the outputs of 2 to 4 decoder are nothing but the min terms of two input
variables A1 & A0, when enable, E is equal to one. If enable, E is zero, then all the
outputs of decoder will be equal to zero.
Similarly, 3 to 8 decoder produces eight min terms of three input variables A 2, A1 &
A0 and 4 to 16 decoder produces sixteen min terms of four input variables A 3, A2, A1 &
A0 .

Implementation of Higher-order Decoders

Now, let us implement the following two higher-order decoders using lower-order
decoders.

 3 to 8 decoder
 4 to 16 decoder
3 to 8 Decoder
In this section, let us implement 3 to 8 decoder using 2 to 4 decoders. We know that
2 to 4 Decoder has two inputs, A1 & A0 and four outputs, Y3 to Y0. Whereas, 3 to 8
Decoder has three inputs A2, A1 & A0 and eight outputs, Y7 to Y0.
We can find the number of lower order decoders required for implementing higher
order decoder using the following formula.

Required number of lower order decoders=m2/m1

Where,

m1 is the number of outputs of lower order decoder.

m2 is the number of outputs of higher order decoder.
Here, m1 = 4 and m2= 8. Substitute, these two values in the above formula.
Requirednumberof2to4decoders=8/4=2
Therefore, we require two 2 to 4 decoders for implementing one 3 to 8 decoder.
The block diagram of 3 to 8 decoder using 2 to 4 decoders is shown in the following
figure.

The parallel inputs A1 & A0 are applied to each 2 to 4 decoder. The complement of
input A2 is connected to Enable, E of lower 2 to 4 decoder in order to get the outputs,
Y3 to Y0. These are the lower four min terms. The input, A2 is directly connected to
Enable, E of upper 2 to 4 decoder in order to get the outputs, Y 7 to Y4. These are
the higher four min terms.

4 to 16 Decoder
In this section, let us implement 4 to 16 decoder using 3 to 8 decoders. We know that
3 to 8 Decoder has three inputs A2, A1 & A0 and eight outputs, Y7 to Y0. Whereas, 4 to
16 Decoder has four inputs A3, A2, A1 & A0 and sixteen outputs, Y15 to Y0
We know the following formula for finding the number of lower order decoders
required.

Required number of lower order decoders=m2/m1

Substitute, m1 = 8 and m2 = 16 in the above formula.
Required number of 3to8 decoders=16/ 8=2
Therefore, we require two 3 to 8 decoders for implementing one 4 to 16 decoder.
The block diagram of 4 to 16 decoder using 3 to 8 decoders is shown in the following
figure.
The parallel inputs A2, A1 & A0 are applied to each 3 to 8 decoder. The complement of
input, A3 is connected to Enable, E of lower 3 to 8 decoder in order to get the outputs,
Y7 to Y0. These are the lower eight min terms. The input, A3 is directly connected to
Enable, E of upper 3 to 8 decoder in order to get the outputs, Y 15 to Y8. These are
the higher eight min terms.
 College of Information Technology / Software Department
Lec. 10
Logic Design / First Class / 2018-2019

Decoders & Encoders

Decoder
In a digital system, discrete quantities of information are represented with binary codes. A
binary code of n bits can represent up to 2n distinct elements of the coded information. A decoder is a
combinational circuit that converts n bits of binary information of input lines to a maximum of
2n unique output lines. Usually decoders are designated as an n to m lines decoder, where n is the
number of input lines and m (=2n) is the number of output lines.
Decoders have a wide variety of applications in digital systems such as data demultiplexing, digital
display, digital to analog converting, memory addressing, etc. A 3-to-8 line decoder is illustrated in
Figure 1.

Figure (1)

04
The 3-to-8 line decoder consists of three input variables and eight output lines. Note that each of the
output lines represents one of the minterms generated from three variables. The internal combinational
circuit is realized with the help of INVERTER gates and AND gates. The operation of the decoder
circuit may be further illustrated from the input output relationship as given in the above table. Note
that the output variables are mutually exclusive to each other, as only one output is possible to be logic
1 at any one time.

Some Applications of Decoders

As we have seen that decoders give multiple outputs equivalent to the minterms corresponding
to the input variables, it is obvious that any Boolean expression in the sum of the products form can be
very easily implemented with the help of decoders. It is not necessary to obtain the minimized
expression through simplifying procedures like a Karnaugh map, or tabulation method, or any other
procedure. It is sufficient to inspect the minterm contents of a function from the truth table, or the
canonical form of sum of the products of a Boolean expression and selected minterms obtained from
the output lines of a decoder may be simply OR-gated to derive the required function. The following
examples will demonstrate this.

Example 1. Implement the function F (A,B,C) = Σ (1,3,5,6).

Solution. Since the above function has three input variables, a 3-to-8 line decoder may be employed. It
is in the sum of the products of the minterms m1, m3, m5, and m6, and so decoder output D1, D3, D5,
and D6 may be OR-gated to achieve the desired function. The combinational circuit of the above
functions is shown in Figure 2.

Figure (2)

Example 2. Design a full adder circuit with decoder IC.

Solution. We have seen earlier that full adder circuits are implemented with logic gates. This can be
very easily implemented with the help of a decoder IC. If we observe the truth table of a full adder. In
respect to minterms, the Boolean expression of sum output S and carry output C can be written as:
S = X′A′B + X′AB′ + XA′B′ + XAB and C = X′AB + XA′B + XAB′ + XAB.

04
The above expression can be realized in Figure 3.

Figure (3)

Encoders
An encoder is a combinational network that performs the reverse operation of the decoder. An
encoder has 2n or less numbers of inputs and n output lines. The output lines of an encoder generate the
binary code for the 2n input variables. Figure 4 illustrates an eight inputs/three outputs encoder. It may
also be referred to as an octal-to-binary encoder where binary codes are generated at outputs according
to the input conditions. The truth table is given bellow.

04
 The encoder in Figure 4 assumes that only one input line is activated to logic 1 at any particular
time, otherwise the other circuit has no meaning. It may be noted that for eight inputs there are a
possible 28 = 256 combinations, but only eight input combinations are useful and the rest are don’t-care
conditions. It may also be noted that D0 input is not connected to any of the gates. All the binary
outputs A, B, and C must be all 0s in this case. All 0s output may also be obtained if all input variables
D0 to D7 are logic 0. This is the main discrepancy of this circuit. This discrepancy can be eliminated by
introducing another output indicating the fact that all the inputs are not logic 0.

However, this type of encoder is not available in an IC package because it is not easy to implement
with OR gates and not much of the gates are used. The type of encoder available in IC package is
called a priority encoder. These encoders establish an input priority to ensure that only highest priority
input is encoded. As an example, if both D2 and D4 inputs are logic 1 simultaneously, then output will
be according to D4 only i.e., output is 100.

04
Objectives:
1. Multiplexers:
a. 4-to-1 Multiplexers.
b. Design of 8:1 Multiplexers.
2. Demultiplexers.
3. Encoders.
4. Examples.
1. Multiplexers

 A Multiplexers (MUX) is a combinational logic component that has several

inputs and only one output.
 MUX directs one of the inputs to its output line by using a control bit word
(selection line) to its select lines.
 Multiplexer contains the followings:
o data inputs
o selection inputs
o a single output
o Selection input determines the input that should be connected to the
output.
 The multiplexer sometime is called data selector.
 The multiplexer acts like an electronic switch that selects one from
different.
 A multiplexer may have an enable input to control the operation of the
unit.
 a) 4-to-1 Multiplexers
 4-data input MUX
 , - Select lines.
 , , , - Input lines.
 - Single output line.

Select Select lines

Output S1
lines S 0

S 1
S 0
0 0
P0
0 0 0 1
1 0
0 1 P1 1 1
P2 F
1 0 Output
P3
1 1 MUX

MUX implementation

S1 s 1 s0 s0
Select

P0 S0 0 MUX
S1 1 G 0

P1 P0 3

F
Input

P1 Output
F P2
P2 P3

4:1 MUX module

P3 "digital element"

Internal logic circuit for 4-1 MUX

b) Design of a 8:1 multiplexer

 How to construct a 8:1 MUX from two 4:1 MUX.
 and are the two output lines of two 4:1 MUX
Select

Select
S0 0 S0 0
S1 1 S1 1
M M
P0 U P0 U
X X X X
Input

Input
1 2
P1 1 P1 2
P2 P2
P3 P3

S2 0 M
U
X1 X F  S2 X 1  S2 X 2
3
X2

S0 0
S1 1 M
P0 U
X
P1 1
P2 S2
P3 M
U
0
X F
S0 0 3
S1 1 M
1
P U
4
X
P5 2
P6
P7

Design for a 8:1 MUX network

 2. Demultiplexers
 The demultiplexer is a combinational logic circuit that performs the
reverse operation of multiplexer (Several output lines, one input
line).
S 1
S 0
Select lines 0 0
S1 S 0 0 1
1 0
1 1
P0

Outputs
Input

P1
X
P2

P3
MUX

S1 s1 s0 s0

P0  X

P1  X

P2  X

X P3  X
Internal logic circuit for 1-4
DEMUX

Explain:

X
C F  X When C  1
inputs Output
Two select lines four outputs

0 0 0
0 1 0
1 0 0
1 1 1
 3. Encoders

 An encoder is a digital circuit that performs the inverse operation of

a decoder.
 An encoder has (or fewer) input lines and output lines.
 The encoder can be implemented with OR gate whose inputs are
determined directly from the truth table.

Inputs Outputs

1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
 Output is equal to 1 when the input digit is 4, 5, 6 or 7.
 Output is equal to 1 when the input digit is 2, 3, 6 or 7.
 Output is equal to 1 when the input digit is 1, 3, 5 or 7.

 We need three OR gates.

D0 D1 D2 D3 D4 D5 D6 D7

X
 4. Examples
4.1) Active-low decoder:
 So we can use active-low decoders to implement arbitrary functions
too, but as a product of maxterms.
 For example, the implementation of the function

Using an active-low decoder is:

 The “ground” symbol connected to EN represents logical 0, so this

decoder is always enabled.
 Remember that you need an AND gate for a product of sums.
4.2) Implement the following combinational functions using active-
high decoder.

Solution:
4.3) A certain logic circuit has four inputs A, B, C, and D. The output
X of the circuit is logic 1 if two or more inputs are logic 1.
a) Write the truth table for this circuit.
Solution:

A B C D X
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
b) Implement the function using one decoder with active low output.
A B C D X Maxterm
0 0 0 0 0 M 0  A  B C  D
0 0 0 1 0 M 1  A  B C  D
0 0 1 0 0 M 2  A  B C  D
0 0 1 1 1
0 1 0 0 0 M 4  A  B C  D
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0 M 8  A  B C  D
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
 X ( A , B ,C , D )    M 0 , M 1 , M 2 , M 4 , M 8 

4.4) Implement the logic function f using a single multiplexer;

assume that the inputs and their complements are available at the
input of the multiplexer.

f  x , y , z     2,3, 4, 7 
Solution:
x y z f
0 0 0 1
I0
0 0 1 1
0 1 0 0
I1
0 1 1 0
1 0 0 0
I2
1 0 1 1
1 1 0 1
I3
1 1 1 0
4.5) The following figure shows a 4-input multiplexer connected to
implement a function F of three Boolean variables A, B, C.

B 0 MUX 0
G
3
C 1

0 0
1 1
A 2
0 3

Complete the following truth table:

Logical
Output
Inputs
A B C F
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2 n output
lines. One of these outputs will be active High based on the combination of inputs
present, when the decoder is enabled. That means decoder detects a particular code.
The outputs of the decoder are nothing but the min terms of ‘n’ input variables lines,
when it is enabled.

2 to 4 Decoder
Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 & Y0. The block
diagram of 2 to 4 decoder is shown in the following figure.

One of these four outputs will be ‘1’ for each combination of inputs when enable, E is
‘1’. The Truth table of 2 to 4 decoder is shown below.

Enable Inputs Outputs

E A1 A0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

From Truth table, we can write the Boolean functions for each output as

Y3=E.A1.A0
Y2=E.A1.A0′
 Y1=E.A1′.A0
Y0=E.A1′.A0′
Each output is having one product term. So, there are four product terms in total. We
can implement these four product terms by using four AND gates having three inputs
each & two inverters. The circuit diagram of 2 to 4 decoder is shown in the following
figure.

Therefore, the outputs of 2 to 4 decoder are nothing but the min terms of two input
variables A1 & A0, when enable, E is equal to one. If enable, E is zero, then all the outputs
of decoder will be equal to zero.
Similarly, 3 to 8 decoder produces eight min terms of three input variables A 2, A1 &
A0 and 4 to 16 decoder produces sixteen min terms of four input variables A 3, A2, A1 &
A0 .

Implementation of Higher-order Decoders

Now, let us implement the following two higher-order decoders using lower-order
decoders.

 3 to 8 decoder
 4 to 16 decoder
3 to 8 Decoder
In this section, let us implement 3 to 8 decoder using 2 to 4 decoders. We know that 2
to 4 Decoder has two inputs, A1 & A0 and four outputs, Y3 to Y0. Whereas, 3 to 8 Decoder
has three inputs A2, A1 & A0 and eight outputs, Y7 to Y0.
We can find the number of lower order decoders required for implementing higher order
decoder using the following formula.
 Required number of lower order decoders=m2/m1
Where,

m1 is the number of outputs of lower order decoder.

m2 is the number of outputs of higher order decoder.
Here, m1 = 4 and m2= 8. Substitute, these two values in the above formula.
Requirednumberof2to4decoders=8/4=2
Therefore, we require two 2 to 4 decoders for implementing one 3 to 8 decoder.
The block diagram of 3 to 8 decoder using 2 to 4 decoders is shown in the following
figure.

The parallel inputs A1 & A0 are applied to each 2 to 4 decoder. The complement of input
A2 is connected to Enable, E of lower 2 to 4 decoder in order to get the outputs, Y 3 to Y0.
These are the lower four min terms. The input, A2 is directly connected to Enable, E of
upper 2 to 4 decoder in order to get the outputs, Y7 to Y4. These are the higher four min
terms.

4 to 16 Decoder
In this section, let us implement 4 to 16 decoder using 3 to 8 decoders. We know that
3 to 8 Decoder has three inputs A2, A1 & A0 and eight outputs, Y7 to Y0. Whereas, 4 to 16
Decoder has four inputs A3, A2, A1 & A0 and sixteen outputs, Y15 to Y0
We know the following formula for finding the number of lower order decoders required.

Required number of lower order decoders=m2/m1

Substitute, m1 = 8 and m2 = 16 in the above formula.
Required number of 3to8 decoders=16/ 8=2
Therefore, we require two 3 to 8 decoders for implementing one 4 to 16 decoder.
The block diagram of 4 to 16 decoder using 3 to 8 decoders is shown in the following
figure.

The parallel inputs A2, A1 & A0 are applied to each 3 to 8 decoder. The complement of input, A3 is
connected to Enable, E of lower 3 to 8 decoder in order to get the outputs, Y7 to Y0. These are the lower
eight min terms. The input, A3 is directly connected to Enable, E of upper 3 to 8 decoder in order to get
the outputs, Y15 to Y8. These are the higher eight min terms.

Encoder