8051 Architecture and

Instruction Set
17:03 1
8051 Architecture
Reset
T0 T1 S1 WDT OSC
Port P1
IR
SFRs IO and Execution Unit
Devices
ID
ALU
A, B, PSW, SP, SFRs
DPTR (2SFRs)
Register Bank
of 8 Condition Test Branch logic
registers
ROM
and RAM Control & Sequencing Circuit
Port P3
PC
Port P2
Interrupt Control Circuit
A8-A15 AD0-AD8
Port P0
17:03 2
8051 Architecture
Features
• 12 MHz clock. Processor
instruction cycle time 1 μs. [in
Classic version]
• An 8-bit ALU and 8-bit internal
bus.
• Harvard memory architecture
–the external program memory
and data memory have separate
address spaces from 0x0000
and separate control signal(s).
17:03 3
8051 Architecture
Features
• 8-bit internal data bus width
and 16-bit internal address bus
–Harvard memory architecture
• CISC (Complex Instruction Set
Computer)
17:03 4
8051 Architecture
Features
• Special function registers
(SFRs) –PSW (processor status
word), A (accumulator), B
register, SP (stack pointer) and
registers for serial IOs, timers,
ports and interrupt handler.
17:03 5
8051 Architecture
Features
• Special bit manipulation
instructions.
• 16-bit Program Counter with
initial default reset value defined
by processor is 0x0000.
• 8-bit Stack Pointer with initial
default value defined by
processor is 0x07
17:03 6
8051 Architecture
Features
Classic 8051 simple architecture
• no floating-point processor,
• no cache,
• no memory management-unit,
• no atomic operations unit,
• no pipeline and
• no instruction level parallelism.
17:03 7
8051 Architecture
Features
• on-chip RAM of 128 bytes.
[8052- version: RAM 256 bytes.]
• 32 bytes of RAM [in 8052 - 256
bytes] is also used as four banks
(sets) of registers. Each
register-set (bank) thus has eight
registers.
17:03 8
8051 Architecture
Features
• External data/stack memory
can be added upto 64 kB in most
versions. [In certain 8051
enhancements, this limit has
been enhanced to 16 MB.]
• 8351 version: on-chip ROM,
8751 version: EPROM, 8951
version has on- chip EEPROM
or flash memory of 4 kB.
17:03 9
8051 Architecture
Features
• Several versions provide for
higher capacity ROM. Additional
program memory can be added
externally upto 64 kB. [In
extended 8051 and unified
address space versions (8051
EX and MX versions), this limit
has been extended to 16 MB.]
17:03 10
8051 Architecture
Features
• Two external interrupt pins,
INT0 and INT1.
• Four ports P0, P1, P2, P3 of
8-bits each in single chip mode.
• Two timers, T0, T1
17:03 11
8051 Architecture
Features
• Serial interface
(SI)–programmable for three full
duplex UART modes for serial
IO. [IO with each bit of a word
successive transmission on the
data line for a time interval.] The
same is programmable for half
duplex synchronous IO.
17:03 12
8051 Architecture
Features
• In certain versions –DMA
controller
• In certain versions–pulse width
modulator and thus support to
DAC, d.c. and servo motor
controls.
17:03 13
8051 Architecture
Features
• In Certain versions –modem,
watchdog timer, ADC. Siemens
SAB 80535-N supports ADC
with programmable reference
voltage. Advanced versions
support these features and a
version is selected as per the
system requirement.
17:03 14
8051 Data Transfer
Instructions
• Move byte between
accumulator (an SFR) and
register at a register bank,
example: MOV R A), n
); n MOV =1 A, R n
(i.e., A ← R to n
, A 8. (i.e., Register
R
n

←
Direct
17:03 15
8051 Data Transfer
Instructions
• Move byte from an
SFR/Internal RAM to another
register indirect, MOV A, @R
means i
and data MOV transfer @R
i

, A; @R
to i
a
n 8bit address pointed by the
contents of the ith register in the
8 register set. PSW bits RS0 and
RS1 predefine the set.
17:03 16
8051 Data Transfer
Instructions
• Four data direct instructions
(direct means transfer to an 8-bit
address internal 128B RAM or
SFR address) MOV direct, #data
MOV A, #data (# represents
constant)
17:03 17
8051 Data Transfer
Instructions
• Four data direct instructions
(direct means transfer to an 8-bit
address internal 128B RAM or
 SFR address) MOV @R
i

, #data @R
i address means transfer to an
8-bit
pointed by the contents
of the ith register in the set (i= 0 or
1)(@ represents indirect ram)
17:03 18
8051 Data Transfer
Instructions
• Seven data transfer
instructions MOV direct, direct
MOV A, direct MOV direct, A
MOV direct , R
n MOV R
n

, direct MOV direct, @R

, direct
17:03 19
8051 Data Transfer
Instructions
• Move indirect to external
memory MOV DPTR, data16
//DPTR ← data16,
DPTR is a 16-bit external
memory data pointer//
17:03 20
8051 Data Transfer
Instructions
• MOVC (move code from
external program memory),
MOVC A, @A+DPTR and
MOVC A, @A+PC
17:03 21
8051 Data Transfer
Instructions
• MOVX for transfer from or to
external data memory, MOVX A,
@DPTR and MOVX @DPTR, A;
@DPTR: address as
pointed by 16-bit of DPTR
• Stack operations: PUSH direct
or POP direct
17:03 22
 8051 Bit and byte
Manipulation
Instructions
Bit Manipulation Set,
Complement, AND or OR or
MOV the bit Logic Instructions
AND, XOR, OR Operation
Instructions Byte Manipulation
Clear, Complement, or swap and
Rotate Instructions
17:03 23
8051 Arithmetic
Instructions
• 8-bit Add, Subtract, Multiply
and divide Instructions
• Increment-Decrement
Instructions
17:03 24
 8051 Program Flow
Control Instructions
• Branch instructions
• Conditional jumps
• Decrement and Jump
conditional
• Compare and then conditional
jump
• Subroutine Call Instructions
• NOP
• Delay
17:03 25
 8051 Interrupt Flow
Control Instructions
• Interrupt flow control-mask bits,
priority bits
• RETI
17:03 26
Addressing Modes
1. DIRECT ADDRESSING 2.
INDIRECT ADDRESSING 3.
REGISTER INSTRUCTIONS 4.
REGISTER-SPECIFIC
INSTRUCTIONS 5. IMMEDIATE
CONSTANTS 6. INDEXED
ADDRESSING
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Addressing Modes
1. DIRECT ADDRESSING In
direct addressing the operand is
specified by an 8-bit address
field in the instruction. Only
internal Data RAM and SFRS
can be directly addressed. MOV
A, 7FH Move direct Byte (7FH to
Accumulator)
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Addressing Modes
2. INDIRECT ADDRESSING In
indirect addressing the
instruction specifies a register
which contains the address of
the operand. Both internal and
external RAM can be indirectly
addressed.
17:03 29
Addressing Modes
2. INDIRECT ADDRESSING The
address register for 8-bit
addresses can be R0 or R1 of the
selected register bank, or the
Stack Pointer. The address
register for 16-bit addresses can
only be the 16-bit “data pointer”
register, DPTR. MOV A, @Ri Move
indirect RAM to
Accumulator
17:03 30
Addressing Modes
3. REGISTER INSTRUCTIONS
The register banks, containing
registers R0 through R7, can be
accessed by certain instructions
which carry a 3-bit register
specification within the opcode
of the instruction.
17:03 31
Addressing Modes
3. REGISTER INSTRUCTIONS
Instructions that access the
registers this way are code
efficient, since this mode
eliminates an address byte.
When the instruction is
executed, one of the eight
registers in the selected bank is
accessed.
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Addressing Modes
3. REGISTER INSTRUCTIONS
One of four banks is selected at
execution time by the two bank
select bits in the PSW. MOV A,
Rn Move register to
Accumulator
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Addressing Modes
4. REGISTER-SPECIFIC
INSTRUCTIONS Some
instructions are specific to a
certain register. For example,
some instructions always
operate on the Accumulator, or
Data Pointer, etc., so no address
byte is needed to point to it. The
opcode itself does that.
Instructions that refer to the
Accumulator as A, assemble as
accumulator-specific opcodes.
17:03 34
Addressing Modes
5. IMMEDIATE CONSTANTS
The value of a constant can
follow the opcode in Program
Memory. For example, MOV A, #
100 loads the Accumulator with
the decimal number 100. The
same number could be specified
in hex digits as 64H.
17:03 35
Addressing Modes
6. INDEXED ADDRESSING
Only Program Memory can be
accessed with indexed
addressing, and it can only be
read. This addressing mode is
intended for reading look-up
tables in Program Memory.
17:03 36
Addressing Modes
6. INDEXED ADDRESSING (a)
A 16-bit base register (either
DPTR or the Program Counter)
points to the base of the table,
and the Accumulator is setup
with the table entry number. The
address of the table entry in
Program Memory is formed by
adding the Accumulator data to
the base pointer.
17:03 37
Addressing Modes
6. INDEXED ADDRESSING (b)
Another type of indexed
addressing is used in the “case
jump” instruction. In this case the
destination address of a jump
instruction is computed as the
sum of the base pointer and the
Accumulator data.
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IO Ports
Port P0 Port P2
P0.0, P0.1, P0.2, P0.3,
P2.0, P2.1, P2.2, P2.3,
P0.4, P0.5, P0.6, P0.7
P2.4, P2.5, P2.6, P2.7 (Also
as AD0-AD7)
(Also as A8-A15)
Port P3
Port P1
P3.0, P3.1, P3.2, P3.3,
P1.0, P1.1, P1.2, P1.3,
P1.4, P3.4, P3.5, P3.6, P3.7
P1.5, P1.6, P1.7
(RxD/SyncData,
(Also P1.6 as I2C clock,
P1.7 TxD/SyncClk, INT0/GT0,
as I2C serial data, and
P1.0 INT1/GT1, T0, T1, WR, RD)
and P1.1 for T2 [8052] )
17:03 39
 IO port circuit for two
stepper motors in a
printer
Stepper Motor 1 Stepper Motor 2
P1.0
Coil A
P1.4
Coil A’
P1.1
Coil B
P1.5
Coil B’
P1.2
Coil C
P1.6
Coil C’
P1.3
Coil D
P1.7
Coil D’
17:03 40
 IO port circuit for six
servo motors in a robot
P1.0
Servomotor 0
P1.1
Servomotor 1
P1.2
Servomotor 2
P1.3
Servomotor 3
P1.4
Servomotor 4
P1.5
Servomotor 5
17:03 41
IO Byte Programming
• 8051 internal IO ports P0, P1,
P2 and P3 have byte addresses
used to access and perform read
or write or other operations
• Direct 8-bit addresses of each
are specified in the instructions
• Addresses of bytes
at─0x80(P0), 0x90(P1),
0xA0(P2) and 0xB0(P3).
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IO Byte Programming
1. All instructions in the
instruction set
using direct addresses can be
used to access and perform read
or write operations on the ports.
17:03 43
IO Byte Programming,
Example 1
MOV 0xA0, #0xFF moves bits to
port P2; and P2 bits will become
= 11111111b. MOV 0x90, #0x1C
moves bits at port P1 =
00011100b. After this instruction,
INC 0x90 will make P1 =
00011100b + 1 = 00011101b.
17:03 44
IO Port Bit
Programming
2. Each port P0, P1, P2 and P3
has 8 bits
and each bit has addresses to
access and perform read or write
or other operations using
bit-manipulation instructions.
Addresses are the bit addresses.
Each bit address is of 8-bits,
which are specified in the
instructions.
17:03 45
IO Port Bit
Programming
Bits P0.0 to P0.7 addresses
─0x80 to 0x87 Bits P1.0 to P1.7
addresses ─0x90 to 0x97, P2.0
to P2.7 ─0xA0 to 0xA7 and P3.0
to P3.7 ─0xB0 to 0xB7.
17:03 46
 IO Port Bit
Programming (SFR
Space)
FFH
REGISTER-MAPPED PORTS
E0H ACC
ADDRESSES THAT END IN 0H AND 8H ARE ALSO
BIT-ADDRESSABLE B0H PORT 3
A0H PORT 2
-PORT PINS -ACCUMULATOR -PSW ETC. 90H PORT 1
THE SFRS CAN ONLY BE ACCESSED BY
80H PORT 0
DIRECT ADDRESSING
17:03 47
IO Port Bit
Programming
All instructions in the instruction
set using bit addresses can be
used to access and perform
complement, read or write or
other operations. C flag in PSW
─Accumulator for bit logic
operations using bit addresses.
17:03 48
IO Port Bit
Programming Example
CPL 0x90 complements the bit 0
at port P1. CLR 0x80 makes
P0.0 as 0. Generation of pulses:
delay of period= T1, say SETB
0x80 //make P0.0 as 1;
17:03 49
IO Port Bit
Programming Example
delay of period= T2, CLRB 0x80
//make P0.0 as 0. continue A
pulse of time-period T2 and duty
cycle 100 ×T2/(T1 + T2) is
created, if the SETB 0x80 and
CLRB 0x80 instructions are
executed in a loop.
17:03 50
IO Port Bit
Programming Example
T2 T1
SETB 0x80 CLRB 0x80 17:03 51
IO Port Bit
Programming Example
SETB C //set carry bit in PSW to
1 ANL C, 0x93 //logic AND
operation between bits C (CY is
written as C) and P1.3 and result
will be in C. If P1.3 = 0, C
becomes 0 else C will remain 1.
PSW structure:
CY AC F0 RS1 RS0 OV P
17:03 52
IO Port Bit
Programming Example
CLR C //reset (clear) carry bit in
PSW to 0. ORL C, 0xB2 //logic
OR between bits C and P3.2 and
result will be in C. If P3.2 = 0
then C will remain 0 else C will
remain 1. MOV 0x85, C //moves
result in C to P0.5.
17:03 53
PSW structure
CY AC F0 RS1 RS0 OV P
CY: carry flag AC: auxiliary carry
F0: general purpose status flag
RS1: register bank select bit 1
RS0: register bank select bit 0 OV:
over flow flag set by arithmetic
operations P: parity of accumulator
(=1, if odd 1s)
17:03 54
Memory mapped IO
8051 Memory and ports are
assigned addresses such that
each have distinct range of
addresses in the data memory
address space. Therefore,
Interfacing circuits design is
identical to that for the memory
and connects the external ports
and programmable peripheral
interface (PPI).
17:03 55
Memory mapped IO
size Address range EA PSEN RD/ WR
Int RAM/SFR (128 or 256B) 0x00 to 0xFF
Int ROM (4KB) 0x0000-0x0FFF High x x
Ext P-Mem (64KB) 0x1000-0xFFFF High
Low x Ext P-Mem (64KB) 0x0000-0xFFFF
Low Low X Ext D-Mem (64KB)
0x0000-0xFFFF Low High Low
17:03 56
The Lower 128 Bytes of
internal RAM 7F
BANK SELECT BITS IN PSW (RS0 and RS1)
20
2F
BIT ADDRESSABLE SPACE (BIT ADDRESS 0-7F)
11
18
1F
10
10
17
01
08
00
17:03 57

4 BANKS OF 0F
8 REGISTERS R0-R7
RESET VALUE OF 00
STACK POINTER 07
Harvard Memory
Architecture
Two sets of memory ─ i.
program memory and ii. data
memory. Two control signals ─
to control read (RD) from
program memory, when PSEN =
low (PSEN, Program Store
Enable) and to control read from
data memory, when PSEN =
high.
17:03 58
Harvard Memory
Architecture
Control signal ALE to control use
of AD0- AD7 through P0.0 –
P0.7, respectively, as address or
data at a given instant. A latch
separates A0-A7 from D0-D7.
17:03 59
Harvard Memory
Architecture
P2 is used in expanded mode as
A8-A15 address lines─ When
the processor activates PSEN,
an active low signal, it reads the
byte from external program
memory through D0-D7 data
bus.
17:03 60
Harvard Memory
Architecture
When the processor activates
RD, also an active low signal, it
reads the byte from external
data memory through D0-D7
data bus.
17:03 61
Harvard Memory
Architecture
ALE
EA
P0 as
AD0-AD7 A0-A7 AD0- AD7
D0-D7
A8-A15 P2 as
D
0-D7 A8-A15
17:03 62

LATCH
PROGRAM MEMORY 0x0000-0xFFFF
PSEN
EA DATA MEMORY 0x0000-0xFFFF
WR RD
Signals from CPU: ALE,
Bidirectional lines: D0-D7 and
AD0-AD7 (from P0) EA, RD, WR
Unidirectional lines: A0-A15, (A8-A15 from P2)
PPI Interfacing
EA
ALE
A0-A1 P0 as
LATCH AD0- AD7
PA
PA0- 8255
 PA7 PPI
PB CS
PB0- PB7
A8-A15 P2 as A8-A15
AD0-AD7
A2-A7
D0-D7
DECODER
PC
PC0- PC7 P3.6
WR
P3.7
RD
D0-D7
Bidirectional lines: D0-D7 and AD0-AD7 Unidirectional
lines: A0-A15
17:03 63
Timing and Counting
Devices
Two T0 and T1 in classic 8051
family and three T0, T1 and T2
in 8052 family (an extension of
8051).
17:03 64
Counting/timing device
as timer
A device for timing when the
inputs are given by a clock. The
clock pulses are internally given
at the specific time intervals.
17:03 65
Counting/timing device
as counter
A device for counting when the
inputs to count are given
externally. Counter is given the
input to count from external input
pin.
17:03 66
 TMOD: Timer/Counter
Mode Control Register
GATE C/T M1 M0 GATE C/T M1 M0
TIMER1 TIMER0 17:03 67
 TCON:Timer/Counter
Control Register
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TF: timer1 over flow; TF0 timer0
over flow TR1: timer1 run control
bit TR0: timer0 run control bit
17:03 68
 External controls for
activation or
deactivation
• As timing or counting devices,
T0 or T1 is externally controlled
by the gate inputs, i.e., when
GT0 or GT1 is externally
activated, the device functions,
else it gets deactivated in gate
input mode.
• GT0 or GT1 signals are given
at P3.2 and P3.3.
17:03 69
Counting/timing device
External count inputs in
counter mode
• T0 counts when T0 is given the
input to count from external input
pin T0 at P3.4.
• T1 counts when T1 is given the
input to count from external input
pin T1 at P3.5.
17:03 70
Four functions of Port
P3 Pins
When TMOD SFR bits 3, 7, 2
and 6 set = 1, P3.2, P3.3, P3.4
and P3.5 function as
• GT0 (gate for starting/stopping
T0),
• GT1 (gate for starting/stopping
T1),
• T0 (count input to T0) and
• T1 (count input to T1) inputs,
respectively.
17:03 71
Two SFRs TH1-TL1
• For accessing the counts or
time, higher and lower 8 bits of
T1 device
• The SFRs, TH1-TL1, hold the
16-bits of T1-device.
17:03 72
Two SFRs TH0-TL0
• For accessing the counts or
time, higher and lower 8 bits of
T0 device
• The SFRs, TH0-TL0, hold the
16-bits of T0-device.
17:03 73
SFR TMOD
• Controls the T1 and T0 modes
using the upper and lower 4 bits
each, which program the
counting/timing of T1 and T0.
• A bit in each controls the
function that external gate input
controls or not.
17:03 74
SFR TMOD
• A bit controls the function that
counter or timer mode is used.
• Two bits control the functional
mode of timer/counter as mode
0 or 1 or 2 or some other action
17:03 75
 SFR TCON T1 and T0
control and status bits
• Upper four 4 bits program the
modes of counting/timing
devices T1 and T0. TCON.7 and
TCON.5 show the timer/counter
overflow status for T1 and T0,
respectively.
• TCON.6 and TCON.4 control
the start and stop of the
timer/counter
• Lower bits of TCON are for the
interrupt control for INT0 and
INT1.
17:03 76
Timer/Counter T0
• 8-bit SFRs─TMOD(lower 4
bits), TCON(bit 5 and 4),
TL0(count/time bits),
TH0(count/time bits)
• Counter with inputs at P3.4,
when bit 2 of TMOD =1, timer
with internal clock timed
inputs when bit 2 of TMOD = 0
17:03 77
Timer/Counter T0
• When mode set = 0, 8-bit
timer/Counter mode and TH0 is
used and TL0 is used for
prescaling(dividing) inputs by 32
• When mode set = 1, 16-bit
timer/counter mode with
TH0-TL0 is used for timing or
counting
17:03 78
Timer/Counter T0
• When mode set = 2, 8-bit
timer/Counter TH0 is used and
TL0 is used for auto-reloading
the TH0 after timeout using a
preset value at TL0
• When mode set = 3, two 8-bit
timer/Counters mode TH0 and
TL0 are independent 8-bit
timer/counter and T1 does not
function.
17:03 79
Timer/Counter T1
8-bit SFRs are used for
TMOD(upper 4 bits), TCON (bit
7 and 6), TL1(count/time bits),
TH1(count/time bits) Counter
with inputs at P3.5 when bit 6
TMOD =1, timer with internal
clock timed inputs when bit 6
TMOD = 0
17:03 80
Timer/Counter T1
When mode set = 0, 8-bit
timer/Counter mode and TH1 is
used and TL1 is used for
prescaling(dividing) inputs by 32
When mode set = 1, 16-bit
timer/counter mode with
TH1-TL1 is used for timing or
counting
17:03 81
Timer/Counter T1
When mode set = 2, 8-bit
timer/Counter TH1 is used and
TL1 is used for auto- reloading
the TH1 after timeout using a
preset value at TL1 When mode
set = 3, T1 stops as TH0 now
functions in place of T1.
17:03 82
Advanced
Architectures2013.pptx
17:03 83