Chapter 3

Implementation Technology

Fundamentals of Digital Logic Department of Electrical Engineering

 3.5 Standard Chips (7400-Series)

VDD

Gnd

(a) Dual-inline package (b) Structure of 7404 chip

Figure 3.21. A 7400-series chip. SOIC
Pin 12

Pin 14

Pin 16

Pin 18

Pin 19
Pin 11

Pin 13

Pin 15

Pin 17
Package?
Pins or Leads

Small
Outline
Integrated
Circuit
Pin 1
Pin 2

Pin 4

Pin 6

Pin 8

Pin 3

Pin 5

Pin 7

Figure 3.23. The 74244 buffer chip. Pin 9

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 3.5 Standard Chips (7400-Series)

A logical function can be implemented using standard chips by

connecting together multiple chips.
DD

• SSI
7404 • MSI
• LSI
• VLSI

7408 7432

x1
x2
x3
f
Figure 3.22. An implementation of f = x1x2 + x2x3.
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 3.6 Programmable Logic Devices

• Motivation

• Introduced in 1970 Inputs

Logic gates Outputs
(logic variables) and (logic functions)
programmable
• Combination of AND & switches
OR gates with
programmable switches

Figure 3.24. Programmable logic device

as a black box.

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 3.6.1 Programmable Logic Array
1 2 n

Input buffers
and
inverters

x1 x1 xn xn

P1

AND plane OR plane

Pk

f1 fm
Figure 3.25. General structure of a PLA.
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 3.6.1 Programmable Logic Array
x1 x2 x3

Programmable
connections

OR plane
P1

P2

P3

P4

AND plane

f1 f2
Figure 3.26. Gate-level diagram of a PLA.
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 3.6.1 Programmable Logic Array
x1 x2 x3
Commercially available PLA’s Specs?

OR plane
P1

P2

Programmable
connections P3

P4

AND plane

f1 f2

Figure 3.27. Customary schematic for the PLA in Figure 3.26.

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 3.6.2 Programmable Array Logic
x1 x2 x3

Less Flexibility P1
Low Cost f1
P2

P3

f2
P4

AND plane
Figure 3.28. An example of a PAL.

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 3.6.2 Programmable Array Logic

Select
Enable

f1
Flip-flop

D Q

Clock

To AND plane

Figure 3.29. Extra circuitry added to OR-gate from Figure 3.28.

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 3.6.3 Programming of PLAs & PALs

Figure 3.30. A PLD programming unit

(courtesy of Data IO Corp)

rd
it boa
circu
nted
Pri

Figure 3. 31. PLCC package with socket.

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 3.6.4 Complex PLDs

Why to use CPLDS?

• Limitation on function implementation with PLAs and
PALs.
• 32 inputs and outputs can be catered with SPLDs.

What is CPLD?
• Multiple circuit blocks (PAL or PLA) connected
together on a single chip.
• Each circuit block is connected to sub-circuit called
I/O block

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 3.6.4 Complex PLDs

I/O block

I/O block
PAL-like PAL-like
block block

Interconnection wires
I/O block

I/O block
PAL-like PAL-like
block block

Figure 3.32. Structure of a complex programmable logic device (CPLD).

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 3.6.4 Complex PLDs (Contd.)

PAL-like block (details not shown) External pin

PAL-like block
Programmable
Switches
D Q

Macro cell

D Q

D Q

Figure 3.33. A section of the CPLD in Figure 3.32.

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 3.6.4 Complex PLDs (Contd.)

• How many macro cells in PLA like block in

commercial CPLDs?
• How many PAL or PLA like blocks in commercial
CPLDs?
• What is the difference between PLCC & QFP??
• Why In System Programming is used for CPLDs?

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 3.6.4 Complex PLDs (Contd.)

(a) CPLD in a Quad Flat Pack (QFP) package

To computerJTAG Port

Printed
circuit board

(b) JTAG programming

Figure 3.34. CPLD packaging and Joint Test Action Group programming.
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 3.6.5 Field Programmable Gate Arrays

Logic Cells
I/O Blocks
Interconnection
Wires

Figure 3.35. A field-programmable gate array (FPGA).

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 3.6.5 FPGA (LUT Implementation)
x1

0/1

0/1 x1 x2 f1
f
0/1 0 0 1
0 1 0
Logic Block 0/1
1 0 0
x2 1 1 1

(a) Circuit for a two-input LUT (b) f 1 = x 1 x 2 + x 1 x 2

x1

Storage Cell 1

0
f1
0

1
x2

(c) Storage cell contents in the LUT

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 3.6.5 Field Programmable Gate Arrays

x1
x2

0/1
0/1
0/1
0/1
f
0/1
0/1
0/1
0/1
x3

Figure 3.37. A three input LUT

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 3.6.5 Field Programmable Gate Arrays

Select

Out
Flip-flop
In1
In2 LUT D Q
In3
Clock

Figure 3.38. Inclusion of a flip flop in an FPGA logic block

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 3.6.5 Field Programmable Gate Arrays
x3 f

x1

x1 0 x2 0
0 f1 1 f2
0 0
x2 x2 x3
1 0

f1 0
1 f
1
f2
1

Figure 3.39. A section of a programmed FPGA

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 3.6.5 Field Programmable Gate Arrays

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 3.8 Tri-State Buffers
e= 0

e x f

x f
e= 1
x f

(a) A tri-state buffer (b) Equivalent circuit

e x f e
0 0 Z
0 1 Z
x
1 0 0
1 1 1

(c) Truth table (d) Implementation

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 3.8 Tri-State Buffers
e e

x f x f

(a) (b)

e e

x f x f

(c) (d)

Figure 3.58. Four types of tri-state buffers.

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 3.8 Tri-State Buffers

x1 f

x2

Figure 3.59. An application of tri-state buffers.

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 3.9 Transmission Gates
s

x f s f

0 Z
1 x
s

(a) Circuit (b) Truth table

s= 0

x f=Z s

s= 1 x f
x f=x s
(c) Equivalent circuit (d) Graphical symbol

Figure 3.60. A transmission gate.

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 3.9.1 Exclusive-OR Gates
x1 x2 f = x1 x2
0 0 0
0 1 1 x1
1 0 1
x2 f = x1 x2
1 1 0

(a) Truth table (b) Graphical symbol

x1
x2

f = x1 x2

(c) Sum-of-products implementation

Figure 3.61a. Exclusive-OR gate.

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 3.9.1 Exclusive-OR Gates

x1
x2

f = x1  x2

(d) CMOS implementation

Figure 3.61b. CMOS Exclusive-OR gate.

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 3.9.1 Multiplexer with Transmission Gates

x1

x2 f

Figure 3.62. A 2-to-1 multiplexer built using transmission gates.

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