Unit | Fundamentals of Microprocessor Introduction to Microprocessor Microprocessor is a controlling unit of a micro-computer, fabricated on a small chip capable of performing ALU (Arithmetic Logical Unit) operations and communicating with the other devices connected to it. Microprocessor consists of an ALU, register array, and a control unit. ALU performs arithmetical and logical operations on the data received from the memory or an input device. Register array consists of registers identified by letters like B, C, D, €, H, L and accumulator (register in which intermediate arithmetic and logic results are stored.). The control unit controls the flow of data and instructions within the computer. Block Diagram of a Basic Microcomputer = Microprocessor 5 Device ————*_ (ALU +Register array + “> _ Device Control unit) Memory How does a Microprocessor Work? The microprocessor follows a sequence: Fetch, Decode, and then Execute. Initially, the instructions are stored in the memory in a sequential order. The microprocessor fetches those instructions from the memory, then decodes itand executes those instructions till STOP instruction is reached. Later, it sends the result in binary to the output port. Between these processes, the register stores the temporarily data and ALU performs the computing functions. Features of a Microprocessor Here is a list of some of the most prominent features of any microprocessor - a) Cost-effective The microprocessorchips are available atlow prices and results. its low cost. 6) Size - The microprocessor is of small size chip, hence is portable ) Low Power Consumption - Microprocessors are manufactured by using metaloxide semiconductor technology, which has low power consumption. 4) Versatility - The microprocessors are versatile as wecan use the same chip ina number of applications by configuring the software program.e) Reliability - The failure rate of microprocessors is very low, hence itis reliable. roprocessor Architecture & Operati System Bus Mi Microprocessor ‘Memory ALU (Arithmetic/Logic Unit) — It performs such arithmetic operations as addition and subtraction, and such logic operations as AND, OR, and XOR. Results are stored either in registers or in memory. Register Array — It consists of various registers identified by letter such as B, C, D, E, H, L, IX, and IY. These registers are used to store data and addresses temporarily during the execution of a program. Control Unit — The control unit provides the necessary timing and control signals to all the operations in the microcomputer. It controls the flow of data between the microprocessor and memory and peripherals. Input — The input section transfers data and instructions in binary from the outside world to the microprocessor. It includes such devices as a keyboard, switches, a scanner, and an analog-to-digital converter. Qutput — The output section transfers data from the microprocessor to such output devices as LED, CRT, printer, magnetic tape, or another computer. Memory — It stores such binary information as instructions and data, and provides that information to the microprocessor. To execute programs, the microprocessor reads instructions and data from memory and performs the computing operations in its ALU section. Results are either transferred to the output section for display or stored in memory for later use. ‘System bus — It is a communication path between the microprocessor and peripherals. The microprocessor communicates with only one peripheral at a time. The timing is provided by the control unit of the microprocessor.Microprocessor Vs Microcontroller ‘CPUis stand alone, RAM.ROM, 1/0 & timer CPU, RAM,ROM, V/O & timer all are on are separate. single chip. Designer can decide amount of RAM,ROM, _ Fixed amount of on-chip RAM.ROM, & /O & VO pons. ports. High processing power Low processing power High power consumption Low power consumption ‘Typically 32/64 bit 8/16 bit General purpose Single purpose(control oriented) Less reliable Highly reliable Eg.- 8086,8085 8051 Bus organization of 8085 microprocessor Bus isa group of conducting wires which carries information, all the peripherals are connected to microprocessor through Bus. es ADDRESS BUS sos Vv micRoP- | . ROCESSOR”|/ \ UNT AG oA > (Pu) 4 L L p CONROLBUS y VAN XZ \AAZ weno] [seer] [amor] Bus organization system of 8085 MicroprocessorThere are three types of buses. a) 4) Address bus — It is a group of conducting wires which carries address only. Address bus is unidirectional because data flow in one direction, from microprocessor to memory or from microprocessor to Input/output devices (That is, Out of Microprocessor) Data bus: itis a group of conducting wires which carries Data only. Data bus is bidirectional because data flow in both directions, from microprocessor to memory or Input/output devices and from memory or Input/output devices to microprocessor. Control bu: itis a group of wires, which is used to generate timing and control signalsto control all the associated peripherals, microprocessor uses control bus to process data, that is what to do with selected memory location. Some control signals are: - Memory read - Memory write - WOread - 1/0 Write 8085 Microprocessor & its Operation 8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology. It has the following configuration — - 8-bit data bus - 16-bit address bus, which can address up to 64KB - A.16-bit program counter stack pointer registers arranged in pairs: BC, DE, HL - Requires +V supply to operate at 3.2 MHZ single phase clock It is used in washing machines, microwave ovens, mobile phones, etc.8085 Microprocessor Architecture & Functional Unit SOLS ces tes on THOT ah bead 580 | o_| est oer ram of 8085 Microprocessor. 8085 consists of the following functional units - 1) Accumulator It is an B-bit register used to perform arithmetic, logical, 1/0 & LOAD/STORE operations. It is connected to internal data bus & ALU. 2) Arithmetic and logic unit As the name suggests, it performs arithmetic and logical operations like Addition, Subtraction, AND, OR, etc. on 8-bit data. 3) General purpose register There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register can hold 8-bit data. These registers can work in pair to hold 16-bit data and their pairing combination is like B-C, D-E & H-L.4) Program counter It is a 16-bit register used to store the memory address location of the next instruction to be executed. Microprocessor increments the program whenever an instruction is being executed, so that the program counter points to the memory address of the next instruction that is going to be executed 5) Stack pointer It is also a 16-bit register works like stack, which is always incremented/decremented by 2 during push & pop operations. 6) Temporary register It is an 8-bit register, which holds the temporary data of arithmetic and logical operations. 7) Flag register Itis an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the result stored in the accumulator. These are the set of 5 flip-flops — ~ Sign (8) - Zero (2) ~ Auxiliary Carry (AC) - Parity (P) - Carry (C) Its bit position is shown in the following table — 07 06 DS D4 3 D2 D1 bo Ss Zz AC P cy 3 Sign Flag(S)—After anyoperationif resultis negative sign flagbecomesset, i.e. If result is positive sign flag becomes reset ie. 0. + Example: MVIA30(load 30HinregisterA) MVIB 40 (load 40Hin registerB) SUBB (A=A-B) These set of instructions will set the sign flag to 1 as 30 - 40 is a negative number. MVIA40(load 40Hin registerA) MVIB 30 (load 30H in registerB) SUBB(A=A-B) These set ofinstructions willresetthe sign fiag to 0as 40-30isapositive number.Zero Flag (2) After any arithmetical or logical operation if the result is 0 (00)H the zero flag becomes seti.e. 1, otherwise it becomes reseti.e. 0. + Example: MVIA10(load 10HinregisterA) SUBA(A=A-A) These set of instructions will set the zero flag to 1 as 10H — 10H is OOH 9 Auxiliary Carry Flag (AC) = If intermediate carry is generated this flag is set to 1, otherwise it is reset to 0. + Example: MOV A 2B (load 2BH in register A) MOV B 39 (load 39H in register B) ADDB(A=A+B) ‘These set of instructions will set the auxiliary carry flag to I, as on adding 2B and 39, addition of lower order nibbles B and 9 will generate a carry 4 Parity Flag (P)— If after any arithmetic or logical operation the result has even parity, an even number of 1 bits, the parity register becomes set i.e. 1, otherwise it becomes reset. 1-accumulator has even number of I bits 0-accumulator has odd parity Carry Flag (CY) — Carry is generated when performing n bit operations and the result is more than n bits, then this flag becomes sct i.c. 1, otherwise it becomes Teset ie. 0. During subtraction (A-B), if A>B it becomes reset and if (A< ‘Machine Cycle 2 ? a 2 8 4 5 6 7 / / \ f -—-~ f / / /| \ I \ J \_/ < Fetch cycle. Execution Cycle . << instruction eyele Instruction cycle in 8085 microprocessor Different types of Machine Cycles: Opcode Fetch Cycle The first machine cycle of every instruction is opcode fetch cycle in which the 8085 finds the nature of the instruction to be executed. In this machine cycle, processor places the contents of the Program Counter on the address lines, and through the read process, reads the opcode of the instruction. The length of this cycle is not fixed. It varies from 4T states to 6T states as per the instruction. Below figure shows timing diagram of opcode fetch: pert tera), ——— ai T 2 Memory Read CycleThe 8085 executes the memory read cycle to read the contents of R/W memory or ROM. The length of this machine cycle is 3-T states (T1 — T3). In this machine cycle, processor places the address on the address lines from the stack pointer, general purpose register pair or program counter, and through the read process, reads the data from the addressed memory location. Timing diagram is shown below: te Menory Read ———o} t a “ASN NT Ae L/ 10/71.5,. Se RO Memory Write Cycle The 8085 executes the memory write cycle to store the data into data memory or stack memory. The length of this machine cycle is 3T states. (T1 — T3). In this machine cycle, processor places the address on the address lines from the stack pointer or general purpose register pair and through the write process, stores the data into the addressed memory location.“\S 7, Arenal X_| Memon adtess 1/0 Read and I/O Write cycl The 1/O read and 1/0 write machine cycles are similar to the memory read and memory write machine cycles, respectively, except that the 10/M signal is high for I/O read and |/O write machine cycles. High 10/M signal indicates that it is an 1/0 operation. + — opens ——s ee 7 7 i aux S| ne aa Ton A0,-ADs_ |X Tronae, {oom = 10/M,s, S|iming Diagrams Draw timing diagrams for following instructions: a) Mov b) mv ©) IN d) OUT e) LOA f) STA Addressing Modes in 8085 To perform any operation, we have to give the corresponding instructions to the microprocessor. In each instruction, programmer has to specify 3 things: 1. Operation to be performed 2. Address of source of data. 3. Address of destination of result. The method by which the address of source of data or the address of destination of result Is given in the instruction is called Addressing Modes. The term addressing mode refers to the way in which the operand of the instruction is specified. Intel 8085 uses the following addressing modes: 1) Direct Addressing Mode 2) Register Addressing Mode 3) Register Indirect Addressing Mode 4) Immediate Addressing Mode 5) Implicit Addressing Mode Direct Addressing Mode In direct addressing mode, the data to be operated is available inside a memory location and that memory location is directly specified as an operand. The operand is directly available in the instruction itself. Example: LDA 2050 (load the contents of memory location into accumulator A) Register Addressing Mode In register addressing mode, the data to be operated is available inside the register(s) and register(s) is(are) operands. Therefore, the operation is performed within various registers of the microprocessor. Examples: MOV A, B (move the contents of register B to register A) ADD B (add contents of registers A and B and store the result in register A) INR A (increment the contents of register A by one)Register Indirect Addressing Mode In register indirect addressing mode, the data to be operated is available inside a memory location and that memory location is indirectly specified by a register pair. Example: MOV A, M (move the contents of the memory location pointed by the H-L pair to the accumulator) Immediate Addressing Mode Inimmediate addressing mode the source operand is always data. If the datais &-bit, then the instruction will be of 2 bytes, if the data is of 16-bit then the instruction will be of 3 bytes. Example: MMVI B45 (move the data 45H immediately to register B) Implied/Implicit Addressing Mode In implied/implicit addressing mode the operand is hidden and the data to be operated is available in the instruction itself. Exampli RRC (rotate accumulator A right by one bit) RLC (rotate accumulator A left by one bit] Introduction to 8086 8086 Microprocessor is an enhanced version of 8085Microprocessor that was designed by Intel in 1976. It is a 16-bit Microprocessor having 20 address lines and16 data lines that provides up to 1MB storage. It consists of powerful instruction set, which provides operations like multiplication and jon easily. It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode is suitable for system having multiple processors and Minimum mode is suitable for system having a single processor. Features of 8086 a) It has an instruction queue, wl is capable of storing si the memory resulting in faster processing. b) It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16-bit external data bus resulting in faster processing. ¢)_ Ituses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves performance. Fetch stage can prefetched up to 6 bytes of instructions and stores them in the queue. Execute stage executes these instructions. d) Itconsists of 29,000 transistors. struction bytes fromComparison between 8085 & 8086 Microprocessor ‘8085 Microprocessor ‘8086 Microprocessor itis an 8 ‘oprocessor. itis 16 bit microprocessor. Ithas 16 ?bit address line. It has 20 bit address line. It has 8- bit data bus. It has 16-bit data bus. ‘The memory capacity is 64 KB. The memory capacity is 1 MB. Clock speed of this microprocessor is 3 MHz. Clock speed of this microprocessor varies between 5, 8 and 10 Miz for different versions. thas 5 flags. Tthas 9 flags. 8085 microprocessor does not support memory segmentation. 8086 microprocessor segmentation. supports memory It does not support pipelining. It supports pipelining. Itis accumulator based processor. Itis general purpose register based processor. It has no minimum or maximum mode. Ithas minimum and maximum modes. In 8085, only one processor is used In 8086, more than one processor is used. Additional external processor can also be. employed. It contains less number of transistors compare to 8086 microprocessor. It contains about 6500 transistor. It contains more number of transistors compare to 8085 microprocessor. It contains about 29000 in size. The cost of 8085 is low. The cost of 8086 is high.Internal Architecture of 8086 Execution Unit (EU) BUS Interface Unit (BIU) Data Register Pointer { Register Segment Register Index { Register DI Internal BUS Extemal BUS | ‘Temporary Registers Instruction Queue Fig: Functional Block Diagram of 8086Functional Units 8086 contains two independent functional units:a Bus Interface Unit (BIU) and an Execution Unit (EU). Bus Interface Unit (BIU The segment registers, instruction pointer and 6-byte instruction queue are associated with the bus interface unit (BIU). The BIU: + Handles transfer of data and addresses, + Fetches instruction codes, stores fetched instruction codes in first-in-first-out register set called a queue, + Reads data from memory and I/O devices, + Writes data to memory and 1/0 devices It has the following functional parts: + Instruction Queue: When EU executes instructions, the BIU gets 6-bytes of the next instruction and stores them in the instruction queue and this process is known as instruction pre fetch. This process increases the speed of theprocessor. + Segment Registers: A segment register contains the addresses of instructions and data in memory which are used by the processor to access memory locations. + There are 4 segment registers in 8086 as given below: + Code Segment Register (CS): Code segment of the memory holds instruction codes of a program. * Data Segment Register (DS): The data, variables and constants given in the program are held in the data segment of the memory. + Stack Segment Register (SS): Stack segment holds addresses and data of subroutines. It also holds the contents of registers and memory locations given in PUSH instruction. + Extra Segment Register (ES): Extra segment holds the destination addresses of some data of certain string instructions. + Instruction Pointer (IP): The instruction pointer in the 8086 microprocessor acts as a program counter. It indicates to the address of the next instruction to be executed. Execution Unit(EU) The EU receives opcode of an instruction from the queue, decodes it and then executes it. While Execution, unit decodes or executes an instruction, then the BIU fetches instruction codes from the memory and stores them in the queue. + General Purpose Registers: There are four 16-bit general purpose registers: AX (Accumulator Register), BX (Base Register), CX (Counter) and DX. + Index Register: The following four registers are in the group of pointer and index registers + Stack Pointer (SP) + Base Pointer (BP)+ Source Index (SI) * Destination Index (D1) It handles all arithmetic and logical operations. Such as addition, subtraction, multiplication, division, AND, OR, NOT operations. Flag Register: It is a 16 bit register which exactly behaves like a flip-flop, means it changes states according to the result stored in the accumulator. It has 9 flags and they are divided into 2 groupsi.e. conditional and control flags. * Conditional Flags: This flag represents the result of the last arithmetic or logical instruction executed. Conditional flags are: + Carry Flag + Auxiliary Flag + Parity Flag + Zero Flag + Sign Flag * Overflow Flag Control Flags: It controls the operations of the execution unit. Control flags are: + Trap Flag + Interrupt Flag + Direction Flag Interrupts: The Intel 8086 has two hardware interrupt pins: NMI (Non-Maskbale Interrupt) INTR (Interrupt Request) Maskable Interrupt.ram MAX MIN move (move GND Ucc Ap14 aos A013 Alg/S3 p12 Al7/S4 oll ale/ss AD10 Alg/s6 ADS BHE/S7 ADs MINIM D7 *0 AD6 RO/GTO (HOLD) ADS RO/GT1 (HLDA) AD4 COCK «= (WR) AD3 52 (vi) D2 31 (ovr) D1 50 (DEN) D0 Qso ALE) NMI Qs1 (INTA) InTR TEST cuK READY GND RESET + ADO-ADI5 (Address Data Bus): Bidirectional address/data lines. These are low order address bus. When these lines are used to transmit memory address the symbol A is used instead of AD for example AO- A15. + A16 - A19 (Output): High order address lines. These are multiplexed with status signals. + A16/S3, A17/S4: A16 and A17 are multiplexed with segment identifier signals $3 and S4.18/5: A18 is multiplexed with interrupt status SS. 19/36: A19 is multiplexed with status signal S6. BHE/S7 (Output): Bus High Enable/Status. During 71, it is low. It enables the data onto the most significant half of data bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE signal. It is multiplexed with status signal S7. S7 signal is available during T3 and 14. RD (Read): For read operation. It is an output signal. It is active when LOW. Ready (Input): The addressed memory or I/O sends acknowledgement through this pin. When HIGH it denotes that the peripheral is ready to transfer data. RESET (Input): System reset. CLK (input): Clock 5, 8 or 10 MHz. INTR: Interrupt Request. NMI (Input): Non-maskable interrupt request. TEST (Input): Wait for test control. When LOW the microprocessor continues execution otherwise waits. VCC: Power supply +SV de. GND: Ground.Unit Il Introduction to Assembly Language Programming Assembly Language Programming Basics ‘An assembly language is the most basic programming language available for any processor. With assembly language, a programmer works only with operations that are implemented directly on the physical CPU. Assembly languages generally lack high-level conveniences such as variables and functions, and they are not portable between various families of processors. They have the same structures and set of commands as machine language, but allow a programmer to use names instead of numbers. This language is still useful for programmers when speed is necessary or when they need to carry out an operation that is not possible in high-level languages. ‘Assembly language is specific to a given processor. For e. different than that of Motorola 6800 microprocessor. assembly language of 8085 is Microprocessor cannot understand a program written in Assembly language. A program known as Assembler is used to convert Assembly language program to machine language. ‘Assembly Machine Language ——+ “ssembler __ Language Program fog Code Assembly language program to add two numbers MVIA, 2H ;Copy value 2H in register A MVI.B, 4H ;Copy value 4H in register B ADDB JA=A+B Advantages of Assembly Language a) The symbolic programming of Assembly Language is easier to understand and saves a lot of time and effort of the programmer. b)_Itis easier to correct errors and modify program instructions. ©) Assembly Language has the same efficiency of execution as the machine level language. Disadvantages of Assembly Language a) One of the major disadvantages is that assembly language Is machine dependent. A program written for one computer might not run in other computers with different hardware configuration. b) If you are programming in assembly language, you must have detailed knowledgeof the particular microcomputer you are using. ©) Assembly language programs are not portable. Instruction Set of 8085 An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions that a microprocessor supports is called Instruction Set. 8085 has 246 instructions. Each instruction is represented by an 8-bit binary value. These 8-bits of binary value is called Op-Code or Instruction Byte. Following are the classification of instructions: a) Data Transfer Instruction b) Arithmetic Instructions ¢) Logical Instructions d) Branching Instructions e) Control Instructions a) Data Transfer Instruction ‘These instructions move data between registers, or between memory and registers. These instructions copy data from source to destination. While copying, the contents of source are not modified. Example: MOV, MVI b) Arithmetic Instructions These instructions perform the operations like addition, subtraction, increment and decrement. Example: ADD, SUB, INR, DCR ¢) Logical Instructions These instructions perform logical operations on data stored in registers and memory. The logical operations are: AND, OR, XOR, Rotate, Compare and Complement. Example: ANA, ORA, RAR, RAL, CMP, CMA d) Branching Instructions Branching instructions refer to the act of switching execution to a different instruction sequence as a result of executing a branch instruction. The three types of branching : Jump, Call and Return. e) Control Instructions The control instructions control the operation of microprocessor. Examples: HLT, NOP, El (Enable Interrupt), DI (Disable interrupt).Arithmetic Instructions Instruction | Opcode | Addressing Bytes | Description Mode ADDA 87 Register 1 it adds the content stored in given register with the accumulator. The result of this addition is stored in accumulator. ADDB 80 Register 1 ADD C 81 Register 1 ADDD 82 Register 1 ADDE 83 Register 1 ADDH 84 Register 1 ADDL 85 Register 1 ADDM | 86 Register Indirect |1 __ | adds the content of memory location whose address is given in H-L register pair with the accumulator and the answer is stored in accumulator. ADI data | C6 Immediate 2 itimmediately adds the given data with the accumulator and the answer will be stored in Accumulator. ADCA C6 Register 1 A=A+A+CY (Add with carry) ADCB 8F Register 1 A-A#BHCYADCC 88 Register ADCD 89 Register ADCE 8B Register ADCH 8c Register ADCL 8D Register ADCM 8E Register Indirect ACidata__ | CE Immediate DADB 09 Register HL=HL4BC DADD 19 Register HL=HL+DE DADH 29 Register HL=HUHL SUBA 97 Register A=A-A SUBB 90 Register A=A-B sUBC 91 Register ‘SUBD 92 Register SUBE 93 Register SUBH 94 Register SUBL 95 Register suBM 96 Register Indirect sul data | D6 Immediate SBBA oF Register A=A-A-CY ‘SBBB 98 Register A=A-B-CY SBBC 99 RegisterSBBH 9c Register SBBL 9D Register SBBM 9 Register Indirect ‘SBI data DE Immediate INRA 3C Register AZAHL INRB 04 Register B=B+1 INR C oc Register INR D 14 Register INRE 1c Register INR H 24 Register INRL 2c Register INRM 34 Register Indirect M=M#1 (pointed by HL) INX B 03 Register| BC=BC+1 INXD 13 Register DESDE INXH 23 Register HL=HLAL DCRA 3D Register A=A-1 DCRB 05 Register DCRC oD Register DCRD 15 Register DCRE 1D Register DCRH 25 Register DCRL 20 Register DCRM 35 Register Indirect M=M-11 BC=BC-1DCXH 28 Register 1 HL=HL-1 RAL 17 Implied/implicit | 4 Rotate accumulator left RAR 1F Implied/implicit | 1 Rotate accumulator right RLC o7 Implied/implicit | 1 Rotate accumulator left through carry RRC OF implied/implicit | 1 Rotate accumulator right through carry Total=65 Logical Instructions Instruction | Opcode | Addressing Bytes | Description Mode ANAA AT Register 1 A=AAND A ANAB a0 Register 1 A=A AND B ANAC Al Register 1 ANAD A2 Register 1 ANAE a3 Register 1 ANAH Aa Register al ANAL AS Register 1 ANAM — | A6 Register 1 Indirect ANIdata | E6 Immediate 2 A=A AND data ORAA B7 Register 1 A=AORA ORAB BO Register 1 A=AORB ‘ORAC BL Register 1 ‘ORAD B2 Register 1ORAL BS Register ORAM BG Register Indirect ORidata | F6 Immediate XRAA AF Register A=AXOR A XRAB Ag Register A=AXOR B XRAC Ag Register XRAD AA Register XRAE AB Register XRAH AC Register XRAL AD Register XRA M. AE Register Indirect xRi data | EE Immediate cP A BF Register ‘A=A-A (Accumulator remain unchanged) CMP B B8 Register A=AB CMP C B9 Register CMP D BA Register CMP E BB Register MPH BC Register MPL BD Register cMPM — | BE CPidata | FE Immediate A=A-data (Acc. Remain unchanged) MA 2F Implied /implicit Complement Accumulator contents CMC 3F Implied /implicit Complement Carry flagSTC 37 Implied implicit » C¥=1 (It sets carry flag) Total=39 CA NotesBranching Instructions Instructio | Opco | Addressin] Byt | Description n de |g es Mode JMP- a Immediat | 3 Unconditional Jump: address e JCaddress| DA | Immediat |__| Jump if CY=1 e INC D2 | immediat|3 | Jump if CY=0 address e JZ address) CA Immediat | 3 Jump if Z=1 e JNZ a Immediat | 3 Jump if Z=0 address e JM FA | immediat |3__ | Jump if S=1 address e JPaddress| F2 | Immediat 3 | Jump if S=0 e JPE EA Immediat | 3 Jump if P=1 address e IPO —2 Immediat | 3 Jump if P=0 address e CALL cD | immediat 3 | Unconditional Call address e ce DC | immediat|3 | Call Subroutine if CY=1 address e CNC D4 Immediat | 3 Call Subroutine if CY¥=0 address e [or CC [immediat [3 | Call Subroutine if 2=1 address e NZ C4 | immediat | 3 | Call Subroutine if 2=0 address e cm FC | Immediat [3 _ | Call Subroutine if S=1 address e cP Fa Immediat | 3 Call Subroutine if S=O address e CPE EC | immediat |3 | Call Subroutine if P=1 address e cPO FE | Immediat [3 _ | Call Subroutine if P=1 address e | | RNZ oO _| Register [1 | Return to main program if Z=0Indirect RZ C8 | Register Return to main program if Z= Indirect RNC DO | Register Return to main program if Indirect RC D8 | Register Return to main program if C= Indirect.RM F8 Register 1 Return to main program if S=1 Indirect RP FO Register 1 Return to main program if =O Indirect RPO EO Register 1 Return to main program if P=O Indirect RPE EB Register 1 Return to main program if P=1 Indirect Total=26 Program Control & Stack Instructions Instruction | Opcode | Addressing Bytes | Description Mode PUSHB | C5 Register 1 PUSH data from data from stack on the basis of Indirect address pointed by BC pair. PUSHD | D5 Register 1 Indirect PUSHH | ES Register 1 Indirect POP B ca Register 1 POP data from data from stack on the basis of Indirect address pointed by BC pair. POP D Di Register 1 Indirect POP H El Register 1 Indirect NOP 00 Implied/Implicit | 1 No operation is performed HLT 76 Implied/Implicit | 1 Terminate program DI F3 Implied/Implicit | 1 el 78 Implied/Iimplicit | 1 RIM 20 Implied/Implicit | 1 Read interrupt mask (read status of interrupt) SIM 30 Implied/implicit | 2 Set interrupt mask (used to implement interrupt)8085 Programs 1. Program to add two 8-bit numbers. Statement: Add numbers OSH & 13H and display result in output port 03H. MVIA,0SH —_//Move data OSH to accumulator MVIB,13H —_//Move data 13H to B register ADD B /JAdd contents of accumulator and B register QUT 03H —_//Transfer result to output port 03H HUT /[Terminate the program. Input: A=0SH B=13H Output: (port 03H) = 18H 2. Program to add two 8-bit numbers. Statement: Add numbers from memory location 2050H & 2051H and store result inmemory location 2055H. LDA2051H —_//Load contents of memory location 2051 to accumulator MOV B,A //Move contents of accumulator to B register LDA 2050H —_//Load contents of memory location 2050 to accumulator ADDB // Add contents of accumulator and B register STA 205SH /|Store contents of accumulator in memory location 205SH HLT //Terminate the program. Input: MemoryLocation Data 2050H 45H 2051H 53H Output: Memory Location Data 2055H 8H 3. Program to subtract two 8-bit numbers. Statement: Subtract numbers 25H & 12H and display result in output port 01H. MVIA,25H —_//Move data OSH to accumulator MVIB,12H — //Move data 13H to B register SUBB //Add contents of accumulator and B register OUT 01H //Transfer result to output port 01H HLT //Terminate the program. Input: A=2SH B=12H Output: (port 03H) 4. Program to subtract two 8-bit numbers.Statement: Subtract numbers from memory location 2050H & 2051H and store result in memory location 2055H. LDA 2051H —_//Load contents of memory location 2051 to accumulator MOVB,A //Move contents of accumulator to B register LDA 2050H —_//Load contents of memory location 2050 to accumulator SUBB // Add contents of accumulator and B register STA2055H _//Store contents of accumulator in memory location 2055H HLT /[Terminate the program. Input Memory Location Data 20S50H 65H 53H MemoryLocation Data 2055H 12H Program to find 1’s complement of a number. Statement: Input number from memory location 2013H and store result in memory location 2052H. LDA 2013H —_//Load contents from memory location 2013H to accumulator cma //Complement contents of accumulator STA 2052H —_//Store result in memory location 2052H HLT //Terminate the program. input: MemoryLocation Data 2013H 22H Output: MemoryLocation Data 2052H EDH Program to find 2’s complement of a number. Statement: Input number from memory location 2013H and store result in memory location 2052H. LDA 2013H —_//Load contents from memory location 2013H toaccumulator CMA //Complement contents of accumulator ADIO1H //Add 01H to the contents of accumulator STA 2052H _//Store result in memory location 2052H HLT //Terminate the program. Inu Memory Location Data2013H 12H Qutput Memory Location Data 2052H EEH Program to right shift 8-bit numbers. Statement: Shift an eight-bit data four bits right. Assume data is in memory location 2051H. Store result in memory location 2055H. LDA 2051H —_//Load data from memory location 2051H to accumulator RAR //Rotate accumulator 1-bit right RAR RAR RAR STA205SH —_//Store result in memory location 2055H HLT /[Terminate the program. 8. Programto left shift 8-bit numbers. Statement: Shift an eight-bit data four bits left. Assume data is in memory location 2051H. Store result in memory location 2055H. LDA2051H —_//Load data from memory location 2051H to accumulator RAL //Rotate accumulator 1-bit left RAR RAR RAR STA 205SH //Store result in memory location 205SH HLT //Terminate the program. 9. Program to add two 16-bit numbers. Statement: Add numbers 1124H & 2253H and store result in memory location 2055H & 2056H. LXIH,1124H — //Load 16-bit data 1124H to HL pair LXLD,2253H —//Load 16-bit data 2253H to DE pair MOV A,L //Move contents of register L to Accumulator ADDE /JAdd contents of Accumulator and E register MOVL,A —_//Move contents of Accumulator to L register MOV A,H //Move contents of register H to Accumulator ADCD //Add contents of Accumulator and D register with carry MOV HA //Move contents of Accumulator to register H SHLD 205SH__//Store contents of HL pair in memory address 205SH & 2056H HLT //Terminate the program. np Register Pair DataHL 1124H DE 2253H Output: Memory Location Data 205SH 77H 2056H 33H 10. Program to add two 16-bit numbers. Statement: input first number from memory location 2050H & 2051H and second number from memory location 2052H & 2053H and store result in memory location 2055H & 2056H. LHLD 2052H //Load 16-bit number from memory location 2052H & 2053H to HL pair XCHG /JExchange contents of HL pair and DE pair LHLD 2050H _//Load 16-bit number from memory location 2050H & 2051H to HL pair MOVA,L //Move contents of register L to Accumulator ADDE /JAdd contents of Accumulator and E register MOVLA //Move contents of Accumulator to L register MOVA,H —_//Move contents of register H to Accumulator ADCD /JAdd contents of Accumulator and D register with carry MOVH,A —_//Move contents of Accumulator to register H SHLD 2055H_//Store contents of HL pi in memory address 2055H & 2056H HLT //Terminate the program. Input: Memory Location Data 2050H 33H 2051H 45H 2052H 24H 2053H 34H Outpu' Memory Location Data 2055H 57H 2056H 79H 11. Program to subtract two 16-bit numbers. Statement: Subtract number 1234H from 4897H and store result in memory location 2055H & 2056H. LX H,4567H_ //Load 16-bit data 4897H to HL pair LX1D,1234H //Load 16-bit data 1234H to DE pair MOVA,L //Move contents of register L to Accumulator SUBE //Subtract contents of Accumulator and E registerMOVLA //Move contents of Accumulator to L register MOV A,H //Move contents of register H to Accumulator SBBD //Subtract contents of Accumulator and D register with borrow MOV HA //Move contents of Accumulator to register H SHLD 2055H _//Store contents of HL pair in memory address 2055H & 2056H HLT //Terminate the program. Input: Register Pair Data HL 4897 DE 1234H Output: Memory Location Data 2055H 63H 2056H 36H 12. Program to subtract two 16-bit numbers. Statement: input first number from memory location 2050H & 2051H and second number from memory location 2052H & 2053H and store result in memory location 2055H & 2056H. LHLD 2052H //Load 16-bit number from memory location 2052H & 2053H to HL pair XCHG //Exchange contents of HL pair and DE pair LHLD 2050H //Load 16-bit number from memory location 2050H & 2051H to HL pair MovA,L —_//Move contents of register L to Accumulator SUBE //Subtract contents of Accumulator and E register MOV LA //Move contents of Accumulator to L register MOVA,H —_//Move contents of register H to Accumulator SBBD //Subtract contents of Accumulator and D register with carry MOVH,A —_//Move contents of Accumulator to register H SHLD 2055H _//Store contents of HL pair in memory address 2055H & 2056H HLT //Terminate the program. Input: Memory Location Data 20504 78H 2051H 45H 2052H 24H 2053H 34H Outpu' Memory Location Data 2055H 54H 2056H 11H13. Program to multiply two 8-bit numbers. ‘Statement: Multiply 06 and 03 and store result in memory location 205SH. MvIA,0OH MMvi B,06H MIV C,03H X: ADD B DcRC JNZX STA 2055H HLT Program to divide to 8- bit numbers. Statement: Divide 0H and 03H and store quotient in memory location 205SH and remainder in memory location 2056H. MvI A,08H MvI B,03H MvI C,00H X: CMP B Jey SUBB INRC JMP X Y: STA 2056H MOV A,C STA 2055H HLT 14, Program to find greatest among two 8-bit numbers. Statement: Input numbers from memory location 2050H & 2051H and store greatest number in memory location 2055H. LDA 2051H MOVB,A LDA 2050H CMP 8 JNCX MOVA.B X: STA 205SH HLT15. Program to find smallest among two 8-bit numbers. ‘Statement: Input numbers from memory location 2050H & 2051H and store smallest number in memory location 2055H. LDA 2051H MOV B.A LDA 20S0H CMP 8 JCx MOVA,B X: STA 2055H HLT 16, Program to find whether 2 number is odd or even. Statement: Input number from memory location 20SOH and store result in 2055H. LDA 2050H ANI O1H JSZxX MVIA,ODH JMPY X: MVIA,OEH Y: STA 2055H HLT 17. Program to count no. of 1’s in given number. Statement: Input number from memory location 20S0H and store result in 205SH. LDA 2050H MVI.C,08H MVIB,00H X: RAR JNCY INRB Y: DER C JNZX MOVA,B STA 205SH HUT 18. Display number from 1 to 10. LX H,2050H MvIB,01H MvICOAH X: MOV MB. INX H19. 20. 21. 22. INR B DCR C INZX HIT Find sum of numbers from 1to 10. LM H,2050H MvIB,01H MMVI. COAH MvIA,OOH X: ADD B. INX H INR B DCR C INZX STA 2055H HIT Display all odd numbers from 1 to 10. Lx H,2050H Mv 8014 MVICOAH X: MOV M,B INXH INRB INR B DCRC DCRC JNZX HUT Display all even numbers from 1 to 20. LX H,2050H MvIB,02H Mvic14H X: MOV M,B INX H INR B INR B DCR C DCR C INZX HUT Display all even numbers from 10 to.50. LX H,2050H MV OAHMvIC32H X: MOV MB INX INR B INR B DCR C DCRC INZX HIT 23. Find sum of 10 numbers in array. Lt H,2050H. MMVI COAH MVIA,0OH X: MOV BM ADD B INX H DCRC INZX STA 20604 HUT 24, Find the largest element in a block of data. The length of the block is in the memory location 2200H and block itself starts from memory location 2201H. Store the maximum number in memory location 2300H. LDA 2200H MOV CA Lx H.2201 MVIA,00H X: CMP M JNCY MOV AM Ys INX H DCRC JNZX STA 2300H HUT 25. Find smallest number in array. LDA 22004 MOV CA LX H,2201H MVIAOOH xX: CMP M icy Mov AM Y:INXH DCRCINZX STA 2300H HLT 26. Generate Fibonacci series upto 10" term. LXI H,2050H| MVIC08H MvIB,00H Mv1 0,014 MOVM,B INKH MOV M,D X: MOV AB ‘ADD D Mov BD Mov D,A INXH Mov MA DCRC JNZX HUT 27. Sort 10 numbers in ascending order in array. MvIC,0AH DCRC X: MOV D,C LXI H,2050H Y:MOV AM INXH. CMP M JCZ MOV B,M MOV MA. DCKH MOV M,B INX H Z:DCRD JNZY DCRC JNZX HLT 28. Sort numbers in descending order in array. Length of array isin memory location2050H. LDA 2050H MVIGA DCR C X: MOV D,C LXIH,2051H Y: MOV A.M INX H CMP M JNCZ MOV B,M MOV M,A. DCKH MOV M,B INX H Z:DCRD JNZY DCRC JNZX HLT 29. Multiply two 8 bit numbers 43H & 07H. Result is stored at address 3050 and 3051. LXI H,0000H MVI D,00H MVIE,43H MVIC,07H X: DAD D perc JNZX SHLD 2050H HLT 30. Multiply two 8 bit numbers stored at address 2050 and 2051. Result isstored at address 3050 and 3051. LDA 2050H MOVE,A LDA 2051H MOVGAMMVI D,00H LX H,0000H X: DAD D DCRC INZX SHLD 3050H HUTUnit Ill Basic Computer Architecture Introduction to Computer Architecture Computer architecture is a specification detailing how a set of software and hardware technology standards interact to form a computer system or platform. In short, computer architecture refers to how a computer system is designed and what technologies it is compatible with ‘As with other contexts and meanings of the word architecture, computer architecture is likened to the art of determining the needs of the user/system/technology, and creating a logical design and standards based on those requirements. ‘A very good example of computer architecture is von Neumann architecture, which is still used by most types of computers today. This was proposed by the mathematician John von Neumann in 1945. It describes the design of an electronic computer with its CPU, which includes the arithmetic logic unit, control unit, registers, memory for data and instructions, an input/output interface and external storage functions. ‘There are three categories of computer architecture: a) System Design: This includes all hardware components in the system, including data processors aside from the CPU, such as the graphics processing unit and direct memory access. It also includes memory controllers, data paths and miscellaneous things like multiprocessing and virtualization. b) Instruction Set Architecture (ISA): This is the embedded programming language of the central processing unit. It defines the CPU's functions and capabilities based on what programming it can perform or process. This includes the word size, processor register types, memory addressing modes, data formats and the instruction set that programmers use Microarchitecture: Otherwise known as computer organization, this type of architecture defines the data paths, data processing and storage elements, as well as how they should be implemented in the ISA. History of Computer Architecture The first document of Computer Architecture was a correspondence between Charles Babbage and Ada Lovelace, that describes the analytical engine. Here is the example of other early important machines: John Von Neumann and Alan Turing. Computer architecture is the art of determining the needs of the user of a structure and then designing to meet those needs as effectively as possible with economic status and as well 2s the technological constraints. In ancient period, computer architectures were designed and prepared on the paper and then, directly built into the final hardware form.Later, in today's computer architecture, prototypes were physically built in the form of transistor logic (TTL] computer such as the prototypes of the 6800 and the PA-RISC tested, and tweaked before committing to the final hardware form Harvard Architecture The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. The term originated from the Harvard Mark |, which stored instructions on punched tape and data in electro-mechanical counters. These early machines had data storage entirely contained within the central processing unit, and provided no access to the instruction storage as data. it required two memories for their instruction and data. Harvard architecture requires separate bus for instruction and data. Instruction Control Data Memory Unit Memory vo Harvard Model Von Neumann architecture Von Neumann architecture was first published by John von Neumann in 1945. His computer architecture design consists of a Control Unit, Arithmetic and Logic Unit (ALU), Memory Unit, Registers and Inputs/Outputs. Von Neumann architecture is based on the stored-program computer concept, where instruction data and program data are stored in the same memory. This design Is still used in most computers produced today. The modern computers are based on a stored-program concept introduced by John Von Neumann. In this stored-program concept, programs and data are stored in a separate storage unit called memories and are treated the same. Von Neumann architecture requires only one bus for instruction and data.Control Unit ALU Memory Unit Von Neumann Model Overview of Computer Organization Computer organization refers to the operational units and their interconnection that realize the architecture specification. Computer organization deals with physical aspects of computer design, memory and their types and microprocessors design. Computer organization is concerned with the way the hardware components operate and the way they are connected together to form a computer system. It describes how the computer performs. Ex, circuit design, control signals, memory types and etc. Computer Organization vs Architecture 1) Computer Architecture refers to those attributes of a system that have a direct impact on the logical exect - the instruction set - the number of bits used to represent various data types - 1/0 mechanisms - memory addressing techniques on of a program. Examples: Computer Organization refers to the operational units and their interconnections that realize the architectural specifications. Examples are things that are transparent to the programmer: - control signals - interfaces between computer and peripherals - the memory technology being used. 2) So, for example, the fact that a multiply instruction is available is a computer architecture issue. How that multiply is implemented is 2 computer organization issue.3) Architecture is those attributes visible to the programmer - _ Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques. e.g. Is there a multiply instruction? Orga n is how features are implemented - Control signals, interfaces, memory technology. e.g. Is there a hardware multiply unit or is it done by repeated addition? 4) Computer arc! system as seen by the user. fecture is concerned with the structure and behavior of computer Computer organization is concerned with the way the hardware components operate and the way they are connected together to form a computer system. Memory Hierarchy ‘The memory unit Is an essential component in any digital computer since It Is needed for storing programs and data. A very small computer with an unlimited application may be able to fulfill its intended task without the use of additional storage capacity. Most general Purpose computers would run more efficiently if they were equipped with additional storage beyond the capacity of the main memory. There is just not enough space in one memory unit to accommodate all the programs used in a typical computer. Moreover, most computer users accumulate and continue to accumulate large amounts of data-processing software. Not all accumulated information is needed by the processor at the same time. Therefore, it is more economical to use low-cost storage devices to serve as a backup for storing the information that is not currently used by the CPU. The memory unit that communicates directly with the CPU is called the main memory. Devices that provide backup storage are called auxiliary memory. The most common auxiliary memory devices used in computer systems are magnetic disks and tapes. They are used for storing system programs, large data files, and other backup information. Only programs and data currently needed by the processor reside in main memory. All other information Is stored in auxiliary memory and transferred to main memory when needed.Register Memory Increasing order of access time ratio Main Memory Primary Memory } Auxillary Memory Magnetic TapesFigwe 12.1 Memory hiewschy in compurer ayer. Si 3 Weesn Mabe Ea— —_ a ‘ss | The total memory capacity of a computer can be visualized as b components. The memory hierarchy system consists of all storage devices employed in a computer system from the slow but high-capacity auxiliary memory to a relatively faster main memory, to an even smaller and faster cache memory accessible to the high-speed processing logic. Above Figure illustrates the components in a typical memory hierarchy. At the bottom of the hierarchy are the relatively slow magnetic tapes used to store removable files. Next are the magnetic disks used as backup storage. The main memory occupies a central position by being able to communicate directly with the CPU and with auxiliary memory devices through an I/O processor. When programs not residing in main memory are needed by the CPU, theyare brought in from auxiliary memory. Programs not currently needed in main memory are transferred into auxiliary memory to provide space for currently used programs and data. speed memory called a Cache is sometimes used to increase the speed of processing by making current programs and data available to the CPU at a rapid rate. The cache memory is employed in computer systems to compensate for the speed differential between main memory access time and processor logic. CPU logic is usually faster than main memory access time, with the result that processing speed is limited primarily by the speed of main memory. A technique used to compensate for the mismatch in operating speeds is to employ an extremely fast, small cache between the CPU and main memory whose access time Is dose to processor logic dock cycle time. The cache is used for storing segments of programs currently being executed in the CPU and temporary data frequently needed in the present calculations. If the active portions of the program and data are placed in a fast small memory, the average memory access time can be reduced, thus reducing the total execution time of the program. Such a fast small memory is referred to as a cache memory. It is placed between the CPU and main memory as illustrated in Fig. below. The cache memory access time isless than the access time of main memory by a factor of 5 to 10. The cache is the fastest component in the memory hierarchy and approaches the speed of CPU components. The basic operation of the cache is as follows. When the CPU needs to access memory, the cache is examined. If the word is found in the cache, it is read from the fast memory. If the word addressed by the CPU is not found in the cache, the main memory is accessed to read the word. A block of words containing the one just accessed is then transferred from main memory to cache memory. The block size may vary from one word (the one just accessed) to about 16 words adjacent to the one just accessed. In this manner, some data are transferred to cache so that future references to memory find the required words in the fast cache memory. Figure 12-10 Example of cache memory. The main memory can store 32K words of 12 bits each. The cache is capable of storing 512 of these words at any given time. For every word stored in cache, there is a duplicate copy in main memory. The CPU communicates with both memories. It first sends a 15-bit address to cache. If there is a hit, the CPU accepts the 12-bit data from cache. If there is a miss, the CPU reads the word from main memoryand the words then transferred tocache. Abhard disk drive (HDD) is a non-volatile computer storage device containing magnetic disks or platters rotating at high speeds. It is a secondary storage device used to store data permanently. Non-volatile means data is retained when the computer is turned off. A hardFigure Magnetic disk. disk drive is also known as a hard drive. A hard drive consists of the following: Magnetic platters - Platters are the round plates in the image above. Each platter holds a certain amount of information, soa drive a lot of storage will have more platters than one with ess storage. When information is stored and retrieved from the platters it is done soin concentric circles, called tracks, which are further broken down into segments called sectors. Arm - The arm is the piece sticking out over the platters. The arms will contain read and write heads which are used to read and store the magnetic information onto the platters. Each platter will have its own arm which is used to read and write data off of it. Motor - The motor is used to spin the platters from 4,500 to 15,000 rotations per minute (RPM). The faster the RPM of a drive, the better performance you will achieve from it. When a computer wants to retrieve data off of the hard drive, the motor will spin up the platters and the arm will move itself to the appropriate position above the platter where the data is stored. The heads on the arm will detect the magnetic bits on the platters and convert them into the appropriate data that can be used by the computer. Conversely, when data is sent to the drive, the heads will this time, send magnetic pulses at the platters changing the magnetic properties of the platter, and thus storing your information. Instruction Code An instruction code is a group of bits that instruct the computer to perform a specific ided into parts, each having its own particular interpretation. The operation. It is usuallymost basic part of an instruction code is its operation part. The operation code of an instruction is a group of bits that define such operations as add, subtract, multiply, shift, and complement. The number of bits required for the operation code of an instruction depends on the total number of operations available in the computer. Instruction codes together with data are stored in memory. The computer reads each instruction from memory and places it in a control register. The control then interprets the binary code of the instruction and proceeds to execute it by issuing a sequence of micro operations. Every computer has its own unique instruction set. The ability to store and execute instructions, the stored program concept, is the most important property of a general-purpose computer. The operation part of an instruction code specifies the operation to be performed. This operation must be performed on some data stored in processor registers or in memory. An instruction code must therefore specify not only the operation but also the registers or the memory words where the operands are to be found, as well as the register or memory word where the result is to be stored. Stored Program Organization The simplest way to organize a computer is to have one processor register and an instruction code format with two parts. The first part specifies the operation to be performed and the second specifies an address. The memory address tells the control where to find an operand in memory. This operand is read from memory and used as the data to be operated on together with the data stored in the processor register. Below figure depicts this type of organization. Instructions are stored in one section of memory and data in another. For amemory unit with 4096 words we need 12 bits to specify an address since 2"? = 4096. If we store each instruction code in one 16-bit memory word, we have available four bits for the operation code (abbreviated opcode) to specify one out of 16 possible operations, and 12 bits to specify the address of an operand. The control reads a 16-bit instruction from the program portion of memory. It uses the 12-bit address part of the instruction to read a 16-bit operand from the data portion of memory. It then executes the operation specified by the operation code.Figure 5-1 Stored program organization. Memory dopants ° [_ovose [ Asores Instructions (program) Insructon format 1s ° Binary operand ome Processor registe (accumulator or AC) Indirect Address It is sometimes convenient to use the address bits of an instruction code not as an address but as the actual operand. When the second part of an instruction code specifies an operand, the instruction is said to have an immediate operand. When the second part specifies the address of an operand, the instruction is said to have a direct address. This is in contrast to a third possibility called indirect address, where the bits in the second part of the instruction designate an address of a memory word in which the address of the operand is found. In register indirect addressing mode, the data to be operated is available inside a memory location and that memory location is indirectly specified by a register pair. Example: MOV A, M (move the contents of the memory location pointed by the H-L pair to the accumulator) Computer Registers Registers are the fastest and smallest type of memory elements available to a processor. Registers are normally measured by the number of bits they can hold, for example, an "8- bit register", "32-bit register" or a "64-bit register” (or even with more bits). A processor often contains several kinds of registers, which can be classified according to their content or instructions that operate on them.TABLE 51 List of Registers for the Basic Computer Register Number symbol of bits Register name Function DR 16 Data register Holds memory operand AR 12 Address register Holds address for memory AC 16 Accumulator Processor register IR 16 Instruction register Holds instruction code PC 12 Program counter _-Holds address of instruction TR 16 Temporary register Holds temporary data INPR 8 Input register Holds input character OUTR 8 Output register Holds output character Common Bus System The basic computer has eight registers, a memory unit, and a control unit. Paths must be provided to transfer information from one register to another and between memory and registers. The number of wires will be excessive if connections are made between the outputs of each register and the inputs of the other registers. A more efficient scheme for transferring information in a system with many registers is to use a common bus. Four registers, DR, AC, IR, and TR, have 16 bits each. Two registers, AR and PC, have 12 bits each since they hold a memory address. When the contents of AR or PC are applied to the 16-bit common bus, the four most significant bits are set to O's. When AR or PC receive information from the bus, only the 12 east significant bits are transferred into the register.Figure 1.4 Basic registers which are connected to a common bus The input register INPR and the output register OUTR have 8 bits each and communicate with the eight least significant bits in the bus. INPR is connected to provide information to the bus but OUTR can only receive information from the bus. This is because INPR receives a character from an input device which is then transferred to AC. OUTR receives acharacter from AC and delivers it to an output device. There is no transfer from OUTR to any of the other registers. The 16lines of the common bus receive information from six registers and the memory unit. The bus lines are connected to the inputs of six registers and the memory. Five registers have three control inputs: LD (load), INR {increment}, and CLR (clear). The input data and output data of the memory are connected to the common bus, but the memory address is connected to AR. Therefore, AR must always be used to specify amemory address. By using a single register for the address, we eliminate the need for an address bus that would have been needed otherwise. The content of any register can be specified for the memory data input during a write operation. Similarly, any register can receive the data from memory after a read operation except AC. iming and Control The timing for all registers in the basic computer is controlled by a master clock generator. The clock pulses are applied to all flip-flops and registers in the system, including the flip- flops and registers in the control unit. The clock pulses do not change the state of a register unless the register is enabled by a control signal. The control signals are generated in the control unit and provide control inputs for the multiplexers in the common bus, control inputs in processor registers, and micro operations for the accumulator. Instruction Cycle Time required to execute and fetch an entire instruction is called instruction cycle._A program residing in the memory unit of the computer consists of a sequence of instructions. The program is executed in the computer by going through a cycle for each instruction. Each instruction cycle in turn is subdivided into a sequence of sub cycles or phases. In the basic computer each instruction cycle consists of the following phases: 1. Fetch an instruction from memory. 2. Decode the instruction. 3. Read the effective address from memory if the instruction has an indirect address. 4. Execute the instruction.INIT IV — Microprogramm: ntrol Microprogrammed vs Hardwired Control ‘A hardwired control differs from microprogrammed control in lowing ways: HARDWIRED CONTROL UNIT MICROPROGRAMMED CONTROL UNIT ‘The control unit whose control signals are generat The control unit whose control signals are generated by the hardware through a sequence of in called a hardwi 1e data stored in control memory and constitute a ‘The control leg Implemented with gates, rogrammed controls the control memory to rations. Chan. rammed control unit are done updating the microprogram in control memory. Ingee are made in the harch if there are any changes required in the design, Hardwired control unit are faster and known to hi complex structure. cones med control unit & comparatively siow re imo) instructure Terminologies Hardwired Control Unit: When the control signals are generated by hardware using conventional logic design techniques, the control unit is said to be hardwired. Micro programmed control unit: A control unit whose binary control va Programmed control unit. bles are stored in memory is called a micro Control Memory: Control Memory is the storage in the microprogrammed control unit to store the microprogram. Control Word: The control variables at any given time can be represented by a control word string of 1's and 0's called a control word. Microoperation: Micro-operations perform basic operations on data stored in one or more registers,including transferring data between registers or between registers and external buses of the central processing unit (CPU), and performing arithmetic or logical operations on registers. Microcod: Avery low-level instruction set which is stored permanently in a computer or peripheral controller and controls the operation of the device. Microinstruction A single instruction in microcode. it is the most elementary instruction in the computer, such as moving the contents of a register to the arithmetic logic unit (ALU). Microprogram A set or sequence of microinstructions. Design of Basic Computer The basic computer consists of the following hardware components: + Amemory unit with 4096 words of 16 bits each. ‘ Nine registers: AR(Address Reg.), PC (Program Counter), DR(Data Reg.), AC (Accumulator), IR (instruction Reg.), TR (Temp. Reg.), OUTR (Output Reg.), INPR (Input Reg.), and SC (Sequence Counter). Flip-flops: IEN (Interrupt Enable), FGI (Input Flag), and FGO (Output Flag). Two decoders: a 3 x8 operation decoder and a 4 x 16 timing decoder A.16-bit common bus. Control logic gates. Adder and logic circuit connected to the input of AC. Sooo es Design of Accumulator Logic ‘ The circuits associated with the AC register are shown in Fig. The adder and lo; circuit has three sets of inputs. One set of 16 inputs comes from the outputs of AC. Another set of 16 inputs comes from the data register DR. A third set of eight inputs comes from the input register INPR. The outputs of the adder and logic circuit provide the data inputs for the register. In addition, it is necessary to include logic gates for controlling the LD, INR, and CLR in the register and for controlling the operation of the adder and logic circuit.Figure 5-20 Gate structure for controlling the LD, INR, and CLR of AC. From adder _!6 6 = +f ac | 2+ Topas — — no { e——_ ww fine jar > App > pe Ts [se rH com % > an Control of AC Register - Gate Structure “ The gate structure that controls the LD, INR, and CLR inputs of ACis shown in Fig. ‘The output of the AND gate that generates this control function is connected to the CLR input of the register. Similarly, the output of the gate that implements the increment micro operation is connected to the INR input of the register. “The other seven micro operations are generated in the adder and logic circuit and are loaded into AC at the proper time. “ The outputs of the gates for each control function is marked with a symbolic name. These outputs are used in the design of the adder and logic circuit. ALU Organization “ Various circuits are required to process data or perform arithmetical operations which are connected to microprocessor's ALU. “* Accumulator and Data Buffer stores data temporarily. These data are processed as. per control instructions to solve problems. Such problems are addition, multiplication etc.enc Functions of ALU: Functions of ALU or Arithmetic & Logic Unit can be categorized into following 3 categories: 1. Arithmetic Operations: Additions, multiplications etc. are example of arithmetic operations. Finding greater than or smaller than or equality between two numbers by using subtraction is also a form of arithmetic operations. 2. Logical Operations: Operations like AND, OR, NOR, NOT etc. using logical circuitry are examples of logical operations. 3, Data Manipulations: Operations such as flushing a register is an example of data manipulation. Shifting binary numbers are also example of data manipulation. Control Memory “* Acomputer that employs a microprogrammed control unit will have two separate memories: a main memory and a control memory. > The main memory is available to the user for storing the programs. The contents of main memory may alter when the data are manipulated and every time that the program is changed. The user's program in main memory consists of machine instructions and data. In contrast, the control memory holds a fixed microprogram that cannot be altered by the occasional user. The microprogram consists of microinstructions that specify ° various internal control signals for execution of register microoperations. * Each machine instruction initiates a series of microinstructions in control memory. These microinstructions generate the microoperations to fetch the instruction from main memory; to evaluate the effective address, to execute the operation specifiedby the instruction, and to return control to the fetch phase in order to repeat the cycle for the next instruction. % The control unit initiates a series of sequential steps of microoperations. During any given time, certain microoperations are to be initiated, while others remain idle. The control variables at any given time can be represented by a string of 1's and 0's called a control word. As such, control words can be programmed to perform various operations on the components of the system + The microinstruction specifies one or more microoperations for the system. A sequence of microinstructions constitutes a microprogram. Microprogrammed Control Organization ~The general configuration of microprogrammed control unit is demonstrated in the block diagram of Fig. The control memory is assumed to bea ROM, wi all control information is permanently stored. jin which + The control memory address register specifies the address of the microinstruction, and the control data register holds the microinstruction read from memory. Address Sequencing “* Microinstructions are stored in control memory in groups, with each group specifying a routine. “+ Each computer instruction has its own microprogram routine in control memory to generate the microoperations that execute the instruction. + To appreciate the address sequencing in a microprogram control unit, let us enumerate the steps that the control must undergo during the execution of a single computer instruction. ‘+ An initial address is loaded into the control address register when power is turned on in the computer. This address is usually the address of the first microinstruction that activates the instruction fetch routine. At the end of the fetch routine, the instruction is in the instruction register of the computer. * The control memory next must go through the routine that determines the effective address of the operand. When the effective address computation routineis completed, the address of the operand is available in the memory address register. “ The next step is to generate the microoperations that execute the instruction fetched from memory. The microoperation steps to be generated in processor registers depend on the operation code part of the instruction. “ When the execution of the instruction is completed, contro! must return to the fetch routine. This is accomplished by executing an unconditional branch microinstruction to the first address of the fetch routine. In summary, the address sequencing capabilities required in a control memory are: Incrementing of the control address register. Unconditional branch or conditional branch, depending on status bit conditions. ‘A mapping process from the bits of the instruction to an address for control memory. A facility for subroutine call and retum. oe Conditional Branching “The branch logic provides decision-making capabilities in the control unit. ‘ The status conditions are special bits in the system that provide parameter Information such as the carry-out of an adder, the sign bit of a number, the mode bits of an instruction, and input or output status conditions. o Information in these bits can be tested and actions initiated based on their condition: whether their value is 1 or 0. ‘ The status bits, together with the field in the microinstruction that specifies a branch address, control the conditional branch decisions generated in the branch logic. The branch logic hardware may be implemented in a variety of ways. The simplest way is to test the specified condition and branch to the indicated address if the condition is met; otherwise, the address register is incremented. Mapping of Instruction “ Each instruction has its own microprogram routine stored in a given location of control memory. The transformation from the instruction code bits to an address in control memory where the routine is located is referred to as a mapping process. + A mapping procedure is a rule that transforms the instruction code into a control memory address. & For example, a computer with a simple instruction format as shown in Fig. 7-3 has an operation code of four bits. Assume further that the control memory has 128 words, requiring an address of seven bits. For each operation code there exists a microprogram routine in control memory that executes the instruction.+ One simple mapping process that converts the 4-bit operation code to a 7-bit address for control memory. % This mapping consists of placing a 0 in the most significant bit of the address, transferring the four operation code bits, and clearing the two least significant bits of the control address register. This provides for each computer instruction a microprogram routine with a capacity of four microinstructions. ‘Ifthe routine needs more than four microinstructions, it can use addresses 1000000 through 1111111. Ifit uses fewer than four microinstructions, the unused memory locations would be available for other routines. Subroutines ~ Subroutines are programs that are used by other routines to accomplish a particular task. ‘A subroutine can be called from any point within the main body of the microprogram. ‘ Frequently, many microprograms contain identical sections of code. Microinstructions can be saved by employing subroutines that use common sections of microcode. For example, the sequence of microoperations needed to generate the effective address of the operand for an instruction is common to all memory reference instructions. This sequence could be a subroutine that is called from within many other routines to execute the effective address computation. ‘ Microprograms that use subroutines must have a provision for storing the return address during a subroutine call and restoring the address during a subroutine return. This may be accomplished by placing the incremented output from the control address register into a subroutine register and branching to the beginning of the subroutine. The subroutine register can then become the source for transferring the address for the return to the main routine. Microprogram “ Microprogram is a sequence of microinstructions that controls the operation of an arithmetic and logic unit so that machine code instructions are executed % Itis a microinstruction program that controls the functions of a central processing or peripheral controller of a computer. Microinstruction Format The microinstruction format for the control memory is shown in Fig. The 20 bits of the microinstruction are divided into four functional parts. The three fields Fi, F2, and F3 specify microoperations for the computer. The CD field selects status bit conditions. The BR field specifies the type of branch to be used. The AD field contains a branch address. The address field is seven bits wide, since the control memory has 128 = 27 words.