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Serial Peripheral Interface: - Nidhi Panchal

Serial Peripheral Interface (SPI) is a synchronous serial communication interface specification used for short-distance communication, such as between devices on the same board. SPI uses separate signal lines for clocking, data input, and data output. A device transmitting data on SPI is the master and generates the clock signal, while receiving devices are slaves. Data is transmitted on SPI in a full-duplex manner with multiple clock modes and data transmission speeds of millions of bits per second.

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72 views29 pages

Serial Peripheral Interface: - Nidhi Panchal

Serial Peripheral Interface (SPI) is a synchronous serial communication interface specification used for short-distance communication, such as between devices on the same board. SPI uses separate signal lines for clocking, data input, and data output. A device transmitting data on SPI is the master and generates the clock signal, while receiving devices are slaves. Data is transmitted on SPI in a full-duplex manner with multiple clock modes and data transmission speeds of millions of bits per second.

Uploaded by

Jaimin Panchal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Serial Peripheral Interface

- Nidhi Panchal
Serial Peripheral Interface

 What is it?
 Basic SPI
 Capabilities
 Master-Slave Setup
 Signal Function
 Protocol Operation
 Registers
 Pros and Cons
 Uses
What is it?

Serial bus protocol


Fast, easy to use, and simple
Very widely used
Separate wires required for data & clock
The clock is not included in data stream, must b separate signal
SPI Basics

A 4-wire communications bus


Full Duplex
Typically communicate across short distances
Supports
- Single master
- Multiple slaves
Synchronized
Communications are “clocked”
Four basic SPI signals
- MISO (Master In Slave Out)
- MOSI (Master Out Slave In)
- SCK (Serial Clock)
- SS_BAR / CS (Slave Select / Chip Select)
SPI Capabilities

Always full-duplex
Communicates in both directions simultaneously
Transmitted (or received) data may not be meaningful
Multiple Mbps transmission speeds
0-50 MHz clock speeds not uncommon
Transfer data in 4 to 16 bit characters
Supports multiple slaves
Master-Slave Setup

SPI can be setup to operate


With single master and single slave.

• Single Slave
Multiple Slave Connection:
It can be set up with multiple slaves controlled by a single master. There are two ways to
connect multiple slaves to the master. If the master has multiple slave select pins, the
slaves can be wired in parallel like this:
If only one slave select pin is available, the slaves can be daisy-chained like this:
Each slave is cascaded so that the output
of one slave is the input of another.
When cascading, they are treated as
one slave and connecting
to the same chip select
SPI Signal Functions

 MOSI – carries data out of master to slave


 MISO – carries data out of slave to master
 Both MOSI and MISO are active during
every transmission
 SS (or CS) – unique line to select each slave
chip
 SCLK – produced by master to synchronize
transfers
Steps of SPI data transmission

1. The master outputs the clock signal:


2. The master switches the SS/CS pin to a low voltage state, which activates the slave:
3. The master sends the data one bit at a time to the slave along the MOSI line. The
slave reads the bits as they are received:
4. If a response is needed, the slave returns data one bit at a time to the master along the
MISO line. The master reads the bits as they are received:
SPI Clocking

Four clocking “modes”


Two phases
Two polarities
Master and selected slave must be in the same mode
During transfers with slaves A and B, Master must
Configure clock to Slave A’s clock mode
Select Slave A
Do transfer
Deselect Slave A
Four clocking modes:
These four modes, we can choose by using control bits CPOL and CPHA in Serial
Peripheral Control Register (SPCR).
Both master and slave must operate with the same timing.
The master device always place data on MOSI line a half cycle before clock edge, In
order for the slave device to latch/sample the data.
Timing Diagram :
Timing diagram for all modes (single clock pulse)
Slave Select (ss_bar) :

The Slave Select line is used to select the slave device.


It has to be low for data transaction and must stay low for the duration of data
transmission.

- Master-Slave Interconnection 
• SPI Registers

1. Serial Peripheral Control Register (SPCR)


2. Serial Peripheral Status Register (SPSR)
3. Serial Peripheral Data Register (SPDR)

 1) SPCR :
SPIE (Serial peripheral Interrupt Enable)
When this bit is set, the SPI system can generate an interrupt.
SPE (Serial Peripheral System Enable)
This bit enables SPI communication.
0 – System off
1 – System on
DORD (Data Ordered)
Bit determines which bytes in serial communication are to be sent first:
0 – MSB bit is sent first.
1 – LSB bit is sent first.
MSTR (Master Mode Select )
Bit determines whether the microcontroller is to operate as master or slave.
0 – Operate as slave.
1 – Operate as master.
CPOL (Clock Polarity)
Bit controls the SCK pin logic state when the SPI communication is not in progress:
0 – Pin SCK is cleared.
1 – Pin SCK is set.
CPHA (Clock Phase) This bit along with the CPOL bit controls relation between clock and
data in serial format.
SPR1,SPR0 (SPI Clock Rate Select)
When SPI system operates as master, these two bits determine baud rate.
 2) SPSR (SPI Status Register)

SPIF (Serial Peripheral Interrupt Flag)


Upon data transfer, this bit is automatically set and an interrupt is generated if SPIE=1
(Serial Peripheral Interrupt Enable).
- By reading or write 1 ,we can clear this bit.
WCOL (Write Collision)
- This bit is set in normal mode 0.
- If the SPDR register is written during data transfer is in progress. The write is premature
and has no effect. It is called Write Collision. This bit is cleared in the same manner as the
SPIF bit.
- The bit is set 1 when buffer is full. It is indication that a new data is ready to be
transmitted to the shift register.
- A new data can be written to buffer when the WCOL bit is set. In addition, the WCOL bit
must be cleared.
MODF (Mode Fault)
- To indicate there are multi master conflict, so it will allow a proper exit from operation to
a reset or default system state.
- By reading we can clear bit or write 1 .(write clear)

 3) SPDR (SPI Data Register)


- The SPDR register is used for storing data to be transferred via SPI (in serial format). It is
also used for storing received data.
Pros
Fast for point-to-point connections
Easily allows streaming/constant data inflow
No addressing in protocol, so it’s simple to implement

Cons
Slave select/chip select makes multiple slaves more complex
No acknowledgement (can’t tell if clocking in garbage)
No inherent arbitration
No flow control (must know slave speed)
Uses

LCDs
Sensors
Radios
Lots of other chips
Microcontrollers
Almost all MCUs have SPI masters
Some have SPI slaves
Thank you

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