THEFUTURE

OF
MICROPROCESSORS
Albert Yu Tn my role as head of Intel’s micro- The bad news is that producing advanced

Intel Corporation 1 pro&or products, I am often asked to

paint a picture of the microprocessor of
the future. Even if our newest processor has
microprocessors involves much higher cap-
ital cost than anyone ever expected. At Intel,
we’ve augmented Moore’s law (the number
just hit the streets and has not even come of transistors on a processor doubles approx-
close to full use, people naturally crave imately every 18 months) with Moore’s law
information about where they’re going 2. Law 2 says that as the sophistication of
rather than where they’ve been. chips increases, the cost of fabrication rises
My colleagues and I have been trying for exponentially (see Figures 1 and 2). In 1986,
about 10 years now to identify trends about we manufactured our 386 containing 250,000
the microprocessor of the future. While transistors in fabs costing $200 million.
these are based on a wide variety of Today, the Pentium Pro processor contains
unknown factors inherent in developing 6 million transistors but requires a $2 billion
new technology, for the most part, we have facility to produce.
been close to the mark. However, before Looking ahead, the important technolog-
making statements about microprocessor ical fact that emerges is that Moore’s law
trends 10 years out-Micro 2006-it might continues to reign, with the number of tran-
be useful to revisit our past statements’J sistors per chip increasing exponentially.
about the microprocessor of today and tge Today’s performance trend can continue,
microprocessor of 2000. Then we can see thanks to microarchitecture and design inno-
where we have been right and where vations beyond raw transistor count. The
wrong. This retrospective will reveal impor- personal computer market, by far the biggest
tant trends that promise to give some insight market for microprocessors, continues to
into the microprocessor of the next decade. grow at a healthy rate. It can provide the vol-
ume markets needed to absorb the huge
Performance, capital costs manufacturing capital costs. To be sure, we
Over the last 10 years, evolving micro- have a number of key technology barriers
processor performance increased at a high- to overcome as device geometry migrates
er than envisioned rate; unfortunately, so did well below the submicron range. However,
manufacturing capital costs. Table 1 lists our all indications are that the microprocessor
1989 predictions for today’s microprocessor of 2006-and beyond-will be well worth
performance at speeds of 100 MIPS (millions the wait.
of instructions per second), which is equiv-
alent to an ISPEC95 rating of 2.5 and clock Micro 2000 revisited
rates of 150 MHz. Surprisingly, today’s per- As Table 1 shows, we anticipated in 1989
formance dramatically exceeds this. The Intel that in 2000 a processor would carry 50 mil-
Pentium Pro processor runs at 400 MIPS, with lion transistors in a 1.Zin. (square) die. The
Intel’s head of an ISPEC95 rating of about 10 and a ZOO-MHz industry is mostly on track to deliver a 40-
clock rate. This great performance boost has million-transistor chip on a l.l-in. die in
microprocessor stimulated a huge range of applications for 2000. This 20 percent offset is not a tech-
business, home, and entertainment, from nology limitation but an economic one,
products looks 10 mobile computers to servers. As a result, the necessitated by creating a reasonable die
PC market segment is a lot larger today than cost (see Figure 1).
years ahead to 2006. we anticipated years ago. Silicon technology. Our visions about

46 IEEE Micro 0272.1732/96/$5.000 1996lEEE

silicon process line width Table 1. Visualizing trends for the microprocessor of the future.
were right on the money, ‘as
Intel is currently in produc- 1989 1989 1996 1996
tion with 0.35micron tech- predictions 1996 predictions predictions predictions
nology for the Pentium and Characteristic for 1996 actuals for 2000 for 2000 for 2006
Pentium Pro. I believe that
line width will continue to Transistors (millions) 8 6 50 40 350
drop to 0.2 micron in 2000 Die size* (inches) 0.800 0.700 1.2 1.1 1.4
and to 0.1 micron in 2006 Line width (microns) 0.35 0.35 0.2 0.2 0.1
(see Figure 3). Also, the Performance:
dielectric thickness and the MIPS 100 400 700 2,400 20,000
voltage supply will have ISPEC95 2.5 10 17.5 60 500
decreased correspondingly. Clock speed (MHz) 150 200 250 900 4,000
This incredible shrinkage will
continue unabated for the *Length of single side of square die.
forseeable future. The num-
ber of metal interconnects
has increased from two to five over
the last 10 years and will increase
^ .
turther as we need more intercon-
nects to hook up all the devices.3 In
fact, this is one of the biggest per-
formance-limiting factors we con-
tend with (see later discussion).
In addition, the problem of inter-
connects from the chip to the pack-
age and eventually to the system
board is another major limiting factor 1971 1976 1981 1986 1991 1996 2001 2006
for performance. Actually, we want Year
to build single chips to avoid per-
formance loss when sending signals Figure 1. Chart showing Moore’s law.
off chip. We added cache and float-
ing-point units on the 486 processor
mostly for that reason, For the Pentium Pro processor, we of microprocessors exceeds our 1989 vision by quite a lot.
placed the second-level cache and the processor in the same There are several reasons for this. Although the silicon
package to achieve the bandwidth needed between the two. process advances were pretty much on target, we have
The future trend will be to incorporate more performance achieved higher frequency out of these advances with novel
and bandwidth-sensitive elements on chip and to continu- microarchitecture and circuit techniques. In addition, the
ously improve the package interconnect performance. number of instructions per clock has increased faster, and
Several companies are investigating MCM (multichip module) we have exploited superscalar architectures and greater
technology to eliminate chip packaging altogether, and I degrees of parallelism. There have also been significant inno-
believe this will be an important trend for future high-per- vations in compiler technology that boost performance even
formance processors. higher. I see these trends continuing.*a5
Performance. It is amazing that the actual performance

0.011 : /
1966 1974 1982 1990 i 998 2006 1971 1976 1981 1986 1991 1996 2001 2006
Year Year

Figure 2. Chart showing Moore’s law 2. Figure 3. Chart showing line width versus time.

December 1996 47
 We will see clock speeds of about 700 MHz with a 60 nology provided software compatibility, compact code size,
ISPEC95 rating in 2000. Such tremendous clock rates place and future RISC-matching performance.
great demands on the resistance and capacitance of the chip’s Today, the architecture debate has pretty much become a
metal interconnects for power and clock distribution. These nonissue. Both the debate and the competition have been
multimillion-transistor devices also face new hurdles in pack- good for the industry, as both sides learned a great deal from
aging and power management. the other, which stimulated faster innovation. There is really
,&rchitecture. In the late 1980s there was much debate no perceptible difference between the two in either perfor-
about which microprocessor architecture held the key to mance or cost. Pure RISC chips like the IBM ROMP, Intel
fastest performance. RISC (reduced instruction set comput- 80860, and early Sun Spare, as well as pure CISC chips like
ing) advocates boasted faster speeds, cheaper manufactur- the DEC VAX, Intel 80286, and Motorola 6800, are gone. Smart
ing costs, and easiest implementation. CISC (complex chip architects and designers have incorporated the best ideas
instruction set computing) defenders argued that their tech- from both camps into today’s designs, obliterating the differ-

48 IEEE Micro
ences between architecture-specific implementations. What in the entry of various circuit-logic data, verify the global
counts most in designing the highest performance, lowest chip timing, and extract the actual layout statistics and veri-
cost chip today is the quality of implementation. fy them,against the original simulation assumptions. One of
Seven years ago in IEEE Spectrum, r our vision was that the the rapidly developing areas is synthesis, first in logic syn-
microprocessor of 2000 would have multiple general-purpose thesis but progressing to data path synthesis. These capa-
CPUs working in parallel. What has instead happened is not bilities have improved design productivity enormously.
separate CPUs on the same chip but a greater degree of par- Future advances will improve the layout density (to reduce
allelism within a single chip. The Pentium processor employs product cost) and raise performance (to enable new applica-
a superscalar architecture with two integer pipes, and the tions). This is particularly challenging as interconnects are
Pentium Pro processor design expanded that to three. Other becoming greater performance limiters than are transistors. In
processors such as the HP PA and IBM PowerPC have used addition to electrical simulation, thermal and package simula-
similar superscalar architectures. I see the trend to exploit tion will be the norm by 2000. Beyond the chips, the trend is
more parallelism continuing well into the future. to expand simulation to encompass the whole system, includ-
Human interface. The number of transistors devoted to ing processor, chip sets, graphics controller, VO, and memory.
the human interface is increasing too. Human interface func- Though the dependency on and rapid innovations in CAD
tions are those that contribute to making a PC or other device have been pretty much on target, the design complexity and
more attractive and easier to use-three-dimensional graph- design team size have grown greater than expected. Two
ics, full-motion video, voice generation and recognition, and engineers developed the first microprocessor in nine months.
image recognition. Even though we have no way of know- Modern microprocessor design requires hundreds of people
ing precisely how future microprocessors will be used, I firm- working together as a team.
ly believe that graphics, sound, and 3D images will play a Though design productivity has improved enormously, it
huge role. We live in a 3D color world, and we naturally is just barely keeping up with the increased complexity and
want our computers to mirror that. Once the computing performance. Looking forward, I see that one of our most
power is available to create these kinds of features, applica- challenging areas is how to achieve quantum leaps in design
tion developers will have a huge opportunity to push com- productivity. An obvious help would be for CAD tools to be
puting into new realms. Therefore, we’ll see a higher truly standards-based and fully interoperable. This is not the
percentage of the microprocessor chip allocated to these case today, causing the industry to waste valuable resources
purposes. struggling with conflicting and proprietary interfaces.
In 1989, we set aside 4 to 8 million transistors-roughly 10 Testing. Testing complex microprocessors has become a
percent of our estimate for 2000-for human interface and huge issue. Though the capital associated with testing micro-
graphics functions. Our new MMX technology for the Pentium processors is still smaller than that associated with wafer test-
processor and Sun UltraSparc’s VIS (visual instruction set) are ing, it has been escalating beyond our anticipations. Why?
examples of general-purpose instructions for accelerating First, the tester is more expensive due to increased frequen-
graphics, multimedia, and communication applications. cies and the large number of pins (the Pentium Pro proces-
Bandwidth. What becomes very apparent in moving into sor runs at 200 MHz and has 387 pins). Second, testers that
the future with complex chips is that microprocessor design previously cost $50,000 cost well over $5 million today.
is becoming system design. The microprocessor designer Lastly, because of chip complexity and quality requirements
must consider everything that touches the chip, which of less than 500 DPM (defects per million), test time contin-
includes the system bus and I/O, among others. As raw ues to increase. As a result, the total factory space and cap-
processor speed increases, system bandwidth becomes more ital costs devoted to test have skyrocketed.
critical in preventing bottlenecks. We will need very high In I989 we envisioned that a larger share of transistors in
bandwidth between the CPU and memory and between 2000 would be devoted to self-test-approximately 3 mil-
other system components to deliver the kinds of real speed lion transistors (6%) out of the total 50 million. A great deal
gains of which the silicon is capable. Toward that end, micro- of innovation has happened in this area. Today, roughly 5
processor buses continue to increase in throughput. PC1 is percent of the Pentium Pro processor’s total transistor count
one of the major standards that allows PCs to increase the I/O supports built-in self-test. Therefore, our prediction for 2000
bandwidth significantly. stands: About 6 percent or so will be devoted to testing; this
Today, Intel is working with the PC community to spear- number may increase in 2006.
head the development of the accelerated graphics port Compatibility. We posited in 1989 that binary compati-
(AGP). This vehicle increases bandwidth between the graph- bility was absolutely critical for investment protection and
ics accelerator and the rest of the system. The AGP will be continuity. There are vast software bases in use today that
critical for the full fruition of applications involving 3D and each year become more valuable assets to businesses.
other high-resolution graphics. As communications become Companies do not want to abandon these, even in favor of
even more important for PCs and Internet applications faster computers. Thus, even with fairly radical architectur-
expand, we will need more communications bandwidth. al departures such as massively parallel processing, we must
Design. We saw that our dependence on advanced maintain compatibility between future microprocessors and
computer-aided design tools would soar, and it has. Today, today’s microprocessors. Only a twofold or greater improve-
we’re simulating an entire chip, rather than just portions of ment in system performance makes a switch to incompati-
it, from behavior to the register-transfer level. CAD tools assist ble hardware worthwhile. This is more true today than ever

December 1996 49
 innovation in oerformance than ever before. The two trends
driving increased performance will continue to be more par-
allelism and higher frequencies. To exploit more parallelism,
we will increasingly focus on compiler and library opti-
mization To push to higher frequencies, we will need
advances in microarchitecture, circuit design, accurate sim-
ulation, and interconnects.
I see a great many good ideas that can be implemented for
years to come. The performance drive is clearly not bound
to the microprocessor but derives from the whole system, as
Year one must build balanced systems to deliver power to users.
~ Trend------+
Interestingly, earlier microprocessors borrowed lots of good
architectural ideas from mainframes. From here on out, we
Figure 4. PC shipment trend. (Source: Dataquest, Apr. are going way beyond the performance any mainframe has
1996) ever provided. Therefore, it is also important that the indus-
try devotes more resources to long-term research and forges
stronger cooperation with universities.
and will continue to be one of the most important business Barriers. Before we can realize a microprocessor of this
and user requirements for future microprocessors. Of course, complexity, we’ll need to meet and resolve several techno-
software is becoming more portable, but no one will devote logical and logistical barriers. One of the most basic is grap-
the resources to recompile and maintain another binary ver- pling with design complexity and the burgeoning size of the
sion without major added benefits! design team. Larger design teams are harder to coordinate
At the same time, the task to ensure compatibility has and ensure communication within. Designing for correct-
grown enormously. The number of different operating sys- ness from the beginning remains a necessity, but becomes
tems, applications, and system configurations has skyrock- far more difficult as designs become exponentially more
eted beyond earlier estimations. Of course, this job of complex.
compatibility validation is much harder after the silicon stage Compatibility validation becomes unbelievably difficult in
than before it, but accomplishing the technical problems with designs as complex as the one we are contemplating for
sufficient speed on software models or hardware emulators 2006. The task of exhaustively testing all possible computa-
is an enormous task. tional and compatibility combinations is huge. We need a
Market segment size. When we had the Pentium proces- breakthrough in our validation technology before we can
sor on the drawing board, we were anticipating sales of only enter the 350-million-transistor realm.
about three million units in 1995. According to IDC reports, Another area crying out for breakthrough thinking is
Pentium processor shipments in 1995 were close to 60 mil- power. Faster microprocessors obviously need more power,
lion. This twentyfold jump has been great for the whole but we also need a way to dissipate the power from the chip
industry. For example, Figure 4 shows Dataquest’s estimation through the package and the system. To lower on-chip
of PC shipments through 2000 predicting steady growth of power, we need breakthroughs to drive voltage requirements
15 to 19 percent. Lucky for all of us, this market segment way below 1 V. We need innovations in low-power micro-
growth will allow more R&D dollars and capital investments architectures, design, and software to contain the power rise.
to drive the microprocessor evolution at the exponential pace For mobile applications, the whole electronics complex
of Moore’s law. needs to stay below 20 W. Power poses big challenges not
only to microprocessors but to other components in the sys-
What about 20061 tem such as graphics controllers and disk drives,
Once we understand where we are versus our earlier As mentioned earlier, ‘interconnects are the major perfor-
vision, it is easier for us to look 10 years ahead to 2006. mance limiter and will remain so until scientists discover
Transistor and die size. Table 1 and Moore’s law show lower resistance, lower capacitance materials. Today’s
that the number of transistors could jump to about 350 mil- Pentium Pro processor has five metal layers; future genera-
lion in 10 years. Remember that plenty of previous-genera- tions will need more. Metallization technologies historically
tion processors will continue to ship in huge volumes. take years to develop, so we urgently need research in this
Die size will push toward 1.4 inches to accommodate the area to create the microprocessor of 2006.
tremendous number of transistors and interconnects. Line Market segment. We have historically erred on the side
width will have shrunk to a mere 0.1 micron, stretching of underestimating microprocessor demand. Although I can-
today’s optical systems to the physical limits. We may well not estimate the exact volumes, I do foresee strong contin-
have to look for other alternatives. Silicon technology will ued growth for the PC and microprocessor market segments
continue to advance at a rapid rate, as predicted by Moore’s into the next decade. Although the PC market segment in
law, and voltage will continue to shrink to well below 1 V. the United States is maturing, it is just beginning in emerg-
Performance and architecture. By 2006, performance ing markets, notably Southeast Asia, South America, and
will have jumped to an incredible 4 GHz or a 500 ISPEC95 Eastern Europe.
rating.6 All indications are that more opportunities exist for In addition to openings of new geographical markets, new

50 IEEE Micro
functional markets will continue to unfold. Although it is the structure with ever-increasing power and capability; innov-
futurist’s job to imagine how computing power will be used ative ideas for using them will follow.
in the next century, history shows that incredible innova- As mentioned earlier, one area that I believe will require
tions will occur only when sufficient computing capability is huge numbers of MIPS (not to mention bandwidth) is human
present. For example, no one predicted the first spreadsheet, interface enrichment: SD, rich multimedia, sight, sound, and
and until the first PC appeared on the scene, there was no motion. Tomorrow’s applications will increasingly incorporate
framework in which such an innovation could come about. video, sound, animation, color, 3D images, and other visual-
Our job is to create the microprocessor and PC platform infra- ization techniques to make PCs and applications easier to use.

December 1996 51
 The consumer market segment, rather than the business opportunities for enterprising application designers to incor-
market segment, is driving PC development in this area. porate 3D visualization in clarifying complex business infor-
Although the business market struggles with how to interpret mation. More powerful processors with powerful graphics
and present enormous amounts of information more clearly, make it easy to display information visually rather than numer-
home users are leading business people in discovering cre- ically and therefore easier to interpret the information. PCs
ative ways to solve problems graphically. There are huge with smart user interfaces will enable their users to become

52 IEEE Micro
 active seekers of information rather than passive absorbers. Semiconductor Industry Assoc., San Jose, Calif., 1995
Some argue that, in the face of the runaway success of the 4. R.P.Colwell and R.L. S&k, “A 0.6 pm BiCMOS ProcessorWith
Internet, less rather than more processing power is needed Dynamic Execution, N froc. Int’l Solid-State Circuits Conf., IEEE,
on the desktop. So-called network computers on the draw- Piscataway, NJ., 1995, p. 136.
ing board today allow users to download necessary “applets” 5. U. Weiser, “Intel MMX Technology-An Overview,” Proc. Hot
and data for temporary use. These devices may find a niche, ChipsSymp., Aug. 1996, p. 142.
but the amount of processing power on the desktop (or in 6. “Special Issue: Celebrating the 25th Anniversary of the
the living room) will depend on the kind of Internet expe- Microprocessor, fl Microprocessor Report, Aug. 5, 1996.
rience users wish to have. If they simply want to browse
through traditional data types, a less powerful processor may
suffice. However, if they want a rich multimedia experience, Albert Y.C. Yu is senior vice president
viewing information with 3D images and sound will require and general manager of the Micro-
considerable MIPS. processor Products Group at Intel Cor-
Another area that urgently needs attention is the historic poration. He has responsibility over Intel
lag between hardware and software development. Software Architecture Processor products such as
has always lagged behind available hardware; just as an the Pentium, Pentium Pro, and future
application takes advantage of new hardware capabilities, microprocessors. He also oversees plat-
vendors release the next generation of hardware. Widespread form architecture, design technology, microprocessor soft-
object-oriented design may help close this gap, but we need ware products, and microcomputer research labs.
breakthroughs in software development to help software Yu received his PhD and MS from Stanford University and
keep pace with hardware developments. I believe this is an his BS from the California Institute of Technology, all in elec-
area of enormous opportunity. Whoever is first to fully take trical engineering. He is a senior member of the IEEE and
advantage of the coming microprocessor power to offer the Computer Society.
innovative applications will be the unquestioned leader.
Address questions or comments about this article to Albert
Y.C. Yu, Intel Corporation, M/S RN 3-31, 2200 Mission
THEMICROPROCESSORDEVELOPMENT
pathwe’ve College Blvd., San Jose, CA 95052-8119; Albert-Yu@
been on for the past 25 years can easily continue into the ccm.sc.intel.com.
next 10. Performance can continue to advance until we reach
close to a stunning 400 million transistors on a 1.7-inch chip
in the year 2006. However, manufacturing capital costs will Reader Interest Survey
be in the multibillion-dollar range, necessitating huge vol- Indicate your interest in this article by circling the appropriate
umes to drive down unit price. Besides the huge cost of man- number on the Reader Service Card.
ufacturing, we have big technological hurdles to overcome
before we realize such a chip. We need to know how to test Low 162 Medium 163 High 164
and validate 400 million transistors, how to connect them,
power them, and cool them.
Once in hand, however, computing power of such magni-
tude will set the stage for huge innovations and market seg- COMING IN FEBRUARY
ment opportunities in everything from business computing to The next issue of IEEE Micro features selected articles from
“edu-tainment” products for kids. One thing I can predict with presentations at the 1996 Hot Interconnects Symposium. Guest
certainty: Micro 2006 will surprise us all with applications and Editors Quang Li (Santa Clara University), Chuck Thacker
(Digital), and Kai Li (Princeton) picked the following to be
devices that will dramatically change our world. Ip
rewritten and reviewed for publication in Micro:

. Scalable Pipelined Interconnect for Distributed

Acknowledgments Endpoint RoutineThe SGI SPIDER Chip
I thank fellow Intel employees Richard Wirt and Wen-Hann l The Tiny Tera: A Packet Switch Core
l Client-Server Computing on the SHRIMP
Wang for assistance in gathering and formulating prediction
Multicomputer
data.
. Transmitter Equalization for 4Gb/s Signaling
l A mm-wave, High-Speed Wireless LAN for Mobile
Computin~Architecture and Prototype
References Modem/Codec Implementations
1. P.P. Gelsinger et al., “Microprocessors Circa 2000,” FEE . Experience Using the First-Generation Memory
Spectrum, Oct. 1989, pp. 43-47. Channel for the PC1 Network
2. P.P.Gelsinger et al., “2001: A Microprocessor Odyssey,” Tech-

3.
nology 2001, The Future of Computing

The National Technology Roadmap

and Communications,
D. Leebaert, ed., The MIT Press,Cambridge, Mass., 1991, pp.
95-113.
for Semiconductors,
““MICIQ
December 1996 53