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Experiment1 - VHDL Code For ALU-2024-25

VLSI VHDL ALU code

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12 views4 pages

Experiment1 - VHDL Code For ALU-2024-25

VLSI VHDL ALU code

Uploaded by

djbravo11.com
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ET,

VLSI Design & Technology(404181)


B.E. (E&TC) Sem. - I Academic Year-2024-2025
CO
PVG's College of Engineering and Technology & G K Pate (Wani) Institute of
Management, Pune-411009

Accredited by NAAC with Grade “A”


Department of Electronics and Telecommunication
Engineering
___________________________________________________________________________

Experiment 1: VHDL code for 4 bit ALU


Name: Class: B.E. Division: I / II
Roll No: Date of Submission:
Marks Obtained: / 10 Signature of the subject teacher:
___________________________________________________________________________

Aim: To write VHDL code, simulate with test bench, synthesis, implement on PLD for 4
bit ALU for add, subtract, AND, NAND, OR, XOR & XNOR.

Objectives
To understand the programming concepts of Hardware Description Language VHDL for
modeling a digital circuit. To understand the EDA tool design flow to design, model and
realize a digital system on an FPGA.

Mapped Outcome:
Model, simulate and synthesize a digital system using front-end EDA tool and implement the
system on FPGA.

Equipment / Software tools required:


Software : Xilinx VIVADO 18.2 System Edition
Hardware: Artix 7 Basys 3 Prototype FPGA Board

Say No to Plagiarism and Yes to Acknowledgements Green Revolution No Pollution


1/8
ET,
VLSI Design & Technology(404181)
B.E. (E&TC) Sem. - I Academic Year-2024-2025

Theory:
CO
1. Draw Entity block diagram for given 4 bit ALU

2. Explain the significance of I/O Ports of ALU.

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Procedure:
1. Open Vivado 18.2 tool.
2. Create a new VHDL project.
3. Select target FPGA device/board for implementation of VHDL code.

Say No to Plagiarism and Yes to Acknowledgements Green Revolution No Pollution


2/8
ET,
VLSI Design & Technology(404181)
B.E. (E&TC) Sem. - I Academic Year-2024-2025

4. Write VHDL code in editor window of Vivado tool and compile.


CO
5. Simulate the code using test bench.
6. Synthesize the design and assign the package pins to I/O ports of the design.
7. Run implementation and generate bit stream for downloading.
8. Connect the hardware and program the target device by downloading the generated
bit stream.
9. Observe the results on the target board.

Results: Attach the following documents

1. VHDL Code Print


2. VHDL Test Bench code Print
3. Simulation Waveforms Print
4. Synthesis Report Print(Selected Pages)
5. UCF file Print
Assignment (10 marks)
Q1) Write the VHDL code and synthesize the 4 bit ALU using "if__ else statement" and
"with__ select statement". Attach the print of the both codes and the synthesis report. Write
the difference in terms of schematic and synthesis generated from the two statements.
Q2) Write the VHDL code and simulate a 4 bit adder using structural modeling style using
full adder as a component. Attach the print of the code and simulation waveform.
Conclusion:
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………

Remarks by Subject teacher about correctness and improvements:

…………………………………………………………………………………………………
…………………………………………………………………………………………………
…………………………………………………………………………………………………
Reference:

[1] Digital systems design using VHDL, Charles H. Roth, PWS Publication
[2] User Manual for Basys 3 Boards

Say No to Plagiarism and Yes to Acknowledgements Green Revolution No Pollution


3/8
ET,
VLSI Design & Technology(404181)
B.E. (E&TC) Sem. - I Academic Year-2024-2025

Important Notes:
CO
Note1. Following points should be considered while writing the conclusion
1. Modeling style of the program
2. Other modeling style that can be used for the same design.
Note2. Print all the documents back to back on every page. Save pages to save trees.
Note3 .Printing on single side will reduce the marks
Note4. Plagiarism of any form is strictly prohibited and attract towards reduction in marks
Note5. Submit the assignments well in time i.e. within four days of performing the
experiment to get maximum marks.

Say No to Plagiarism and Yes to Acknowledgements Green Revolution No Pollution


4/8

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