8086 SIGNALS & BASIC CONFIGURATION

Ans: PIN Diagram of 8086

OR
Clock Signals
Interrupt Signals
Power supply signal
Address and Data lines
Timing and control signals
SYSTEM BUS TIMINGS
The bus cycle is also named as machine cycle.

Bus cycle of 8086 is used to access memory, peripheral devices (Input/Output devices), and Interrupt controller.
Bus cycle corresponds to a sequence of events that starts with an address being output on system address bus
followed by a write or read data transfer. During these operations, a series of control signals are also produced
by microprocessor to control direction and timing of bus. There are at least four clock periods in a bus cycle of
8086 microprocessor. The 8086 has a combined address and data bus commonly referred as a time multiplexed
address and data bus. The main reason behind multiplexing address and data over the same pins is the
maximum utilization of processor pins and it facilitates the use of 40 pin standard DIP package. The bus can be
demultiplexed using a few latches and transreceivers, whenever required. Basically, all the processor bus cycles
consist of at least four clock cycles. These are referred to as T1, T2, T3, T4. The address is transmitted by the
processor during T1, It is present on the bus only for one cycle. The ALE pulse is used to separate the address
and the data or status information as shown in Figure 2.2.1.
In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of operation. Status bits S3 to S7
are multiplexed with higher order address bits and the BHE signal. Address is valid during T1 while status bits
S3 to S7 are valid during T2 through T4.These four clock periods are called T1, T2, T3 and T4 states.
These four clock states gives bus cycle duration T of 200 ns *4 = 800 ns in 5-MHz 8086 system.
1. Read Cycle: When a read cycle is to be performed, during T1 microprocessor puts an address on address
bus, and then bus is put in high impedance state during T2 state. Data to be read must be out on bus during
T3 and T4. During T3 bus is made “reserved for data in” and finally data is read during T4.

8086 Read Bus Cycle 8086 Write Bus Cycle

2. Write Cycle: A write cycle also begins with the assertion of ALE and the emission of the address. The
M/IO* signal is again asserted to indicate a memory or I/O operation. In T2 after sending the address in Tl the
processor sends the data to be written to the addressed location. The data remains on the bus until middle of T4
state. The WR* becomes active at the beginning ofT2 (unlike RD* is somewhat delayed in T2 to provide time
for floating). The BHE* and A0 signals are used to select the proper byte or bytes of memory or I/O word to be
read or written. The M/IO*, RD* and WR* signals indicate the types of data transfer.

1. S0,S1,S2 are set at the beginning of bus cycle. On detecting the change on
passive state S0 = S1 = S2 = 1, the 8288 bus controller will output a pulse on its ALE and apply a
required signal to its DT/R pin during T1.

2. In T2, 8288 will set DEN = 1 thus enabling transceiver. For an input, 8288 it will activates MRDC or
IORC. These signals are activated until T4. For an output, the AMWC or AIOWC is activated from
T2 to T4 and MWTC or IOWC is activated from T3 to T4.
 3. The status bits S0 to S2 remain active until T3, and become passive during T3 and T4.

4. If ready input is not activated before T3, wait state will be inserted between T3 and T4.

SYSTEM DESIGN USING 8086 ( Multi Processor)

MAXIMUM MODE 8086 SYSTEM AND TIMINGS
In the maximum mode, the 8086 is operated by strapping the MN/MX* pin to ground. In this mode, the
processor derives the status signals S2*, S1* and S0*. Another chip called bus controller derives the control
signals using this status information. In the maximum mode, there may be more than one microprocessor in
the system configuration.

The 8288 bus controller is able to originate the address latch enable signal to the 8282’s, the enable and
direction signals to the 8286 transceivers, and the interrupt acknowledge signal to the interrupt controller. It
also decodes the S2-S0 signals to generate MRDC, MWTC, IORC, IOWC, MCE/PDEN, AEN, IOB, CEN,
AIOWC, and AMWC signals.
MRDC (Memory Read Command): It instructs the memory to put the contents of the addressed location on
the data bus.
MWTC (Memory Write Command) : It instructs the memory to accept the data on the data bus and load the
data into the addressed memory location.
IORC (I/O Read Command) : It instructs an I/O device to put the data contained in the addressed port on the
data bus.
 IOWC (I/0 Write Command) : It instructs an I/O device to accept the data on the data bus
and load the data into the addressed port.
MCE/PDEN (Master Cascade Enable/Peripheral Data Enable) : It controls the mode of operation of 8259.
It selects cascade operation for 8259 (interrupt controller) if IOB signal is grounded and enables the I/O bus
transceivers if IOB is tied high.
AEN, IOB and CEN: These pins are used in multiprocessor system. With a single processor in the system,
AEN and IOB are grounded and CEN is tied high. AEN causes the 8288 to enable the memory control signals.
IOB (I/O bus mode) signal selects either the I/O bus mode or system bus mode operation. CEN (control
enable) input enables the command output pins on the 8288.
AIOWC/AMWC (Advance I/O Write Command/Advance Memory Write Command): These signals are
similar to IOWC and MWTC except that they are activated one clock pulse earlier. This gives slow interfaces
an extra clock cycle to prepare to input the data.

IO Programming
The data is transferred from input / output devices to the microprocessor. there are three different
ways in which data can be transferred:
1. Program Controlled IO
2. Interrupt Program controlled IO
3. Hardware controlled IO
1. Program Controlled IO: Data transfer is completely under the control of microprocessor program. Data
transfer takes place only when IN and OUT instruction is executed. Both the instructions perform data transfer
using accumulator (AX).
Port no.or address is specified along with IN and OUT instruction.
8-bit fixed port number appears on address bus A0-A7. remaing lines A8-A15 kept as zero. A16-A19 are
undefined.
16-bit port numbers.
IO read and write are used as control signals.
2. Interrupt program controlled I/O: in this , an external device indicates the microprocessor its readiness to
transfer data by sending a signal to an interrupt input.
3. Hardware controlled I/O: Data transfer takes place directly between I/O device and memory but not
through microprocessor. Also known as DMA ( Direct Memory Access). MP only provides the starting address
and no. of bytes to be transferred.

Multi-Programming
8086 and 8088 can be configured in two modes of operation, the minimum mode and the maximum mode. The
minimum model is used for a small system with a single processor, a system in which the 8086/8088 generates
all the necessary bus control signals directly (thereby minimizing the required bus control logic). The maximum
mode is for medium-size to large systems, which often include two or more processors
MULTIPROCESSOR SYSTEMS
Multiprocessor Systems refer to the use of multiple processors that execute instructions simultaneously and
communicate using mailboxes and semaphores Maximum mode of 8086 is designed to implement 3 basic
multiprocessor configurations:
1. Coprocessor (8087): 8087 numeric data processor is also known as Math co-processor, Numeric processor
extension and Floating point unit. It was the first math coprocessor designed by Intel to pair with 8086/8088
resulting in easier and faster calculation. Once the instructions are identified by the 8086/8088 processor, then it
is allotted to the 8087 co-processor for further execution.
The data types supported by 8087 are −
• Binary Integers
• Packed decimal numbers
• Real numbers
• Temporary real format
The most prominent features of 8087 numeric data processor are as follows −
• It supports data of type integer, float, and real types ranging from 2-10 bytes.
• The processing speed is so high that it can calculate multiplication of two 64-bits real numbers in ~27 µs
and can also calculate square-root in ~35 µs.
• It follows IEEE floating point standards.
2. Closely coupled (dedicated I/O processor:8089):It is a multiprocessor system with common shared
memory
CPU CPU CPU

Shared Memory

3. Loosely coupled (Multibus): It is a multiprocessor system in which each processor has its own local
memory.
CPU CPU CPU

Memory Memory Memory

Connection Network
Coprocessors and closely coupled configurations are similar - both the CPU and the external processor share:
 Memory
 I/O system
 Bus & bus control logic Clock generator
Difference between Closely coupled and Loosely coupled configuration

Sr. No. Closely coupled Loosely coupled

1. The information can be shared among The information is transferred from one
the CPUs by placing it in the shared processor to other by using message passing
memory. system.
2. It is used in parallel processing It is used in distributed computing systems.
systems
3. Example: Example:
Two CPUs on the same PC is Two CPUs connected by a modem over the
connected by wires placed onto the telephone system.
board.
4. Data rate is high Data rate is low.
5. There is a short delay experienced Machine delay is large
when message is sent from one CPU
to another CPU
6. Smaller in size Larger in size
7. Less flexible structure More flexible structure
8. More Expensive Less expensive
9. Parallelism can be implemented less Parallelism can be implemented more
efficiently efficiently

8086 BUS Structure

System Bus Bus is a group of communication lines to carry information bits. Different components of a
microprocessor system are organised around bus. The 8085 microprocessor has three buses: address
bus, data bus and control bus.
Types of Buses: Address Bus Data Bus Control Bus
Address Bus A collection of wires used to identify location in main memory is called Address Bus. It is a
group of 16 lines generally marked as A0 to A19. It is unidirectional which flow from microprocessor to
Input Output devices. The address bus carries address bits. It is used to identify IO peripheral or a
memory location.
Data Bus A collection of wires through which data is transmitted from one part of a computer to another is
called Data Bus. It is a group of 16 lines used for data flow generally mark as D0 to D15. These lines are
bidirectional. This bus connects all the computer components to the CPU and main memory. Data flow in
both directions between microprocessor and memory. The data bus is used to transfer binary information.
Control Bus The connections that carry control information between the CPU and other devices within
the computer is called Control Bus. This bus provides timing signals. It is compromised of various single
lines that carry synchronization signals. There are three control pins: Input Output/Memory (IO/M'), Read
(RD') and Write (WR'). Using these three pins, four different control signals can be generated: Memory
Read, Memory Write, Input Read, Output Write.