MODE,

MINIMUM
CONFIGURATIONS-

2.BASIC MODE (OR)

MAXIMUM
CONFIGURATIONS-SYSTEM BUS

MINIMUM
MODE
TIMING
SYSTEM BUS STRUCTURE; c o m p u t e r system.
of a
components
the major
bus that c o n e c t s
System bus is a single computer
address bus andcontro bus.
Itconsistsof databus.
DATA BUS: and peripherals.
It is bi-
the processor, memory it
of data between the address of the data,
It is used for the exchange When it issues
allows data flow in both directions.
directional so that it
loads the data through the data bus.

ADDRESS BUS:
or output
between the microprocessor and memory
The address bus contains the connections
which the CPU is processing at that time
devices that carry the signals relating to the addresses
It is unidirectional. Maximum
such as the locations that the CPU is reading from or writing to.
address capacity= 2 Address may be multiplexed with data bus.

CONTROL BUS:
The control bus camies the signals relating to the control and coordination of the various
activities across the computer, which can be set from the control unit within the CPU. It is used
to process data and various operations are performed by microprocessor with the help of control
bus. This is a dedicated bus, because all timing signals are generated
according to control signal.
Some control signals are Read, Write and Opcode fetch etc.

Minimum Mode:-

When only one 8086 microprocessor is to used in a

8086 is used in the minímum mode of microcomputer system, the
operation.
Ncc
B284A MNATR
Clock
Generalo READY ALE
RES RESET STB
RDY
8282
Address BHE
alch
NAddress
Bus
WAT
STATE
GENERATORI a086 CPU

DEN
DTR
L fransceiver
(2)

(Optional for increesed

Deta bus drive)

MOLD Conbrol
RLDA Bus
NTR

The main blocks of

8086 are

1. Clock Generator
2. 8086 CPU
3. 3 address latches
4. 2 transceivers

The clock generator generates the

necessary clock for the CPU by using a crystal and
supplies the same clock to the eady and reset signals of 8086. To make the device work in
minimum mode a high inpul is given to the MX/MX pin.

The address/data pins and address/status pins along with ALE and BHE are connected to
the address latches. Since the device can handle 20 bit address, 3 address latches are connected
together. This address latiches demultiplex the address from the address/data pins and
address/status pins and sends the address to the address bus.

The remaining data is send to the transceiver. The data control signals DEN and DT/R are
connected with the transceiver. So the data can be sent through the data bus. All other minimum
mode signals are conmected to the control bus.
 The status of
memory, read and write signals decides the type of data transfer.
M/IO RD WR OPERATION
0
VOREAD
0 VO WRITE
0 Memory Read
Memory Write

Timing Diagram for Read Operation

ADDSTATUS w
BHA SS
Bus reserved
ADD/DATTA
for datain DKT
RD

DEN

Steps during READ cvcle;

During TI State:

The Address Latch Enable (ALE) pin goes high to initiatea bus cycle.

10
 with DEN
and DT/R should be stable
Derore the trailing edge of ALE, BHE, M/IO, DEN
and DT/R input or DT/R
=
1 for output.
l =
0 for an

During T2 State:
received from
data is
in $3 to S7 and
ddress Is dropped and status is received RD signal is
the tranceiver.
BHE/S7 and DEN are made low to enable
address/data pins,
activated low during T2 state.

During T3 State:
there is no wait
data transfer immediately,
It the memory or 10 interface that perform
T3 state.
state and the data can be put on the bus during

During T4 State:
RD is raised to 1 at the beginning of
When the input data is accepted by the processor,
the memory or 10
device will drop its data signal.
T4, and upon detecting this transition,

Timing Diagram for Write Operation:

T T
CIk

ALE

ADD /STATUS YBIE

ADD /DATA XAsA Valld data D DAwwww

Wwww.
DEN

DT/R

Steps during WRITE cycle:

During TI State:

11
 dependino
o r low g
made high
DHE is
initiate a
bus cycle,
to
high
ALE pin goes
bit data.
bit or 16 the cycle.
upon & throughout
remains low
and this to p r o c e s s o r .
DTR is low from memory
data p r o c e s s o r address
direction of used to latch the
the of ALE Is
It
indicates edge
bus. The falling
the address
Address is put in
from address bus.

During T2 State: T2 to T4.

continues from

put on the
statusline.This activity
RD and DEN status

During T3 State:

Data is put on
the data lines

During T4 State:

RD and DEN are high.

Mode System
Grant Timings
in Minimum
Bus
B u s Request &

CLK

HOLD

tatn

ALDA

indicates in Time Space HOLD (input)

The HOLD and HLDA timing diagram
HLDA (Hold Acknowledge)..
occurs first and then the processor outputs

CONFIGURATIONS -SYSTEMBUS TIMING

MAXIMUM MODE is called maximum mode
is involved, the configuration
When than one processor device work in
& 8288. TO make the
more
are used, 8086
configuration. Here two processors
maximum mode, the MN/MX pin
of 8086 is connected to ground.

12
 LOCAL BUSES

MXww GH CLX MIRC MEMORY FEEAD

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CLK wwwww.www
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READY AMWG AOVANCED MW
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O READ
RESET
ROY CIMR OWC 0WRITE

CPU DTR
MOWO A0VANCED VOW
WIA NIERRYPT
WAIT ACKNOWLEGE
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MRDC: Memory Read Command:

It instructs the memory to put the contents of addressed location on the data bus.

MWTC: Memory Write Command:

It instructs the memory to accepts the data on the data bus and load the data into the
addressed memory location.

IORC: /O Read Command:

it instructs an /O device to put the data contained in the addressed port on the data bus.

IOWC: 1/0 Write Command:

14
 into t n
t nstructis an VO device to accept the data on the data bus and load the data
addressed port.

Timing Diagram for READ Operation:

e bus Ycle R

Ck

AL

ACVE ACU
MM
Add/Status. BHE, A A

Add/Data As
MRDC . w

DT/R A

DEN

During Ti1:

.S0. S1 & $2 are set by the 8086 in the

beginning of clock signal.
It is decoded by the 8288 bus controller

ALE is made high. BHE is made high/low depending upon 8 bit / 16 bit data
.DT/R goes low. Address is put on the address bus
and data is put on the data bus.
During T2:

BHE is pulsed high if it is made low in

TI.
DEN goes high to enable the
transceiver.
MRDC or IORC goes low as
memory read control signal
During T3:

Data is put on the data lines

The status lines SO, SI& $2
becomes inactive
During T3:

15
 MRDC goes high.
DEN goes low.

DT/R goes high.

Timing Diagram for WRITE Operation:

ADDSTATUS BHE
ADDDATA AA Dit out DD
****** A

AMWC o .

AIOWC
MWTCrIOWC

DT/R we.ww

DEN

During Ti:

S0, Si & S2areset by the 8086 and are decoded by 8288.

ALE is made high.
BHE is madehighlow depending upon 8 bit / 16 bit data.
Address is put on the address bus.

During T2:

BHE is pulsed high ifit is made low in TI.

DEN goes high to enable the transceiver.

During T3:

Data is put on the data lines.

The status lines S0, S1 & S2 becomes inactive.
AMWC/AIWC start writing the data. (AMWCI AIWC-Advanced Memory Write
command/ Advanced input write command)
16
 Basic Multiprocessor configurations
1. Co processor configuration
2. Closely coupled configuration

3. Loosely coupled configuration

Co-processor configuration
share.
and external processor(Math co processor)
In coprocessor both the CPU(8086)

VO system
Memory
Bus& control logic

Clock generator

Here 8086 is the master and 8087 act as a slave

8086/80b88 Coprocessor (ie: 8087)

Moitor the
8086 or 8088
ESC Wake up the
coprocessor

Deactivate the
Execute host's !TEST pin
8086 and execute the
instructions
specified operation

Wake up the A.ctivate the

8086 or 8088 TEST pin
WAIT

An instruction to be executed by the co processor is indicated by an ESC prefix or

instruction

18
 The 8086 fetches the instructions
instructions.
instruction sequence and captures its own
The co processor monitors the

simultaneously.
The ESC is decoded by the CPU and co processor
and the co processor captures
The CPU computes the 20 bit address of memory operand
bus to load or store as needed.
the address of the data and obtains control of the

(high) siganl to the TEST pin.

The co processor sends BUSY

8086 instruction the CPU and

co

The CPU the next instruction and if this is an

goes to
processor execute in parallel.
the 8086 must wait until BUSY goes low. (i.e)
lf another instruction occurs
co processor
TEST pin become active.
instruction by the
a WAIT instruction
is put in front of most 8087
To implement this,
assembler.
is active
The WAIT instruction does
the operations (i.e) WAIT until TEST pin
CLOSELY COUPLED CONFIGURATIONN
VO
configurations are similar : i.e share the
same
Coprocessor and closely coupled
Bus & control logic Clock generator.
system ,Memory,
,

The difference between co processor

and closely coupled configuration is here no WAIT
or ESC instruction
is used.

The Communication between 8086 and independent processor is done through memory space

Cosely Coupled Configuratton:

CLOCK

& 0 86

Bus S ystem Bus

Controi
Logic
C proeessor

ndcpende rt
Pocessur
Memory /o

19
 the CPU
through
everything

it does Two
control
ofthe bus, independently

take bus
cannot
control ofthe
Coprocessor
take
may
processor
Coupled
Closely
NOTE: coupled.
cannot be closely
8086's

Independent Processor (8089)

8086/8083

Wa for
request
Set up
message

Fetch the
message

Wake up
ndependent processor Perform
with OUT instruetion requested

Notify
Execute CPU of
8086 completiona
instruction

Wait for redy

or interrupt
reqest

independent processor by sending

o The 8086 sets up a message in memory and wakes up
command to one of its ports.
with
the task in parallel
then accesses the memory to execute
The independent processor
the 8086.

20
 when task is
task by using completed the external
status bit or processor informs the
interrupt request. 8086 about the
In
loosely coupled
LOOSELY COUPLED cONFIGURATION completion of
a
configurationa number of modules
common system
bus to work
of 8086
Each CPU has its as a

own bus control muliprocessor system.

can be
interfaced through
Several CPU's can logic.
form a very
processor or co large
processor attached to system
it
and each
CPU may have
Each
processor has its independent
being the bus master own clock as well as its
own
memory. Each module is
ADVANTAGES capable of
High system
throughput can be achieved by
The system
can be
having more than one CPU.
unit and expanded in modular
form. Each bus
normally resides on
affecting the others in the separate PC board. One canmaster
a module is an
be added or independent
system. removed without
A failure in
one module
the faulty module normally does not affect the
can be
easily detected and breakdown of the entire
replaced. system and
Each bus master
has its own local
greater degree of parallel bus to access
dedicated memory or 10 devices
In
processing can be achieved. so a
a
loosely coupled
tothe shared multiprocessor system more
system bus. Since each master is than one bus master module may have
must be
provided to reslove the bus arbitration nunning independently, extra bus controlaccess
logic. Bus request are resolved on a problem.This extra logic
priority basis. Three scheme for logic is called bus access
1. Daisy establishing priority.
chaining method
2. Polling method

3. Independent method

21
Laosely coupled configuration using 8086:

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1.Daisy Chaining:
In daisy chaining method all masters make use of the same line for making bus
To respond to a bus request signal the controller sends out bus request.
grant signal if the bus busy
signal is inactive. The grant signal serially propagates through each master until it
encounters the first one that is Tequesting access to the bus.
This module blocks the
propagation of the bus grant signal, activates the busy line and gains control of the bus.
Therefore any other requesting module will not receive the
grant signal and the priority is
determined by the physical locations of the modules. The one located closest to the
controller has the highest priority.
22
 low cost.
Advantage: The Daisy chaining method is characterized by its simplicity and

Disadvantage:
Failure of any one master causes the whole system to fail and arbitration is slow due to
the propagation delay of bus grant signal. This delay is proportional to the number of
modules and therefore a daisy chaining system is limited to only a few modules.

Master 1 Master 2 Master N

Bus Access Bus Access Bus Access

Logic Logic Logic

BGR T
Bus BRQ
Controller
BBSY

2. POLLING METHOD
The polling method uses a set of lines sufficient to address each module. In
response to bus
request, the controller generates a sequence of module addresses. Whena
recognizes its address, it activates the busy line and begins to use the bus. requesting
module

Advantage:-Priority can be dynamically changed by altering the polling sequences stored in the
controller.

Master 1 Master 2
Master N
Bus Acce*
Bws Aeces Bs Accem
L.ang
Bus
Controller
TTT
Rotating
Encoder BRO
to N BASY

23
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pair of
has a separate
module
fashion.
Each The
controller

parallel to it.
assigned
priority in
a
resolves has a priority and r e t u r n s
scheme
each pair priority
nis lines and highest
with the
and bus grant request
bus request selects the
which
decoder,
ncludes a priority
bus grant signal.
the corresponding

in the system.
Advantage
of the
number of modules
independent
Arbitration is
Fast and is

Fastest method.

Independent request
design is the
and bus grant lines.
more bus request
Itrequires
LOOSELY COUPLED
Disadvantage:-

TIGHTLY COUPLED
AND
DIFFERENCE BETWEEN
MULTIPROCESSOR
LOOSELY COUPLED
TIGHTLY COUPLED

multiprocessor system
multiprocessor systems ()Loosely-coupled are baesd on
(1)Tightly-coupled
are connected at (often referred to as clusters)
CPUs that standalone single or dual processor
standalone processor
contain multiple access to mutiple
nuie
These CPUs may have interconnected via a
the bus level.
UMA), or odny computers
a central
shared memory (SMP
or
high speed communication system.
in a memory hierarchy
with
may participate

24
both local and shared
memory (NUMA).
(2)Tighdy-coupled systems perform better
are physically smaller than &| (2)
System. loosely-coupled thanLoosely coupled
tightly coupled system physically larger
is
system.
(3) More expensive.
(4) In a (3) Less expensive.
tightly-coupled
system, the delay
Experienced,
from one
when a
message is sent 4) In a
loosely-coupled system, the opposite
computer another is short,
and data rate
to is true: The inter-machine
is high; that
of bits per second is, the number large and the data rate is low. message delay is
that can be
is large. transferred
(5) For example, two
CPU
printed circuit board chips
and
on the same
(5) For example, two
he board areconnected by a 2400 bit/sec modem
wires ctched onto computers connected by
tightly Coupled. likely to be over the
system are certain to be telephone
loosely coupled.
(6) Tightly-coupled systems tend to be much
more energy efñcient than (6)
because considerable clusters. This is that loosely-coupled systems use
realized by economies can
were
be for use in not neccessarily intended components
specifically
designing components to work
together from the beginning
such systems.
Systems. in tighily-coupled

CO PROCESSOR
NUMERIC DATA PROCESSOR (8087)
8087 is a
Multiprocessor
system consists of
coprocessor which has been processors and coprocessors. The numeric
processor 8086. specially designed to work under processor
the control of the
Features of 8087:
3. It
can operate on data of the
from 2 to 10
bytes. inieger, decimal, and real
2. Its
instruction
types, with lengths ranging
set not
aiso only includes various forms
So on
provides many useful fiunctions such as of
addition and
square root, subtraction, but
3 t is
high exponential, tangent, and
numbers in períormance numeric data
about 27 us and processor. It can multiply
A. it follows calculate square root in about two 64-bit real
IEEE 36 us.
. t is muitibus floating point standard.
compatible.
25