DESIGNING WITH GIGABIT SERIAL I/O

Another important aspect of bypassing is placement. As a general rule, the larger the cap value,
the less critical the placement. The smallest values want to go as near a power and ground pin as pos-
sible. One way to do this that is often available when using MGTS inside FPGAs is to remove the trace
and via of unused general IO to make room for the bypassing. This is shown in Figure 4-19.

FIGURE 4-19: Removing Trace and Via

Shielding
Any multi-gigabit signal needs to be isolated from interfering, and being interfered on, by other sig-
nals, whether the signal is on a board, cable, or going through a connector. This is accomplished by
isolation and shielding with connectors and cables. On PCBs, multi-gigabit signals should be isolated
from other signals by using extra space, and should be isolated from parallel traces on other layers by
ground or power planes.

Boards, Connectors, and Cables

When designing a system that uses multi-gigabit serial streams, component selection and board
design are critical. The wrong connector, a marginal stack-up, or the wrong PCB material can com-
pletely ruin an MGT project.

Printed Circuit Board Design

Designing a PCB for multi-gigabit operation is a challenge for even the best PCB designers. Differen-
tial traces must be matched, geometry for impedance-controlled differential pairs must be adjusted as
layers are added, and power distribution needs to be critically analyzed. And while there will be thou-
sands of individual trade-offs and decisions, an overall list of issues can help. That list of issues might
include the following:
• Material selection
• Stack-up/board thickness
• Power and ground planes
• Differential pairs
• Differential trace width and spacing
• Vias
• Space between pairs
• Ground guards between pairs
• Power layout.
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Material Selection
While FR-4 has become the standard board material for a number of years, some lower loss alterna-
tives have become readily available. A general guideline is that for total trace length less than 20
inches and speed at or below 3.125 Gb/s, FR-4 may be acceptable. If we need longer traces or faster
speed, we should seriously consider using a high-speed material such as ROGERS 3450.
Stack-up/Board Thickness
Once we have selected a material, the next step will be to devise a general stack-up plan. This may
change as the number of signal layers is determined, but we will need to keep our stack-up in mind
throughout the processes. Do not forget to add an adjacent power and ground plane layer to improve
bypassing.
Power and Ground Planes
We need to think about how we are going to distribute all those special analog voltages. We may need
to consider separate planes for each analog power. Isolating and filtering ground planes that are the ref-
erence plane for the multi-gigabit signals might be a good idea. We could also consider eliminating
the digital power supply plane from signal areas that operate at less than gigabit speed.
Differential Pairs
For best results, we should run differential pairs tightly coupled and closely matched. Trace length
matching is essential. In FR-4, a 100-mil (1 tenth of an inch) difference in trace length results in
approximately 18 picoseconds of difference between the positive and negative signal. This is also
enough skew to start causing problems. And, while a tenth of an inch may sound like a lot if we just
use normal trace routing from one BGA to another, it is easy to end up with 300 - 400 mils of differ-
ence. If our PCB tool has an auto-trace matching, we need to use it. In general, we will want 50 mils
or less difference in differential trace lengths.
Differential Trace Width and Spacing
This will need to be worked out for each particular stack-up. The board foundry can be a valuable
resource, but we need to make sure they know what they are doing. Some published guidelines recom-
mend against letting the PCB vendor do these calculations. We need to make sure they are using a
field solver tool to figure the width and spacing of tightly coupled pairs. Then we need to adjust our
boards accordingly. One technique we definitely should not use is just choosing a close geometry and
then letting the board foundry adjust the impedance with over- or under-etching. If we have a local,
in-house field solving program and the expertise to use it, that is even better.
Sample geometry is shown in Figure 4-20 and Figure 4-21.

W1 = 6.29 mil (0.160 mm)

W1 S W2 W2 = 6.29 mil (0.160 mm)
S = 10 mil (0.254 mm)
H = 5.0 mil (0.127 mm)
Trace Trace
Z01 = 55.3
Z02 = 55.3
Er = 4.3 H Z0DIFF = 100
Dielectric
Reference Plane

FIGURE 4-20: Sample Geometry: Microstrip Edge-Coupled Differential Pair

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Reference Plane

W1 = 3.0 mil (0.076 mm)

H1
W2 = 3.0 mil (0.076 mm)
W1 S W2 S = 6.85 mil (0.174 mm)
H1 = 10.0 mil (0.254 mm)
Trace Trace
H2 = 10.0 mil (0.254 mm)
Z01 = 64.8
Z02 = 64.8
Z0DIFF = 100
Dielectric H2
Er = 4.3

Reference Plane

FIGURE 4-21: Sample Geometry: Stripline Edge-Coupled Differential Pair

Vias
Changing layers on the multi-gigabit differential traces should be avoided whenever possible. If a layer
transition is required, we must be extra careful. First, we must provide an intact return path. To do
this, we must couple the reference plane of layer A to the reference plane of layer B. The ideal situation
is to have both reference planes be ground. In this case, the return path is created by placing a via con-
necting the planes in close proximity to the via used to make the transition. Figure 4-22 illustrates the
technique.

Ground Path Tie Vias

Ground Path Tie Vias

Layer B

Layer B

Layer Transfer Vias

Layer A

Layer A

Layer Transfer Vias

FIGURE 4-22: Vias with Both Reference Planes as gnd

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If reference planes are not common (one is gnd and one is pwr), then a 0.01 μF capacitor should be
placed across the two planes as close to the transition via as possible. This is illustrated in Figure 4-23.

0.01 uF Cap

Ground Via Power Via

Layer B

Layer Transfer Vias Layer A

0.01 uF Cap

Layer Transfer Vias

Ground Via Power Via

FIGURE 4-23: Vias if Reference Planes are Not Common

Another problem with vias is that they represent a stub. Clearly, we know it is a bad idea to intro-
duce stubs in our transmission line (see Figure 4-24).

FIGURE 4-24: Transmission Line

Consider a via that transfers a signal from an inner layer to the top layer. The via also goes to the
bottom layer, and that unused portion of the via is a stub. One method to avoid this stub is a technique
called back drilling. After plating, the unused portion of the via is removed by drilling (as shown with
drill bit in lower portion of Figure 4-25).

FIGURE 4-25: Back Drilling Process

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Any design over 5 Gb/s should seriously consider back drilling vias (see Figure 4-26).

FIGURE 4-26: Back Drilled vs. Non-Back Drilled Channels

Space Between Pairs

It is important to maintain a good amount of distance between differential pairs carrying multi-giga-
bit signals and other traces. One general rule is that at least five times the space between the two sig-
nals of the pair should be placed between adjacent pairs (Figure 4-27).

FIGURE 4-27: Space Between Pairs

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Ground guards between pairs

Another technique is to route a ground guard in parallel to the differential traces. Tying the guard
plane back to the reference plane using a via in parallel to the trace often improves this shielding
method (Figure 4-28).

GND

GND
FIGURE 4-28: Ground Guards Between Pairs

Power layout
Many of the items discussed in the Powering MGT section have board layout implications as well. The
placement of the ferrite beads (Figure 4-29) and capacitors that filter the analog power supplies rela-
tive to the supply pins and the signal traces (Figure 4-30) must be carefully considered.

FIGURE 4-29: Placement of Ferrite Beads

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Large Bypass

Small Bypass
Near Power Pins Medium
Bypass

Analog Power Filters

FIGURE 4-30: Power Layout

Connector Selection
Only high-speed connectors should be used for multi-gigabit signals. Like everything else in the path,
a high-speed connector has controlled impedance. While the connector impedance is never as contin-
uous as a PCB trace, high-speed connectors are much better than normal connectors (Figure 4-31).
Early high-speed connectors were designed for both single-ended and differential signals. The latest,
fastest connectors are designed specifically for differential pairs. Here are a few examples of high-speed
connectors:
• Gbx
• VHDM-HSD
• VHDM
• HDM
• High Density Plus
• Z-PACK HM-Zd

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• Z-PACK HS3

FIGURE 4-31: High-Density 10 Gb/s Copper Interconnect System

If designing to a predefined protocol or bus, the connector selection may have already been made
by the standard. If not, some questions to consider in addition to normal connector issues such as num-
ber of signals, density, and size include:
• bandwidth
• shielding
• differential pairs
• maximum edge rate.
Bandwidth
Consider the speed of the part and how fast has it been successfully used. Many early gigabit connec-
tors were originally specified at 1 or 2 Gb/s, but have been widely used at 3 Gb/s (Figure 4-32).

FIGURE 4-32: High-Speed 2G Connectors

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Shielding
Consider how the signals are shielded from each other and from other outside influences. There may be
shielding issues on the sides of the connectors.
Differential Pairs
Was the connector designed for differential pairs or is it only adaptable to differential pairs?
Maximum Edge rate
Have we considered the maximum edge rate? A common source of cross-talk is found in connectors if
the edges of the signals entering the connector are too fast. We must know what our connector can
handle and what we expect to send through it.

Cable Selection
If going box-to-box in a custom application, we will need to select a cable/connector scheme. The first
thing to consider is how far the signals will travel, and if the signal can go that distance using copper
or if we will have to convert to optical. If distance is under 20 meters and speed under 6 gigabits, then
copper may work.
One cable used in many multi-gigabit applications is Infiniband cables (Figure 4-33). Originally
designed for 2.5 Gb/s operation in Infiniband applications, the cable has been adapted and slightly
modified for FiberChannel, CX4 (10-Gigabit Ethernet) and other uses. It comes in 1, 4, and 12-pair
variations.

FIGURE 4-33: Infiniband Cables

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Another interesting cabling option is cable assemblies designed to plug into backplane-type con-
nectors (Figure 4-34 and Figure 4-35). These assemblies can be used inside cabinets and some include
EMI shielding to allow box- to-box connectivity.

FIGURE 4-34: Backplane Cable Assemblies

FIGURE 4-35: More Backplane Cable Assemblies

Many other cables are being investigated for multi-gigabit uses, including coax and the familiar
Cat 5 twisted pair.

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