Introduction to VLSI Design

Ideas, Design Flow, Design

Strategy
 Introduction
• The electronics industry has achieved tremendous growth over the last few
decades, mainly due to the rapid advances in integration technologies and large-
scale systems design.
• The use of integrated circuits in high-performance computing, telecommunications,
and consumer electronics has been growing at a very fast pace. This trend is
expected to continue, with very important implications for VLSI and systems design.
• As more and more complex functions are required in various devices, the need to
integrate these functions in a small package is also increasing.
• The level of integration as measured by the number of logic gates in a monolithic
chip has been steadily rising for almost three decades, mainly due to the rapid
progress in processing technology and interconnect technology
Evolution of Logic Complexity in Integrated
Circuits
 Moore’s Law
• M o o r e ’s l a w i s b a s i c a l l y a
prediction on the growth rate of
logic complexity made by
Gordon Moore. It says that the
transistor count per chip
increases exponentially with
years (approximately two times
every eighteen months).
VLSI Design Flow

HDL

SPICE

Layout Design tools

 VLSI Design Strategy
• Design Hierarchy
A larger system with unmanageable complexity is
further divided into smaller parts. This decomposition
process will continue until and unless the complexity
of the generated blocks is manageable.
For example, one eight-bit full adder can be
decomposed into eight single-bit adder.
Now it is much easier to design a single-bit adder.
Each single bit adder can be further divided into sum
and carry parts. Finally, at the end of the design
process, all eight adders are connected and form the
eight-bit adder. The hierarchy process is shown in the
figure
 VLSI Design Strategy
• Regularity: At the time of decomposition, the
designer must look for not only simple blocks but
also similar types of blocks as much as possible.
This strategy reduces the design time. For
example, if one designer designs a single-bit
adder, then the same design will be repeated to
form a complete eight bit adder quickly.
 VLSI Design Strategy
• Modularity: After decomposition, the generated
sub-modules must have their well-defined,
independent functions and interfaces. This
property permits the designer to test each sub-
module independently and to allow the design of
multiple components parallelly (since each
module is independent of the other).
 VLSI Design Strategy
• Locality: This property ensures that the
interconnection between sub-modules should
be within local places. That means, the
modules should be placed close to each other
to avoid long-distance wiring and thus reduce
interconnect delays and also fabrication costs.
 Gajski's Y-Chart
• In VLSI design flow, there are three design
domains: Functional or Behavioral, structural,
and geometric or physical domain. They are
strongly correlated to each other.
• The relationship between the three domains is
represented by Gajski's Y chart.
Gajski's Y-Chart
 Gajski's Y-Chart
• The behavioral description of an algorithm can be
implemented by using a processor.
• The process can be designed using the layout of the chip i.e.
floorplanning.
• Similarly, in the behavioral domain, one algorithm may
consist of several finite state machines (FSM) to execute the
different tasks.
• At the structural level, the FSM can be realized using some
memory elements such as registers. The same can be
designed as a module during chip layout and floorplanning.
 Gajski's Y-Chart
• The next level of abstraction starts with module
description, which can be represented by leaf cell i.e. a
group of basic logic gates, flip flops, etc.
• The same can be placed using a cell placement inside
the chip.
• In the next level of abstraction, the Boolean equation is
used to describe the functionalities of a module, which
can be structurally implemented using transistors
followed by the mask/layout of a single transistor.
 VLSI Design Styles
• A VLSI system sometimes is referred to as Application
Specific Integrated Circuit (ASIC).
There are several methodologies to implement a VLSI system.
Each one having its own advantages and drawbacks.
They are
(1) Full custom design
(2) Semi-custom design
(3) Programmable design style.
 VLSI Design Styles
• Full Custom Design Style
• In this design, the designer starts from scratch.
• This might be because existing cell libraries are not fast
enough, or the logic cells are not small enough or consume
too much power.
• As a designer, you can optimize your design for speed, power,
and area requirements.
• The full custom design approach needs more time and the
cost of prototyping is higher compared to other design styles.
 VLSI Design Styles
• Semi Custom Design:
• In this type of design process, some part of the design is customized.
• That means the designer can pick up a pre-designed and tested cell from
the cell library.
• Each cell library may contain an adder, subtractor, multiplier, flip flops, etc.
• For a single design, category say adder, there may be different variants
with different speed and power ratings.
• This drastically reduces design time and cost.
• This is further divided into two categories: standard cell-based and gate
array-based design.
 VLSI Design Styles
• Standard Cell based design
• In this approach, the designer uses pre-designed logic cells such as gates (AND, OR,
NOR, NAND, etc.), multiplexers, flip flops, etc., and they are commonly known as
standard cells.
• Those pre-designed and tested cells are stored in a library. Different cells with
different speed grades, power, and area requirements are also available.
• The chip designer only defines the placement and interconnections between
different cells. By using stand cell, a designer can save time, and risk of failure by
using a pre-designed tested, and characterized cell library.
• The disadvantage of this type of design approach is the expense of purchasing the
cell library. Also, it may take time to interconnect all layers. The average
manufacturing lead time is six to eight weeks.
 VLSI Design Styles
• Gate Array based design:
• In this design style, the transistors are predefined on a silicon wafer.
These are called a base array or base cell.
• Only the top few layers of metal which are used to make
interconnections are customized.
• The designer chooses a pre-verified gate array library of logic cells.
These are termed as "macros".
• The designer needs to define the interconnections between the
base array. Depending upon the configuration of base cells, there
are three different types of gate array-based design, (1) channel-
less (2) Channelled, and (3) Structured gate array.
 VLSI Design Styles
• These are some of the most popular options among
the designer and available in the market which are sold
at a large volume at affordable cost. These options are
adopted by designers for faster prototyping. Since they
are designed for a specific application, sometimes they
are also termed as "Programmable ASIC".
• There are two basic types of programmable ASICs. One
is a Programmable logic device (PLD) and another one
is Field programmable gate array (FPGA).
 VLSI Design Styles
• PLDs use programmable AND, OR gates where one programmable switch is
placed. The connection is established by activating these switches.
• They may be one-time programmable or can be re-programmable in
nature. The designer only implements the logic function in a CAD tool and
after synthesis, a bit file (binary file) is generated.
• The software-generated bit file takes care of defining interconnection
between different logic gates by activating corresponding MOS switches.
They are suitable for small to medium-scale logic design.
• Due to the use of programmable switches, generally, PLDs are not suitable
for high-speed operations. Examples of PLDs: Programmable logic array
(PLA), Programmable array logic (PAL), Complex programmable logic
devices (CPLD).
Programmable Logic Devices
Field Programmable Gate Array (FPGA)
• FPGA uses SRAM, multiplexers as core components.
• The logic is implemented using the lookup table (LUT) approach. The combination
of several LUTs, flip flops, and the mux is called a configurable logic block (CLB).
• S i m i l a r to P L D s , p ro g ra m m a b l e i nte rc o n n e c t s a re u s e d to e sta b l i s h
interconnections between different CLBs. Input/output buffers are used to connect
data with external pins.
• Design time is faster than PLDs. Hardware description language is used to describe
the logic function. After synthesis and successful placement, routing analysis, the
bit file is transferred to FPGA and it is configured as the required logic functions.
• Xilinx, Altera, Actel are the manufacturer of FPGA. Popular FPGA categories are
SPARTAN, VIRTEX series from Xilinx, and also others.
Field Programmable Gate Array (FPGA)