Integrated Circuit 2

ECE 430

Lecture 9: Design flow of Hardware Implementation

Dr. Emad Badry

 Design Methodology

❑ VLSI design is a sequential process of generating the physical layout of an IC, starting from the specification of that
circuit. It can be fully or semi-automated using numerous software called electronic design automation (EDA) or
computer aided design (CAD) tools.

❑ The concept or idea is first documented in a formal language and then translated into register transfer level (RTL)
using hardware description languages (HDL) such as Verilog and VHDL. The RTL netlist is then complied and tested
to check if the functionality expected is correctly described.

❑ Some major constraints are less area, low power, and high speed. Taking the behavioral netlist and design constraints,
different synthesis styles have come up with optimum hardware, which meet all the constraints and generate correct
functional output.
 Hierarchical Abstraction

❑ Hierarchical decomposition or ‘divide and conquer’ is a useful methodology that partitions the entire system into its
components. The components are again partitioned into modules and this process continues until the basic building
blocks are reached.
Design Flow
 Design Styles

❑ According to the application, cost of production, performance, and the volume of production, there are different VLSI
design styles that are followed to implement a chip. Each of the styles has its own advantages and disadvantages and is
chosen on the basis of the target application. The commonly used design styles are as follows:

• Field programmable gate array (FPGA) design

• Gate array design
• Standard cell-based design
• Full-custom design
• Semi-custom design
• Programmable logic device (PLD)
Field Programmable Gate Array (FPGA) Design

Field programmable gate array (FPGA) is a fully fabricated IC chip in which the
interconnections can be programmed to implement different functions. An FPGA chip
has thousands of logic gates which are to be connected to implement any logic
function.
Gate Array Design

In a gate array (GA) structure, the transistors are fabricated on the silicon wafer. But the interconnections are not fabricated.
The metal mask layers are customized It can also be used for the prototype development in short time, ranked after the FPGA.
GA-based design time typically varies from a few days to a few weeks. Depending on the array structure, the GA are of the
following three types:
• Channelled
• Channel-less
• Structured
Standard Cell-based Design
The standard cell-based integrated circuit refers to a class of integrated circuits which uses the pre-designed, pre-tested,
and pre-characterized standard cells. The standard cells include basic logic gates (AND, OR, NAND, NOR, XOR, XNOR,
NOT, etc.), some mega cells (such as multiplexer, full-adder, decoder, etc.), sequential elements (such as D flip-flop, scan-
FF, flip-flop with direct set/reset/clear inputs, registers, etc.), input–output buffers (I/O cells), and some special cells. All
these standard cells are designed, tested, and characterized and put in a database which is known as a standard cell library.
In the standard cell-based architecture, the standard cells are placed in rows to build the integrated circuit chip. However,
this design style also includes the already designed mega modules or fixed blocks.
Semi-custom Design
In this style of design, almost all the basic building blocks are used from the standard cell library. Only few cells are
designed from the beginning, which are not available in the standard cell library or to be optimized for a specific target.
This approach is faster compared to the full-custom style but slower than the standard cell-based design.

Programmable Logic Device (PLD)

Programmable logic devices (PLDs) are standard products, which can be programmed to obtain the desired functionality
required for a specific application. The programming can be done either by the end user or by the manufacturer.
VLSI Design using Computer-aided Design Tools
Functional Specification and Verification
In the very first step, the functionality is specified in a very formal hardware description language (HDL). For example, let
us consider that we have to build a VLSI circuit which will multiply binary numbers. Then the multiplier needs to be
specified in detail. For example, whether the multiplier will multiply signed numbers or unsigned numbers. Depending on
the type of operands, the architecture of the multiplier can be decided. Again, the size of the operands must be specified, that
is the number of bits; 4-bit, 8-bit, or 16-bit multiplier. Then the constraints can be imposed on the design, such as area,
power, and timing constraints.
 Logical Design and Verification

The next step after the functional verification is the logic design step. In this step, the design is synthesized from the HDL
specifications using a set of design constraints and the cell library. It basically maps the design to the process technology
and the logic cells already pre-designed, pre-characterized, and pre-tested in the cell library. The synthesis process always
tries to meet the design constraints such as area, speed, and power.
Circuit Design and Verification
In the circuit design phase, the design is implemented at the
transistor level. The transistor level design can be either a
schematic design or a SPICE netlist to describe the circuit.
SPICE is circuit simulation software which is widely used for
circuit design and simulation. After describing the circuit
components and their connectivity, the input stimulus are
applied to the circuit and then simulated to check the output
voltage, current, or waveform.
Physical Design and Verification
The next phase is the physical design. The physical design phase converts the netlist into a geometric
representation. The outcome is called a layout. The physical design phase mainly involves the following five
steps:
• Circuit or logic partitioning
• Floorplanning
• Placement
• Routing
• Compaction and verification
Circuit or Logic Partitioning

In the partitioning process, the large circuit is partitioned into a

number of subcircuits (called blocks). Factors such as number of
blocks, block sizes, interconnection between blocks, critical delay,
etc., are considered during the circuit partitioning.

Floorplanning

This step sets up a plan for a good layout. It tentatively places the
modules (modules can be blocks, functional units, etc.) at an early
stage when details such as shape, area, I/O pin positions of the
modules, etc., are not yet fixed.
Placement

In this step, the exact placement of the modules (modules can be gates,
standard cells) are done. The details of the module design are known in this
phase. The main goal of placement is to minimize the total area, delay,
congestion, interconnect metrics, etc.

Routing

This step completes the interconnections among modules. Factors such

as critical path, clock skew, crosstalk, congestion, repeater placement,
wire spacing, etc., are considered during the routing. The routing
problem is divided into two problems, global routing and detailed
routing. In the global routing steps, the plan for the interconnection is
prepared and in the detailed routing step, the actual interconnections
are made.