ADC1205/ADC1225 12-Bit Plus Sign mP Compatible A/D Converters

June 1994

ADC1205/ADC1225 12-Bit Plus Sign

mP Compatible A/D Converters
General Description Key Specifications
The ADC1205 and ADC1225 are CMOS, 12-bit plus sign Y ResolutionÐ12 bits plus sign
successive approximation A/D converters. The 24-pin Y Linearity ErrorÐ g 1 LSB
ADC1205 outputs the 13-bit data result in two 8-bit bytes, Y Conversion TimeÐ100 ms
formatted high-byte first with sign extended. The 28-pin
ADC1225 outputs a 13-bit word in parallel for direct inter-
face to a 16-bit data bus.
Features
Negative numbers are represented in 2’s complement data Y Compatible with all mPs
format. All digital signals are fully TTL and MOS compatible. Y True differential analog voltage inputs
A unipolar input (0V to 5V) can be accommodated with a Y 0V to 5V analog voltage range with single 5V supply
single 5V supply, while a bipolar input (b5V to a 5V) re- Y TTL/MOS input/output compatible
quires the addition of a 5V negative supply.
Y Low powerÐ25 mW max
The ADC1205C and ADC1225C have a maximum non-lin- Y Standard 24-pin or 28-pin DIP
earity of 0.0224% of Full Scale.

Connection and Functional Diagrams

Dual-In-Line Package

TL/H/5676–1
Top View

Dual-In-Line Package

TL/H/5676 – 3

See Ordering Information

Top View TL/H/5676–2

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation TL/H/5676 RRD-B30M115/Printed in U. S. A.

 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions (Notes 1 & 2)
If Military/Aerospace specified devices are required, Temperature Range TMINsTAsTMAX
please contact the National Semiconductor Sales ADC1205CCJ, ADC1225CCD b 40§ C s TA s a 85§ C
Office/Distributors for availability and specifications. ADC1205CCJ-1, ADC1225CCD-1 0§ CsTAs70§ C
Supply Voltage (DVCC and AVCC) 6.5V Supply Voltage (DVCC and AVCC) 4.5 VDC to 6.0 VDC
Negative Supply Voltage (Vb) b 15V to GND
Negative Supply Voltage (Vb) b 15V to GND
Logic Control Inputs b 0.3V to a 15V
Voltage at Analog Inputs
[VIN( a ), VIN(b)] (Vb)b0.3V to VCC a 0.3V
Voltage at All Outputs, VREF, VOS b 0.3V to (VCC a 0.3)V
Input Current per Pin g 5mA
Input Current per Package g 20mA
Storage Temperature Range b 65§ C to a 150§ C
Package Dissipation at TA e 25§ C 875 mW
Lead Temp. (Soldering, 10 seconds) 300§ C
ESD Susceptibility (Note 12) 800V

Electrical Characteristics
The following specifications apply for DVCC e AVCC e 5V, VREF e 5V, fCLK e 1.0 MHz, Vb e b5V for bipolar input range, or
Vb e GND for unipolar input range unless otherwise specified. Bipolar input range is defined as b5.05V s VIN( a ) s 5.05V;
b 5.05V s VIN( b ) s 5.05V and l VIN( a ) b VIN( b ) l s 5.05V. Unipolar input range is defined as b 0.05V s VIN( a ) s 5.05V;
b 0.05V s VIN( b ) s 5.05V and l VIN( a ) b VIN( b ) l s 5.05V. Boldface limits apply from TMIN to TMAX; all other limits TA e TJ
e 25§ C (Notes 3, 4, 5, 6, 7).

ADC1205CCJ, ADC1225CCD ADC1205CCJ-1, ADC1225CCD-1

Tested Design Tested Design Limit
Parameter Conditions Typ Typ
Limit Limit Limit Limit Units
(Note 8) (Note 8)
(Note 9) (Note 10) (Note 9) (Note 10)
CONVERTER CHARACTERISTICS
Linearity Error Unipolar Input
ADC1205CCJ, ADC1225CCD Range g1 LSB
ADC1205CCJ-1, ADC1225CCD-1 (Note 11) g1 g1 LSB
Unadjusted Zero Error Unipolar Input g2 g2 g2 LSB
Range
Unadjusted Positive and Negative Unipolar Input g 30 g 30 g 30 LSB
Full-Scale Error Range
Negative Full-Scale Error Unipolar Input g (/2 g (/2 LSB
Range, Full
Scale Adj. to
Zero
Linearity Error Bipolar Input
ADC1205CCJ, ADC1225CCD Range g2 LSB
ADC1205CCJ-1, ADC1225CCD-1 (Note 11) g2 g2 LSB
Unadjusted Zero Error Bipolar Input g2 g2 g2 LSB
Range
Unadjusted Positive and Negative Bipolar Input g 30 g 30 g 30 LSB
Full-Scale Error Range
Negative Full-Scale Error Bipolar Input g2 g2 g2 LSB
Range, Full
Scale Adj. to
Zero
Maximum Gain Temperature 6 15 6 15 ppm/§ C
Coefficient
Maximum Offset Temperature 0.5 1.5 0.5 1.5 ppm/§ C
Coefficient
Minimum VREF Input Resistance 4.0 2 4.0 2 2 kX
Maximum VREF Input Resistance 4.0 8 4.0 8 8 kX

2
 Electrical Characteristics (Continued)
The following specifications apply for DVCC e AVCC e 5V, VREF e 5V, fCLK e 1.0 MHz, Vb e b5V for bipolar input range, or
Vb e GND for unipolar input range unless otherwise specified. Bipolar input range is defined as b5.05V s VIN( a ) s 5.05V;
b 5.05V s VIN( b ) s 5.05V and l VIN( a ) b VIN( b ) l s 5.05V. Unipolar input range is defined as b 0.05V s VIN( a ) s 5.05V;
b 0.05V s VIN( b ) s 5.05V and l VIN( a ) b VIN( b ) l s 5.05V. Boldface limits apply from TMIN to TMAX; all other limits TA e TJ
e 25§ C (Notes 3, 4, 5, 6, 7).

ADC1205CCJ, ADC1225CCD ADC1205CCJ-1, ADC1225CCD-1

Tested Design Tested Design Limit
Parameter Conditions Typ Typ
Limit Limit Limit Limit Units
(Note 8) (Note 8)
(Note 9) (Note 10) (Note 9) (Note 10)
CONVERTER CHARACTERISTICS (Continued)
Minimum Analog Input Unipolar Input GND-0.05 GND-0.05 GND-0.05 V
Voltage Range
Bipolar Input b VCC b 0.05 b VC b 0.05 b VCC b 0.05 V
Range
Maximum Analog Input Unipolar Input VCC a 0.05 VCC a 0.05 VCC a 0.05 V
Voltage Range
Bipolar Input VCC a 0.05 VCC a 0.05 VCC a 0.05 V
Range
DC Common-Mode Error g (/8 g (/2 g (/8 g (/2 g (/2 LSB
Power Supply Sensitivity AVCC e DVCC e
5V g 5%,
Vb eb5V g 5%
Zero Error g */4 g */4 g */4 LSB
Positive and Negative g */4 g */4 g */4 LSB
Full-Scale Error
Linearity Error g (/4 g (/4 g (/4 LSB
DIGITAL AND DC CHARACTERISTICS
VIN(1), Logical ‘‘1’’ Input VCC e 5.25V, 2.0 2.0 2.0 V
Voltage (Min) All Inputs except
CLK IN
VIN(0), Logical ‘‘0’’ Input VCC e 4.75V, 0.8 0.8 0.8 V
Voltage (Max) All Inputs except
CLK IN
IIN(1), Logical ‘‘1’’ Input VIN e 5V 0.005 1 0.005 1 mA
Current (Max)
IIN(0), Logical ‘‘0’’ Input VIN e 0V b 0.005 b1 b 0.005 b1 mA
Current (Max)
VT a (Min), Minimum Positive- CLK IN 3.1 2.7 3.1 2.7 2.7 V
Going Threshold Voltage
VT a (Max), Maximum Positive- CLK IN 3.1 3.5 3.1 3.5 3.5 V
Going Threshold Voltage
VTb (Min), Minimum Negative- CLK IN 1.8 1.4 1.8 1.4 1.4 V
Going Threshold Voltage
VTb (Max), Maximum Negative- CLK IN 1.8 2.1 1.8 2.1 2.1 V
Going Threshold Voltage
VH(Min), Minimum Hysteresis CLK IN 1.3 0.6 1.3 0.6 0.6 V
[VT a (Min)bVTb(Max)]
VH(Max), Maximum Hysteresis CLK IN 1.3 2.1 1.3 2.1 2.1 V
[VT a (Max)bVTb(Min)]

3
 Electrical Characteristics (Continued)
The following specifications apply for DVCC e AVCC e 5V, VREF e 5V, fCLK e 1.0 MHz, Vb e b5V for bipolar input range, or
Vb e GND for unipolar input range unless otherwise specified. Bipolar input range is defined as b5.05V s VIN( a ) s 5.05V;
b 5.05V s VIN( b ) s 5.05V and l VIN( a ) b VIN( b ) l s 5.05V. Unipolar input range is defined as b 0.05V s VIN( a ) s 5.05V;
b 0.05V s VIN( b ) s 5.05V and l VIN( a ) b VIN( b ) l s 5.05V. Boldface limits apply from TMIN to TMAX; all other limits TA e TJ
e 25§ C (Notes 3, 4, 5, 6, 7).

ADC1205CCJ, ADC1225CCD ADC1205CCJ-1, ADC1225CCD-1

Parameter Conditions Tested Design Tested Design Limit

Typ Typ Units
Limit Limit Limit Limit
(Note 8) (Note 8)
(Note 9) (Note 10) (Note 9) (Note 10)
DIGITAL AND DC CHARACTERISTICS (Continued)
VOUT(1), Logical ‘‘1’’ Output VCC e 4.75V
Voltage (Min) IOUT eb360 mA 2.4 2.4 2.4 V
IOUT eb10 mA 4.5 4.5 4.5 V
VOUT(0), Logical ‘‘0’’ Output VCC e 4.75V 0.4 0.4 0.4 V
Voltage (Max) IOUT e 1.6 mA
IOUT, TRI-STATE Output Leakage VOUT e 0V b 0.01 b3 b 0.01 b 0.3 b3 mA
Current (Max) VOUT e 5V 0.01 3 0.01 0.3 3 mA
ISOURCE, Output Source Current VOUT e 0V b 12 b 6.0 b 12 b 7.0 b 6.0 mA
(Min)
ISINK, Output Sink Current (Min) VOUT e 5V 16 8.0 16 9.0 8.0 mA
DICC, DVCC Supply Current (Max) fCLK e 1 MHz, CS e 1 1 3 1 2.5 3 mA
AICC, AVCC Supply Current (Max) fCLK e 1 MHz, CS e 1 1 3 1 2.5 3 mA
Ib, Vb Supply Current (Max) fCLK e 1 MHz, CS e 1 10 100 10 100 100 mA

AC Electrical Characteristics
The following specifications apply for DVCC e AVCC e 5.0V, tr e tf e 20 ns and TA e 25§ C unless otherwise specified.
Tested Design
Typ Limit
Parameter Conditions Limit Limit
(Note 8) Units
(Note 9) (Note 10)
fCLK, Clock Frequency MIN 1.0 0.3 MHz
MAX 1.0 1.5 MHz
Clock Duty Cycle MIN 40 %
MAX 60 %
TC, Conversion Time MIN 108 1/fCLK
MAX 109 1/fCLK
MIN fCLK e 1.0 MHz 108 ms
MAX fCLK e 1.0 MHz 109 ms
tW(WR)L, WR Pulse Width MAX 220 350 ns
tACC, Access Time (Delay from CL e 100 pF 210 340 ns
Falling Edge of RD to
Output Data Valid) (Max)
t1H, t0H, TRI-STATE Control (Delay RL e 2k, CL e 100 pF 170 290 ns
from Rising Edge of RD to
Hi-Z State) (Max)
tPD(READYOUT), RD or WR to 250 400 ns
READYOUT Delay (Max)
tPD(INT),RD or WR to Reset of INT 250 400 ns
(Max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating ratings.
Note 2: All voltages are measured with respect to ground, unless otherwise specified.
Note 3: A parasitic zener diode exists internally from AVCC and DVCC to ground. This parasitic zener has a typical breakdown voltage of 7 VDC.

4
AC Electrical Characteristics (Continued)
Note 4: Two on-chip diodes are tied to each analog input as shown below.

TL/H/5676 – 4
Errors in the A/D conversion can occur if these diodes are forward biased more than 50 mV. This means that if AVCC and DVCC are minimum (4.75 VDC) and Vb is
minimum ( b 4.75VDC), full-scale must be s 4.8VDC.
Note 5: A diode exists between analog VCC and digital VC.

TL/H/5676 – 20
To guarantee accuracy, it is required that the AVCC and DVCC be connected together to a power supply with separate bypass filters at each VCC pin.
Note 6: A diode exists between analog ground and digital ground.

TL/H/5676 – 21
To guarantee accuracy, it is required that the analog ground and digital ground be connected together externally.
Note 7: Accuracy is guaranteed at fCLK e 1.0 MHz. At higher clock frequencies accuracy may degrade.
Note 8: Typicals are at 25§ C and represent most likely parametric norm.
Note 9: Tested and guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 11: Linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line which passes through positive full scale and zero,
after adjusting zero error. (See Figures 1b and 1c ).
Note 12: Human body model; 100 pF discharged through a 1.5 kX resistor.

TL/H/5676 – 8
FIGURE 1a. Transfer Characteristic

5
 TL/H/5676 – 22
FIGURE 1b. Simplified Error Curve vs. Output Code Without Zero and Fullscale Adjustment

TL/H/5676 – 23
FIGURE 1c. Simplified Error Curve vs. Output Code after Zero/Fullscale Adjustment

TL/H/5676 – 7
FIGURE 2. TRI-STATE Test Circuits and Waveforms

6
Timing Diagrams

TL/H/5676 – 15

FIGURE 3. Timing Diagram

TL/H/5676 – 13

FIGURE 4. Ready Out

TL/H/5676 – 14

FIGURE 5. Data Out

7
8
TL/H/5676 – 5
FIGURE 6. Functional Block Diagram
Functional Description
1.0 THE A/D CONVERSION Setting CC enables the UPDATE LOGIC [12]. This logic
controls the transfer of data from the SAR LOGIC to the
1.1 STARTING A CONVERSION OUTPUT LATCH [6] and resets the internal logic in prepa-
When using the ADC1225 or ADC1205 with a microproces- ration for a new conversion. This means that when EOC
sor, starting an A-to-D conversion is like writing to an exter- goes high, a new conversion can be immediately started
nal memory location. The WR and CS lines are used to start since the internal logic has already been reset. In the same
the conversion. The simplified logic (Figure 6 ) shows that way, data is transferred to the OUTPUT LATCH prior to is-
the falling edge of WR with CS low clocks the D-type flip- suing an interrupt. This assures that data can be read imme-
flop and initiates the conversion sequence. A new conver- diately after INT goes low.
sion can therefore be restarted before the end of the previ-
2.0 READING THE A/D
ous sequence. INT going low indicates the conversion’s
end. The ADC 1225 makes all thirteen bits of the conversion
result available in parallel. Taking CS and RD low enables
1.2 THE CONVERSION PROCESS (Numbers designated the TRI-STATEÉ output buffers. The conversion result is
by [ ] refer to portions of Figure 6 .) represented in 2’s complement format.
The SARS LOGIC [2] controls the A-to-D conversion pro- The ADC1205 makes the conversion result available in two
cess. When ‘sars’ goes high the clock (clk) is gated to the eight-bit bytes. The output format is 2’s complement with
TIMING GENERATOR [9]. One of the outputs of the TIM- extended sign. Data is right justified and presented high
ING GENERATOR, Tz, provides the clock for the Succes- byte first. With CS low and STATUS high, the high byte
sive Approximation Register, SAR LOGIC [5]. The Tz clock (DB12 – DB8) will be enabled on the output buffers the first
rate is (/8 of the CLK IN frequency. time RD goes low. When RD goes low a second time, the
Inputs to the 12-BIT DAC [11] and control of the SAMPLED low byte (DB7 – DB0) will be enabled. On each read opera-
DATA COMPARATOR [10] sign logic are provided by the tion, the ‘byst’ flip-flop is toggled so that on successive
SAR LOGIC. The first step in the conversion process is to reads alternate bytes will be available on the outputs. The
set the sign to positive (logic ‘0’) and the input of the DAC to ‘byst’ flip-flop is always reset to the high byte at the end of a
000 (HEX notation). If the differential input, VIN( a )bVIN(b), conversion. Table 1 below shows the data bit locations on
is positive the sign bit will remain low. If it is negative the the ADC1205.
sign bit will be set high. Differential inputs of only a few The ADC1205’s STATUS pin makes it possible to read the
hundred microvolts are enough to provide full logic swings conversion status and the state of the ‘byst’ flip-flop. With
at the output of the SAMPLED DATA COMPARATOR. RD, STATUS and CS low, this information appears on the
The sign bit indicates the polarity of the differential input. If it data bus. The ‘byst’ status appears on pin 18 (DB2/DB10).
is set high, the negative input must have been greater than A low output on pin 18 indicates that the next data read will
the positive input. By reversing the polarity of the differential be the high byte. A high output indicates that the next data
input, VIN( a ) and VIN(b) are interchanged and the DAC read will be the low byte. A high status bit on pin 22 (DB6/
sees the negative input as positive. The input polarity rever- DB12) indicates that the conversion is in progress. A high
sal is done digitally by changing the timing on the input sam- output appears on pin 17 (DB1/DB9) when the conversion
pling switches of the SAMPLED DATA COMPARATOR. is completed and the data has been transferred to the out-
Thus, with almost no additional circuitry, the A/D is extend- put latch. A high output on pin 16 (DB0/DB8) indicates that
ed from a unipolar 12-bit to a bipolar 12-bit (12-bit plus sign) the conversion has been completed and the data is ready to
device. read. This status bit is reset when a new conversion is initia-
After determining the input polarity, the conversion pro- ted, data is read, or status is read. When reading status or a
ceeds with the successive approximation process. The SAR conversion result, STATUS should always change states at
LOGIC successively tries each bit of the 12-BIT DAC. The least 600 ns before RD goes low. If the conversion status
most significant bit (MSB), B11, has a weight of (/2 of VREF. information is not needed, the STATUS pin should be hard-
The next bit, B10, has a weight of (/4 VREF. Each successive wired to V a . Table 2 summarizes the meanings of the four
bit is reduced in weight by a factor of 2 which gives the least status bits.
significant bit (LSB) a weight of 1/4096 VREF. TABLE I. Data Bit Locations, ADC1205
When the MSB is tried, the comparator compares the DAC HIGH BYTE DB12 DB12 DB12 DB12 DB11 DB10 DB9 DB8
output, VREF/2, to the analog input. If the analog input is
greater than VREF/2 the comparator tells the SAR LOGIC to LOW BYTE DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
set the MSB. If the analog input is less than VREF/2 the TABLE II. Status Bit Locations and Meanings
comparator tells the SAR LOGIC to reset the MSB. On the
next bit-test the DAC output will either be */4 VREF or (/4 Status
Status
Condition to
VREF depending on whether the MSB was set or not. Fol- Bit Meaning Clear Status
Bit
lowing this sequence through for each successive bit will Location Bit
approximate the analog input to within 1-bit (one part in DB6 SARS ‘‘High’’ indicates that
4096). the conversion is in
On completion of the LSB bit-test the conversion-complete progress
flip-flop (CC) is set, signifying that the conversion is finished. DB2 BYST ‘‘Low’’ indicates that Status write
The end-of-conversion (EOC) and interrupt (INT) lines are the next data read is or toggle it
not changed at this time. Some internal housekeeping tasks the high byte. with data
must be completed before the outside world is notified that ‘‘High’’ indicates that read
the conversion is finished. the next data read is
the low byte

9
Functional Description (Continued)
TABLE II. Status Bit Locations and Meanings
(Continued)
Status Status Condition to
Bit Bit Meaning Clear Status
Location Bit
DB1 EOC ‘‘High’’ indicates that
the conversion is
completed and data is
transferred to the
output latch.
DB0 INT ‘‘High’’ indicates that Data read or
it is the end of the status read
conversion and the or status
data is ready to read write

3.0 INTERFACE TL/H/5676 – 10

3.1 RESET OF INTERRUPT FIGURE 8. READY OUT Timing Diagram

INT goes low at the end of the conversion and indicates that 3.3 RESETTING THE A/D
data is transferred to the output latch. By reading data, INT All the internal logic can be reset, which will abort any con-
will be reset to high on the leading edge of the first read (RD version in process and reset the status bits. The reset func-
going low). INT is also reset on the leading (falling) edge of tion is achieved by performing a status write (CS, WR and
WR when starting a conversion. STATUS are low).
3.2 READY OUT 3.4 ADDITIONAL TIMING AND INTERFACE OPTIONS
To simplify the hardware connection to high speed micro- ADC1225
processors, a READY OUT line is provided. This allows the 1. WR and RD can be tied together with CS low continu-
A-to-D to insert a wait state in the mP’s read cycle. The ously or strobed. The previous conversion’s data will be
equivalent circuit and the timing diagram for READY OUT is available when the WR and RD are low as shown below.
shown in Figures 7 and 8 .
One drawback is that, since the conversion is started on the
falling edge and the data read on the rising edge of WR/RD,
the first data access will have erroneous information de-
pending on the power-up state of the internal output latch-
es.
If the WR/RD strobe is longer than the conversion time,
TL/H/5676–9
INTR will never go low to signal the end of a conversion.
FIGURE 7. READY OUT Equivalent Circuit The conversion will be completed and the output latches will
be updated. In this case the READY OUT signal can be
used to sense the end of the conversion since it will go low
when the output latches are being updated.

TL/H/5676 – 24
FIGURE 9

10
Functional Description (Continued)

TL/H/5676 – 25
FIGURE 10

TL/H/5676 – 26
FIGURE 11

TL/H/5676 – 27
FIGURE 12

11
Functional Description (Continued)

TL/H/5676 – 28

TL/H/5676 – 29
FIGURE 13

When using this method of conversion only one strobe is 3. Tying CS and RD low continuously and strobing WR to
necessary and the rising edge of WR/RD can be used to initiate a conversion will also yield valid data. The INTR will
read the current conversion results. These methods reduce never go low to signal the end of a conversion and the
the throughput time of the conversion since the RD and WR digital outputs will always be enabled, so using INTR to
cycles are combined. strobe the WR line for a continuous conversion cannot be
2. With the standard timing WR pulse width longer than the done with this part.
conversion time a conversion is completed but the INTR will A simple stand-alone circuit can be accomplished by driving
never go low to signal the end of a conversion. The output WR with the inverse of the READY OUT signal using a sim-
latches will be updated and valid information will be avail- ple inverter as shown below.
able when the RD cycle is accomplished.

FIGURE 14 TL/H/5676 – 30

12
Functional Description (Continued)
ADC1205 through the output resistance of the analog signal source.
Case 1 would be the only one that would appy to the This charge pumping action is worse for continuous conver-
ADC1205 since two RD strobes are necessary to retrieve sions with the VIN( a ) input voltage at full-scale. For continu-
the 13 bits of information on the 8 bit data bus. Simulta- ous conversions with a 1 MHz clock frequency and the
neously strobing WR and RD low will enable the most signif- VIN( a ) input at 5V, the average input current is approximate-
icant byte on DB0–DB7 and start a conversion. Pulsing ly 5 mA. For this reason bypass capacitors should not be
WR/RD low before the end of this conversion will enable used at the analog inputs for high resistance sources
the least significant byte of data on the outputs and restart a (RSOURCE 100 X).
conversion. If input bypass capacitors are necessary for noise filtering
and high source resistance is desirable to minimize capacitor
4.0 REFERENCE VOLTAGE
size, the detrimental effects of the voltage drop across this
The voltage applied to the reference input of the converter input resistance, due to the average value of the input cur-
defines the voltage span of the analog inputs (the difference rent, can be minimized with a full-scale adjustment while the
between VIN( a ) and VIN(b), over which 4096 positive out- given source resistance and input bypass capacitor are both
put codes and 4096 negative output codes exist. The in place. This is effective because the average value of the
A-to-D can be used in either ratiometric or absolute refer- input current is a linear function of the differential input volt-
ence applications. VREF must be connected to a voltage age.
source capable of driving the reference input resistance
(typically 4 kX). 5.4 INPUT SOURCE RESISTANCE
In a ratiometric system, the analog input voltage is propor- Large values of source resistance where an input bypass
tional to the voltage used for the A/D reference. When this capacitor is not used, will not cause errors as the input cur-
voltage is the system power supply, the VREF pin can be rents settle out prior to the comparison time. If a low pass
tied to VCC. This technique relaxes the stability requirement filter is required in the system, use a low valued series resis-
of the system reference as the analog input and A/D refer- tor (Rs100 X) for a passive RC section or add an op amp
ence move together maintaining the same output code for a RC active low pass filter. For low source resistance applica-
given input condition. tions, (RSOURCEs100 X) a 0.001 mF bypass capacitor at
the inputs will prevent pickup due to series lead inductance
For absolute accuracy, where the analog input varies be-
of a long wire. A 100 X series resistor can be used to isolate
tween very specific voltage limits, the reference pin can be
this capacitor – both the R and C are placed outside the
biased with a time and temperature stable voltage source.
feedback loop – from the output of an op amp, if used.
In general, the magnitude of the reference voltage will re-
quire an initial adjustment to null out full-scale errors. 5.5 NOISE
5.0 THE ANALOG INPUTS The leads to the analog inputs should be kept as short as
possible to minimize input noise coupling. Both noise and
5.1 DIFFERENTIAL VOLTAGE INPUTS AND COMMON undesired digital clock coupling to these inputs can cause
MODE REJECTION errors. Input filtering can be used to reduce the effects of
The differential inputs of the ADC1225 and ADC1205 actu- these sources, but careful note should be taken of sections
ally reduce the effects of common-mode input noise, i.e., 5.3 and 5.4 if this route is taken.
signals common to both VIN( a ) and VIN(b) inputs (60 Hz is
6.0 POWER SUPPLIES
most typical). The time interval between sampling the ‘‘ a ’’
and ‘‘b‘‘ input is 4 clock periods. Therefore, a change in the Noise spikes on the VCC supply line can cause conversion
common-mode voltage during this short time interval may errors as the comparator will respond to this noise. Low
cause conversion errors. For a sinusoidal common-mode inductance tantalum capacitors of 1 mF or greater are rec-
signal the error would be: ommended for supply bypassing. Separate bypass caps
should be placed close to the DVCC and AVCC pins. If an
4
VERROR(MAX) e VPEAK (2q fCM) unregulated voltage source is available in the system, a sep-
fCLK arate LM340LAZ-5.0 voltage regulator for the A-to-D’s VCC
where fCM is the frequency of the common-mode signal, (and other analog circuitry) will greatly reduce digital noise
VPEAK is its peak voltage value and fCLK is the converter’s on the supply line.
clock frequency. In most cases VERROR will not be signifi-
cant. For a 60 Hz common-mode signal to generate a (/4 7.0 ERRORS AND REFERENCE VOLTAGE
LSB error (300 mV) with the converter running at 1 MHz its ADJUSTMENTS
peak value would have to be 200mV. 7.1 ZERO ADJUST
5.2 INPUT CURRENT The zero error of the A/D converter relates to the location
Due to the sampling nature of the analog inputs, short dura- of the first riser of the transfer function and can be mea-
tion spikes of current enter the ‘‘ a ’’ input and exit the ‘‘b’’ sured by grounding the VIN(b) input and applying a small
input at the leading clock edges during the actual conver- magnitude positive voltage to the VIN( a ) input. Zero error is
sion. These currents decay rapidly and do not cause errors the difference between the actual DC input voltage neces-
as the internal comparator is strobed at the end of a clock sary to just cause an output digital code transition from all
period. zeroes to 0,0000,0000,0001 and the ideal (/2 LSB value ((/2
LSB e 0.61 mV for VREF e 5 VDC). Zero error can be adjust-
5.3 INPUT BYPASS CAPACITORS ed as shown in Figure 15 . VIN( a ) is forced to 0.61 mV, and
Bypass capacitors at the inputs will average the current VIN(b) is forced to 0V. The potentiometer is adjusted until
spikes mentioned in 5.2 and cause a DC current to flow the digital output code changes from all zeroes to
0,000,0000,0001.

13
Functional Description (Continued)
A simpler, although slightly less accurate, approach is to tude of the VREF input so that the output code is just chang-
ground VIN( a ) and VIN(b), and adjust for all zeros at the ing from 0,1111,1111,1110 to 0,1111,1111,1111.
output. Error will be well under (/2 LSB if the adjustment is
Bipolar Inputs
done so that the potentiometer is ‘‘centered’’ within the
0,000,000 range. A positive voltage at the VOS input will Do the same procedure outlined above for the unipolar case
reduce the output code. The adjustment range is a 4 to and then change the differential input voltage so that the
b 30 LSB. digital output code is just changing from 1,0000,0000,0001
to 1,0000,0000,0000. Record the differential input voltage,
VX. the ideal differential input voltage for that transition
should be;

# J
VF
b VF a
8192
Calculate the difference between Vx and the ideal voltage;

# J
VF
D e VX b bVF a
8192
Then apply a differential input voltage of;

#V J
TL/H/5676–11 D
FIGURE 15. Zero Adjust Circuit Xb
2
7.2 POSITIVE AND NEGATIVE FULL-SCALE and adjust the magnitude of VREF so the digital output
ADJUSTMENT code is just changing from 1,0000,0000,0001 to
1,0000,0000,0000. That will obtain the positive and negative
Unipolar Inputs
full-scale transition with symmetrical minimum error.
Apply a differential input voltage which is 1.5 LSB below the
desired analog full-scale voltage (VF) and adjust the magni-

Typical Applications

*Input must have some

current return path to
signal ground

TL/H/5676 – 12

14
Typical Applications (Continued)
Protecting the Input

Diodes are 1N914 TL/H/5676 – 16

Operating with Ratiometric Transducers

*VIN( b ) e 0.15 VCC

15% of VCC s VXDR s 85% of VCC

TL/H/5676 – 17

15
Typical Applications (Continued)
Bipolar Input Temperature Converter

TL/H/5676 – 18
a 150 to b 55§ C with 0.04§ C resolution
Note: * resistors are 1% metal film types

Strain Gauge Converter with .025% Resolution and Single Power Supply

TL/H/5676 – 19
Note: 1)* resistors are 1% metal film types
2) LF412 power a 10V and ground

16
Ordering Information
Temperature Range 0§ C to 70§ C b 40§ C to a 85§ C

Non-Linearity 0.024% ADC1205CCJ-1 ADC1225CCD-1 ADC1205CCJ ADC1225CCD

Package Outline J24A D28D J24A D28D

Physical Dimensions inches (millimeters)

Ceramic Dual-In Line Package (J)

Order Number ADC1205CCJ-1 or ADC1205CCJ
NS Package Number J24A

17
ADC1205/ADC1225 12-Bit Plus Sign mP Compatible A/D Converters
Physical Dimensions inches (millimeters) (Continued)

Ceramic Dual-In-Line Package (D)

Order Number ADC1225CCD-1 or ADC1225CCD
NS Package Number D28D

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