4 .

1 ARITHMETIC BLOCKS
Jean-Pierre Deschamps
University Rovira i Virgili, Tarragona, Spain

1
 4 .1
Arithmetic blocks constitute an important part of practically any digital circuit. They
deserve a particular treatment.

Four operations:

1. Addition
2. Subtraction
3. Multiplication
4. Division

2
1. Binary adder
4 .1
Algorithm - n-bit binary adder, s = x + y + carry
cy(0) <= carry;
See lessons 2.2 and 2.3.
for i in 0 to n-1 loop
s(i) <= x(i) xor y(i) xor cy(i);
Each FA (full adder = 1-bit adder)
cy(i+1) <= (x(i) and y(i)) or (x(i) and cy(i))
block implements two Boolean
or (y(i) and cy(i));
equations:
end loop;
s(n) <= cy(n);
 s(i) <= x(i) xor y(i) xor cy(i);
 cy(i+1) <=
(x(i) and y(i)) or (x(i) and cy(i)) S = sn2n + sn-12n-1 + sn-22n-2 + ··· + s12 + s0.
or (y(i) and cy(i));
xn-1 yn-1 x1 y1 x0 y0

cyn-1 cy2 cy1 cy0 = carry

sn =cyn FA .... FA FA

3
sn-1 s1 s0
2. Binary subtractor
4 .1
A binary subtractor computes
Representation of D?
D = X - Y - borrow,
D can be represented as a 2'complement (n+1)-bit
X and Y: n-bit numbers,
number:
borrow: initial carry borrow.
Maximum value of D: 2n-1 D = -dn2n + dn-12n-1 + dn-22n-2 + ··· + d12 + d0.
(X = 2n-1, Y = borrow = 0).
Minimum value of D:-2n
(X = 0, Y = 2n-1, borrow = 1).

4
2. Binary subtractor
4 .1
“Pencil and paper" algorithm: Examples:

n steps; 1100 1001

1001 1100
at each step compute: -------- --------
 a difference bit 0011 11101

d = (x - y - bIN) mod 2;
Algorithm - n-bit binary subtractor, s = x - y - borrow
 an outgoing borrow bit b(0) <= borrow;
for i in 0 to n-1 loop
bOUT = 1 iff x - y - bIN < 0. d(i) <= (x(i) + y(i) + b(i)) mod 2;
b(i+1) <= sign(x(i) - y(i) - b(i));
end loop;
Comment:
s(n) <= b(n);
(x - y - bIN) mod 2 = (x + y + bIN) mod 2 5
2. Binary subtractor
4 .1
Algorithm - n-bit binary subtractor, s = x - y - borrow
b(0) <= borrow;
for i in 0 to n-1 loop
d(i) <= (x(i) + y(i) + b(i)) mod 2;
b(i+1) <= sign(x(i) - y(i) - b(i));
end loop; Algorithm - n-bit binary subtractor, s = x - y - borrow
s(n) <= b(n); b(0) <= borrow;
for i in 0 to n-1 loop
d(i) <= x(i) xor y(i) xor b(i);
b(i+1) <=
(not(x(i)) and y(i)) or (not(x(i)) and b(i))
Iteration body in terms of or (y(i) and b(i));
Boolean operations => end loop;
s(n) <= b(n);

6
2. Binary subtractor
4 .1
Complete circuit.

Each FS (full subtractor) block

implements two Boolean equations:

 d(i) <= x(i) xor y(i) xor b(i);

 b(i+1) <=
(not(x(i)) and y(i)) or (not(x(i)) and b(i))
or (y(i) and b(i));
xn-1 yn-1 x1 y1 x0 y0

b n-1 b2 b1 b0 = borrow
dn =bn FS .... FS FS

7
dn-1 d1 d0
 4 .1
(Exercise)
Define a circuit that generate the difference D = x - y under the form (sign and
magnitude) D = (-1)sign·|D|.

Hint: compute in parallel x – y and y – x and select |D| in function of the sign of x – y.

8
 4 .1
(Solution)
Define a circuit that generate the difference D = x - y under the form (sign and
magnitude) D = (-1)sign·|D|.

Hint: compute in parallel x – y and y – x and select |D| in function of the sign of x – y.

x y y x

subtract. 0 subtract. 0
d’ d’’

0 1

sign d 9
3. Binary multiplier
4 .1
A binary multiplier computes If Y = ym-1·2m-1 + ym-2·2m-2 + ··· + y1·2 + y0 then

P = X · Y, P = X·ym-1·2m-1 + X·ym-2·2m-2 + ··· + X·y1·2 + X·y0

X: n-bit number,
Algorithm:
Y: m-bit numbers. p0 = X·y0;
Maximum value of P: p1 = X·y1·2;
p2 = X·y2·22;
(2n-1) · (2m-1) =
···
2n+m - 2m - 2n + 1 < 2n+m pm-1 = X·ym-1·2m-1;
=> P: (n+m)-bit number.
P = p0 + p1 + p2 + ··· + pm-1 .

10
3. Binary multiplier
4 .1
p0 = X·y0;
p1 = X·y1·2;
p2 = X·y2·22;
Example:
···
pm-1 = X·ym-1·2m-1;
101101
x 1011
P = p0 + p1 + p2 + ··· + pm-1 .
---------
101101  p0
101101  p1
000000  p2
101101  p3
------------------
111101111  P

11
3. Binary multiplier
4 .1
0 X
acc_in X
p0 = X·y0; acc_in X
y
p1 = X·y1·2; y y(0)
acc_out
p2 = X·y2·22;
X·2
···
adder
pm-1 = X·ym-1·2m-1; acc_in X
y y(1)
acc_out acc_out
P = p0 + p1 + p2 + ··· + pm-1 .
X·22

acc_in X
Algorithm - Multiplication, y y(2)
right to left algorithm acc_out

acc <= 0; ····

for i in 0 to m-1 loop X·2m-1

acc <= acc + X*(2**i)*y(i);

acc_in X
end loop; y y(m-1)
P <= acc; acc_out

12
P
4. Binary divider
4 .1

A binary divider computes Q and R such that

X = Q·Y + R,
X, Y: naturals, with X < Y, In other words:
Q: multiple of 2-p ,
X/Y = Q + (R/Y) where Q is a multiple of 2-p and
R < Y·2-p. error = (X/Y) - Q = (R/Y) < 2-p.

A previous operand alignment may be

necessary in order that X < Y.

13
4. Binary divider
4 .1
Algorithm - Binary division Example: X = 21, Y = 35, p = 6
r(0) <= x;
for i in 1 to p loop 2·21 = 1·35 + 7
d <= 2*r(i-1) - y; 2·7 = 0·35 + 14
if d < 0 then q(i) <= 0; r(i) <= 2*r(i-1); 2·14 = 0·35 + 28
else q(i) <= 1; r(i) <= d; 2·28 = 1·35 + 21
end if; 2·21 = 1·35 + 7
end loop; 2·7 = 0·35 + 14

Result: => Q = [100110]2/64 = 38/64 = [0.100110]2,

Q = (q1 q2 ··· qp-1 qp)·2-p, R = 14/64 = [0.001110]2

R = rp·2-p. Check that Q·Y + R = X, R < Y·2-p:
(38/64)·35 + (14/64) = 21, 14/64 < 35/64.

14
4. Binary divider X Y
4 .1
r Y
0
r Y
Algorithm - Binary division q1 q sign
r+ q subtractor
r(0) <= x;
2·r
for i in 1 to p loop
d <= 2*r(i-1) - y; r Y 1 0
if d < 0 then q(i) <= 0; r(i) <= 2*r(i-1); q2 q
r+
else q(i) <= 1; r(i) <= d;
r+
end if;
end loop; r Y
q3 q
r+

····

r Y
qp q
r+

rp 15
 4 .1
SUMMARY

 Circuits to execute the basic arithmetic operations (addition, subtraction,

multiplication and division, natural operands) have been described.
 Some information about 2’s complement representation have been given.

16
4.2 Introduction to VHDL: Lexicon, syntax
and structure
Juan Antonio Martinez1, Lluís Terés1,2
1Universitat Autònoma de Barcelona (UAB)
2Instituto de Microelectrónica de Barcelona, IMB-CNM (CSIC)
HDLs: what are and what are they used for? 4 .2
What HDLs are?
• High level abstraction languages oriented to describe/model Hardware
• Write formal, non ambiguous models instead of using natural language or drawings
• Understandable by computers and humans
• Like programming languages but to model Hw instead of developing Sw

What HDLs are used for?

• First of all to model hardware independently of its technological implementation
• To simulate HDL models against specifications
• To synthesize HDL models into different implementation technologies

Which are the main HDLs?

• VHDL: VHSIC Hardware Description Language (Std. IEEE 1076 since 1987)
• Verilog: Cadence simulation language (1985) moved to public HDL (Std. IEEE 1364 since 1995)
• C/C++/SystemC/SystemVerilog: higher abstraction languages used to specify Hw/Sw systems at
functional level
 HDLs: what are and what are they used for? 4 .2
Abstraction Software development Hardware description
level languages languages
compilation + simulation
void Error(int Codigo) { if (reset = ‘1’) then
Hardware / Technology switch (Codigo) { q <= ‘0’;
case 1: printf(“ ….. elsif (clk’event and clk=‘1’) then
independent ... q <= d; Pre-synthesis
Programs/Models } High level end if; High level language
} language program hardware model Simulation
Results
compilation

synthesis

compilation synthesis validation

str r1, 1Ah d q

lea dx, cadena Post-synthesis
Hardware / Technology mov ah, 0ah clk Simulation
dependent int 21h reset Physical Results
… Machine implementation
Programs/Models ... code description/model
jmp end (specific P) (specific technology) compilation + simulation
19
CONTENTS 4 .2
1. Basics on VHDL lexical & syntax
2. VHDL Design Units
3. VHDL Sequential Sentences (selection)
4. VHDL Concurrent Sentences (selection)
5. VHDL based design flow: modelling - simulation - synthesis
6. Summary

20
1. Basic on VHDL Lexical & Syntax 4 .2
Lexical elements: Reserved Words, Identifiers, Symbols and Literals
Language Reserved Words
abs access after alias all and architecture
array assert attribute begin block body buffer
bus case component else elsif end entity
exit file for function generate generic guarded
if in inout is label library nand
new next nor not null of on
open or others out process procedure ...
Identifiers to provide specific names to VHDL elements and objects
- Based on character set {„a‟…‟z‟, ‟A‟…‟Z‟, ‟0‟…‟9‟, ‟_‟}
- First character shall be alphabetical and „_‟ at the end or two „__‟ are forbidden
- Upper/lower-case are indifferent and reserved words are forbidden
Examples: COUNT, aBc, X, f123, VHDL, VH_DL, ABC, q1, Q0

Symbols Literals
- 1 or 2 characters Base Character Physical
- operators, punctuation, comments, part of 2#110_1010# „a‟ „A‟ „@‟ 10 ns
sentences: + - * / ( ) . , : & 16#CA# String 2.2 V
„ < > = | # ; -- => ** := 16#f.ff#e+2 “Tiempo” 50 pF
Decimal “110101” Bit String
/= >= <= <> “
12 0 1E Bit:‟0‟,‟1‟ X”F0f” B”111_100”
1.1. VHDL Objects 4 .2
• VHDL object is any language element able to contain a value
• Types of VHDL objects:
 Constant
 Variable Object definition:
<Object type> <identifier> : <data type> [:= Initial value];
 Signal
 File
constant PI : real := 3.1415927; variable Counter : integer :=0; Variables
constant WordBits : natural := 8; variable Increment : integer;
declaration
constant NumWords : natural := 1024;
constant TotBits : natural := WordBits * NumWords; Increment := 2; Variables
Counter := Counter + Increment; assignment
Signal declaration
signal Clk : bit := „0‟;
... & initialization
Clk <= „1‟; Signal assignment

file Estimuli : FileTypeName1 open read_mode is “data.in”;

file Dataout : FileTypeName2 open write_mode is “data.out”;
1.2. Data Types 4 .2
• The VHDL is a strongly typed language
• A data type defines a set of fixed and static values
• Any language object belongs to a specific data type
• Object values shall belong to related data type
• New user defined data types available
Package standard is STANDARD package: Predefined Types of VHDL
type boolean is (false, true);
type bit is („0‟, „1‟);
type character is (NUL, SOH, STX,…, „ „, „!‟, „”‟, „#‟, „$‟,… „0‟, „1‟, „2‟, „3‟, „4‟, „5‟,
„6‟, „7‟, „8‟, „9‟,…,„A‟, „B‟, „C‟, „D‟, „E‟, „F‟ ,…, „a‟, „b‟, „c‟, „d‟, …);
type severity_level is (note, warning, error, failure);
type integer is range -2.147.483.647 to 2.147.483.647; -- implementation dependent
type real is range -1.0e38 to 1.0e38 ; -- implementation dependent
…/…
function NOW return TIME;
subtype natural is integer range 0 to integer'high;
subtype positive is integer range 1 to integer'high;
type string is array (positive range <>) of character;
type bit_vector is array (natural range <>) of bit
…/…
End standard;
1.2. Data Types 4 .2
• The VHDL is a strongly typed language
• A data type defines a set of fixed and static values
• Any language object belongs to a specific data type
• Object values shall belong to related data type
• New user defined data types available

Also in STANDARD package…

-- implementation dependent
type time is range 0 to 1e20
units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units time;
24
1.3. Operators and Expressions 4 .2
• Operators are symbols identifying specific operations
• Types: relational , logic, arithmetic and concatenation
• Operators: • Expressions:
Relational Logic Arithmetic Arithmetic
(-b + sqrt(b**2 - 4.0*a*c))/(2.0*a)
= and +
/= or - Relational Logic
< nand * delay >= 20 ns (a xor b) and not c;
name < “Smith”
<= nor /
> xor **
Concatenation
>= not mod BitSign & VectorValue
rem
Concatenation abs • Expressions used as conditions or assigned to:
 Constants (const := expression;)
&  Variables (var := expression;) 25
 Signals (sig <= expression;)
2. Design Units 4 .2
VHDL is organized on different “Design Units”:
• Entity
• Architecture
• Package (declaration & body)
• Configuration

Primary
Entity Configuration Package
Declaration Declaration Declaration

Architecture 1 Package

Secondary
Body
Architecture 2

Architecture n
26
2.1. ENTITY 4 .2
• Like a “black-box” just describing external interface for a module while
hiding its internal behaviour or functionality
• Syntax:
Entity name (module name)
entity <id> is Generic parameters
[<generics>];
[<ports>]; Input/Output ports (electrical interface)
[<declarations>];
[begin <sentences>];
Global declarations (common to any potential architecture of this entity)
end [entity] [<id>];
Passive sentences (common to any potential architecture of this entity)

entity MUX21 is
port( A : in bit; A
B : in bit;
Ctrl : in bit; B MUX21 Z
Z : out bit;
end MUX21;
Ctrl
27
2.1. ENTITY 4 .2
• Like a “black-box” just describing external interface for a module while
hiding its internal behaviour and architecture
• Syntax:
Entity name (module name)
entity <id> is Generic parameters
[<generics>];
[<ports>]; Input/Output ports (electrical interface)
[<declarations>];
[begin <sentences>];
Global declarations (common to any potential architecture of this entity)
end [entity] [<id>];
Passive sentences (common to any potential architecture of this entity)

entity MUX21n is Bus size as generic parameter

generic( n : integer := 2);
n
port( A : in bit_vector(n-1 downto 0);
B : in bit_vector(n-1 downto 0);
A
n n
Ctrl : in bit; B MUX21 Z
Z : out bit_vector(n-1 downto 0));
end MUX21; Ctrl 28
2.2. ARCHITECTURE 4 .2
• Details what is behind an “Entity” while describing its behaviour at functional,
data-flow, structural or mixed levels
• Multiple Architectures for a single Entity are possible
• Syntax:
Architecture name
Entity name
architecture <id> of <id_entity> is
[<declarations>]; Data types, constants, signals, variables,
begin components declarations specific for this
<concurrent sentences>; architecture
end [architecture] [<id>];

Concurrent sentences:
• Concurrent assignments
• Instances to components
• Processes
• Blocks
29
2.2.1 Entities & Architectures 4 .2
entity MUX21 is entity MUX21n is
port( A, B, Ctrl : in bit; generic ( n: natural);
Z : out bit); port( A : in bit_vector(n-1 downto 0);
end MUX21; B : in bit_vector(n-1 downto 0);
Ctrl : in bit;
Z : out bit_vector(n-1 downto 0));
architecture Functional of MUX21 is
end MUX21;
begin
process(A, B, Ctrl)
begin architecture Functional of MUX21n is
if Ctrl = „0‟ then begin
Z <= A; process(A, B, Ctrl)
else begin
Z <= B; if Ctrl = „0‟ then
end if; Z <= A;
end process; else
Z <= B;
end Functional; n
end if;
end process; A
A end Functional; B
n
MUX21n
n
Z
B MUX21
Z Ctrl
Ctrl
2.2.1 Entities & Architectures 4 .2
entity MUX21 is
port( A : in bit;
B : in bit;
architecture structural of MUX21 is Ctrl : in bit;
signal Ctrl_n, As, Bs : bit; Z : out bit;
component INV end MUX21;
port( Y : in bit;
Z : out bit);
end component;
component AND2
port( X, Y : in bit;
Z : out bit);
end component;
component OR2
port( X, Y : in bit;
Z : out bit); architecture DataFlow of MUX21 is
As Bs
end component; signal Ctrl_n, N1, N2 : bit;
begin begin
U0: INV port map (Ctrl, Ctrl_n); Ctrl_n <= Ctrl_n
N1 not Ctrl;
and a;
U1: AND2 port map (Ctrl_n, A, As); N1
Z <= (N1
Ctrl_n
or N2);
and a;
U2: AND2 port map (Ctrl, B, Bs); N2 <= Ctrl and b;
U3: OR2 port map (As, Bs, Z); Z
Ctrl_n <= (N1
not Ctrl;
or N2);
end structural; end DataFlow;
Sentencias Concurrentes
2.3. PACKAGE 4 .2
• Useful for code reuse as it could contain definitions of data types, functions and
language objects (constants, variables, signals or files) for its use on different codes
• Two units: Package name
 “Package declaration” package <identifier> Declarations of:
[<declarations>]; • Data types
end [package] [<identifier>] • VHDL objects
• Functions & procedures
Package name
 “Package body” package body <identifier> Assignments & definitions of:
[<Assignments and • Constants
Detailed definitions>];
• Functions & procedures
end [package body] [<identifier>]
• Any other hidden information
Usual packages:
• Package usage - STANDARD & TEXTIO
- Std_logic_1164
use <library>.<package name>.[<identifier> | all]; - Std_logic_arith
- Used defined
 2.3. PACKAGE 4 .2
Example of user defined package
library IEEE; Comment
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package main_parameters is
constant m: natural := 8; -- m-bit processor
-- Value „0‟ in m-bits
constant zero: std_logic_vector(m-1 downto 0):= conv_std_logic_vector(0, m);
-- Value „1‟ in m-bits
constant one: std_logic_vector(m-1 downto 0) := conv_std_logic_vector(1, m);
-- Instruction codes for our simple processor instruction set
constant ASSIGN_VALUE: std_logic_vector(3 downto 0) := "0000";
constant DATA_INPUT: std_logic_vector(3 downto 0) := "0010";
constant DATA_OUTPUT: std_logic_vector(3 downto 0) := "1010";
constant OUTPUT_VALUE: std_logic_vector(3 downto 0) := "1000";
constant OPERATION_ADD: std_logic_vector(3 downto 0) := "0100";
constant OPERATION_SUB: std_logic_vector(3 downto 0) := "0101";
constant JUMP: std_logic_vector(3 downto 0) := "1110";
constant JUMP_POS: std_logic_vector(3 downto 0) := "1100";
constant JUMP_NEG: std_logic_vector(3 downto 0) := "1101";
end main_parameters;
Constant Constant
VHDL constant object Constant Id. 33
data type value
2.3. PACKAGE 4 .2
IEEE standard packages

• IEEE standard 1164 (std_logic_1164) Character Value

 Multivalued logic (std_logic): (‘U’, ’X’, ‘0’, ’1’, ’Z’, ’W’, ’L’, ’H’, ’-’); 'U' uninitialized
 Subtypes: (‘X’, ’0’, ’1’), (‘X’, ’0’, ’1’, ’Z’), ... 'X' strong drive, unknown logic value
'0' strong drive, logic zero
 Basic arithmetic and logic operations with above data types
'1' strong drive, logic one
 Data types conversion functions
'Z' high impedance (disconnected)
• Arithmetic (std_logic_arith) 'W' weak drive, unknown logic value

 More complex arithmetic operations & functions with “std_logic” 'L' weak drive, logic zero
data types 'H' weak drive, logic one
'-' don't care
 Data type conversion functions (i.e integer <=> std_logic)

• Others: std_logic_unsigned, std_logic_signed, …

• Modelling, simulation and synthesis tools made an optimized usage of those standard
35
packages  Standard packages are strongly recommended.
SUMMARY 4 .2
• Concept and general goals of HDLs: “Hw modelling– simulation – synthesis”
• Basics on VHDL lexical and syntax
 Language lexical elements
 Objects (constant, variable, signal and [files])
 Data types, Operators and expressions

• VHDL design units

 Entity and Architecture
 [Configuration]
 Package (declaration & body)

• Examples of simplified formal VHDL design units descriptions have been used

36
4.3 Introduction to VHDL: sequential
sentences
Juan Antonio Martinez1, Lluís Terés1,2
1Universitat Autònoma de Barcelona (UAB)
2Instituto de Microelectrónica de Barcelona, IMB-CNM (CSIC)
Preliminary: Sequential vs. Concurrent VHDL worlds 4 .3
Sequential vs. Concurrent Sentences
• Sequential
 Algorithmic sentences like for SW languages (if, case, loop, exit, return, …)
 Interpreted sequentially  Order of sentences is important for the results
 Only used in functions, procedures and Processes
• Concurrent
 Devoted to express hardware structure (Hw components and blocks are doing concurrently) and
processes working simultaneously along the time
 Some sequential sentences have its equivalent concurrent ones
 Selected sentences: Process, Signal assignments, Components instantiation
 Mainly used in Architectures
• Concurrent to Sequential for simulation
 Each concurrent statement could be translated to its equivalent Process based on sequential
statements.
 For simulation purposes all the concurrent statements are translated to its equivalent processes.
 VHDL event driven simulation will manage just a lot of processes.
38
Preliminary: Sequential vs. Concurrent VHDL worlds 4 .3
General structure of a VHDL model

entity X is
begin
…
end X;
…
S <= A when Sel=„0‟ else B;
Clock <= not clock after 20 ns;
architecture Y of X is …
…
begin P1: process (clock, S);
… begin
…
only concurrent sentences only sequential sentences
end process;
end Y;
P2: process …

39
1. Sequential Sentences (selection) 4 .3
• Where are possible?

process procedure P() is function F() return

begin begin begin
-- sequential -- sequential -- sequential
-- sentences -- sentences -- sentences
end process; end P; end F;

• Which are the selected sentences?

• Variable & Signal assignments
• Wait
• If … then … else … endif
• Case
• Loop, Exit and Next
• Functions & Procedures
• Assert…report…severity
40
1.1. Variable Assignment 4 .3
• Immediate replacement of variable value.
• Syntax:
[label:] <variable name> := <expression>;

• Examples:

Var := „0‟;
Vector := “00011100”;
string := “Message is: ”;
A := B + C;
B := my_function(3,databus)
C := my_function(4,adrbus) + A;

41
1.2. Signal Assignment 4 .3
• Projects a new event (time, value) on the signal driver.
“Event”: “time-value” pair – the signal takes value vi at time ti. t t0 t1 … ti
“Signal Driver”: sequence of time ordered events of a signal. v v0 v1 … vi
• Syntax:
[label:] <signal_name> <= [delay_type] <expression> {after <delay>};

• Delay types: “inertial” or “ transport”

• Examples: driver t 0 10 15 20 28 40 50
A <= „0‟, „1‟ after 10 ns, „0‟ after 15 ns, „1‟ after 20 ns, A v 0 1 0 1 0 1 0
„0‟ after 28 ns, „1‟ after 40 ns, „0‟ after 50 ns;

B1 <= transport A after 10 ns; B1

B2 <= A after 10 ns;
B2
B3 <= reject 5 ns A after 10 ns;
B3
A
(ns)
0 10 20 30 40 50 60 70
1.3. Wait 4 .3
• Indicates the point where a process execution shall be suspended, as well as the conditions
for its further reactivation. More than just one “wait” sentence per process is possible.
• Syntax:
[label:] wait [on <signal> {, ...}]
[until <boolean_expresion>]
[for <time_expresion>];
process
begin
Clock <= not Clock;
• Basic examples: wait for 10 ns;
process process end process;
begin begin
<sequential sentences> c <= a and b; Suspends and fixes a time for reactivation 10ns
wait; wait on a, b;
end process; end process; process
begin clk
Without reactivation condition Sensible to events on signals “a” “b” q <= d;
wait until Clock = „1‟;
end process;

Sensible to events on signals & condition=True

REMARK about VHDL simulation 4 .4
VHDL Event Driven Simulation Cycle
Updating
Signals & Time
Which processes Processes
shall be resumed? Execution

?
y/n y/n
y/n y/n Initialize Signals
DT
Signals Initialization
Drivers
Process-1

Process-2

Process-n
Update signals ...
drivers

d delay
STOP
Wait till all resumed
processes are stopped
0 1 3 4 5 Time
1.4. If … then … else … endif; 4 .3
• Selects the group of sentences to execute depending on a Boolean condition.
• Syntax:
[label:] if <condicion> then
<sentencias secuenciales> FlipFlop: process
{elsif <condicion> then begin clk
<sentencias secuenciales} if rst = „1‟ then
[else Q <= „0‟;
<sentencias secuenciales>] elsif (clk‟even and clk=„1‟) then
end if [label]; Q <= D;
end if; end if;
wait on rst, clk;
• Examples: end process; Flip-flop
process
Process (A, B, Ctrl) begin
Begin if Enable =„1‟ then
if Ctrl = „0‟ then Salida <= Entrada; Latch: process begin
Q <= A; else if load =„1‟ then
else Salida <= „Z‟; Q <= D;
Q <= B; end if; end if;
end if; wait on Enable, Entrada; wait on load, D;
end process; end process; end process;
Mux Buffer Triestate Latch
1.5. Case 4 .3
• Selects the group of sentences to execute
depending on a expression value. [label:] case <expresion> is
{when <value> =>
• Syntax: <sequential sentences>;}
 Or of values: when “00” | “01” => ... [when others =>
<sequential sentences>;]
 Values range: when 5 to 12 (integers) => ... end case [label];
 Last option: when others => ...
• Examples: type weekdays : (Monday, Tuesday, Wednesday, Thursday, Friday, Saturday, Sunday);
type typeofday : (Workingday, Holiday);
Signal Day : Weekdays; process
process Signal Daytype : typeofday;
begin begin
case Day is case ValEnt is
when Monday to Friday => when 0 => Res := 5;
Daytype <= Workingday; when 1 | 2 | 8 => Res := ValEnt;
when Saturday | Saunday => when 3 to 7 => Res := ValEnt + 5;
Daytype <= Holiday; when others => Res := 0;
end case; end case;
wait on Day; wait on ValEnt;
end process; end process;
1.6. If & Case entity LatMux is
port(
4 .3
Load : in bit;
• Example: model the behaviour of next block A, B, C, D : in bit;
Ctrl : in bit_vector(0 to 1);
with two “Process”: Y : out bit);
 Mux end LatMux;

 Latch architecture TwoProc of LatMux is

Signal X : bit;
LatMux Concurrent Statements
begin
Mux: process (Ctrl, A, B, C, D);
A begin
case Ctrl is
X when “00” => X <= A;
B when “01” => X <= B;
Y
when “10” => X <= C;
C when “11” => X <= D;
end case;
D end process;
Sequential Statements
Ctrl Latch: process (Load, X);
begin
if Load=„0‟ then
Load Y <= X;
end if;
end process;
end TwoProc; 47
Exercise 4 .3
• For the same module “LatMux”, could you entity LatMux is
port(
describe a new architecture using just one Load : in bit;
process? A, B, C, D : in bit;
Ctrl : in bit_vector(0 to 1);
Y : out bit);
LatMux end LatMux;

A architecture OneProc of LatMux is

Begin
B
C
? Y UnicP: process (Load, Ctrl, A, B, C, D);
begin
if Load=„0‟ then
case Ctrl is
D when “00” => Y <= A;

Ctrl ?
when “01” => Y <= B;
when “10” => Y <= C;
when “11” => Y <= D;
Load end case;
end if;
end process UnicP;

end OneProc; 48
Exercise (solution) 4 .3
• For the same module “LatMux”, could you entity LatMux is
port(
describe a new architecture using just one Load : in bit;
process? A, B, C, D : in bit;
Ctrl : in bit_vector(0 to 1);
Y : out bit);
LatMux end LatMux;

A architecture OneProc of LatMux is

Begin
B UnicP: process (Load, Ctrl, A, B, C, D);
Y
begin
C if Load=„0‟ then
case Ctrl is
D when “00” => Y <= A;
when “01” => Y <= B;
Ctrl when “10” => Y <= C;
when “11” => Y <= D;
Load end case;
end if;
end process UnicP;

end OneProc; 49
 1.7. Loop 4 .3
• Sequential sentences in the loop region are repeated for a number of times.
• Types of loops: “while”, “for” and “without iterations control (infinite loop)”.
• Syntax: [label:] [while <boolean_condition> | for <repetition_control>]
loop
<sequential sentences>}
end loop [label]; achitecture Functional of ParallelAdder is
begin
process (X, Y, Cin);
• Examples: “Full-adder” variable C : std_logic_vector(n downto 0);
entity ParallelAdder is variable tmp : std_logic;
generic (n : natural :=4 ); variable I : integer;
port ( X, Y : in begin
std_logic_vector(n-1 downto 0); C(0) := Cin;
Cin : in std_logic; for I in 0 to n-1 loop
Z : out std_logic_vector(n-1 downto 0); tmp := X(I) xor Y(I);
Cout : out std_logic); Z(I) <= tmp xor C(I);
End ParallelAdder ; C(I+1) := (tmp and C(I)) or (X(I) and Y(I));
end loop;
Cout <= C(n);
• Exit & Next sentences: conditional loop end process;
end Functional;
breakings
1.8. Function 4 .3
• A piece of code devoted to specific computation of input parameters to return a value.
• Syntax for function declaration:
function <name> [(<parameters list>)] return <data_type>;

• Syntax for function definition:

function <name> [(<parameters list>)] return <data_type> is
{<declarative part>}
begin
{<sequential sentences>} [label:] return [expresion];
end [function] [<name>];

• Example:
function bv2int (bs: bit_vector(7 downto 0)) return integer; Function declaration

Var := base + bv2int(adrBus(15 downto 8));

Function usage
Sig <= base + bv2int(adrBus(7 downto 0)); or reference
51
1.9. Procedure 4 .3
• A piece of code devoted to specific computation of input parameters to return values on
its output parameters.
• Syntax for procedure declaration: procedure <name> [(<parameters list>)];

• Syntax for procedure definition:

procedure <name> [(<parameters list>)] is
{<declarative part>}
begin
{<sequential sentences>}
end [function] [<name>];

• Example:
procedure bv2int (bs: bit_vector(7 downto 0); x: out integer ); Procedure
declration

bv2int(adrBus(15 downto 8); Var); Procedure usage

Var := base + Var; or reference 52
1.10. Assert 4 .3
• A kind of validation sentence: when <boolean expression> is FALSE the <string of characters>
is printed out and actions related to specified severity level are done.
• Syntax: [label:] assert <boolean expression>
[report <string of characters>]
[severity (note | warning | error |failure);

• Examples:
assert not(addr < X"00001000" or addr > X"0000FFFF“)
report “Address in range" severity note;

assert (J /= C) report "J = C" severity note;

Sequential Sentences: Report

• Syntax: [label:] [report < string of characters >]
[severity (note | warning | error |failure);

• Example:
report “Check point 13”;
= assert FALSE “Check point 13” severity note;
RESUMEN 4 .3
• Sequential vs. Concurrent worlds in VHDL
• VHDL sequential sentences (inside a process, function or procedure)
 Selected sentences:
• Variable & signal assignments • If … then … else … endif • Loop, Exit and Next
• Wait • Case • Assert, Functions & Procedures

 Time management and event driven simulation of concurrent processes

 Examples based VHDL learning

54
4.4 Introduction to VHDL: Concurrent
sentences
Juan Antonio Martinez1, Lluís Terés1,2
1Universitat Autònoma de Barcelona (UAB)
2Instituto de Microelectrónica de Barcelona, IMB-CNM (CSIC)
Previous comment 4 .4
General structure of a VHDL model

entity X is
begin
…
end X;
…
S <= A when Sel=„0‟ else B;
Clock <= not clock after 20 ns;
architecture Y of X is …
…
begin P1: process (clock, S);
… begin
…
only concurrent sentences only sequential sentences
… …
end process;
end Y;
P2: process …

56
1. Concurrent sentences (selection) 4 .4
• All the concurrent sentences are being evaluated simultaneously

• Where are possible?

entity X is Concurrent sentences
• Entity (passive sentences) begin
• Block (collects concurrent sentences)
• Architecture
end X;

• Which are the selected sentences?

B : block
• Process architecture Y of X is begin
• Signal assignments begin
• Direct Assignment
end block;
• Conditional Assignment end Y;
• Selected Assignment
• Components
• Generate
• Each concurrent sentence will be translated to its equivalent process before its simulation.
57
Thus, any simulation manages a set of concurrent processes.
1.1. Process 4 .4
• Contains sequential sentences to define its own behaviour
• Communicates with other processes and concurrent sentences by means of signals
• Each process is sensible to events on specific signals or conditions to launch again its execution
• The sensitivity list identifies the signals to which this process is sensitive (“stop/wait” condition)
• The process is an infinite execution loop able to contain “stop/wait” conditions (at least ONE!!)
• Processes could contain local declarations which are only visible inside each related process
• Syntax: [<label>:] process [(<signal> ,{<signal>, ...})] [is]
<local declarations>
begin Signals which events
<sequential sentences> sensitivity signals list activates the process
end process [<label>]; execution

process
process (<sensitivity signals list>) begin
begin <sequential sentences>
<sequential sentences> = wait on <sensitivity signals list>;
end process; end process;
1.2. Signal Assignment 4 .4
• Syntax:
[label:] <signal> <= [delay_type] <expresion | waveform> {after <delay_time>};

• Examples: A B
Tmp <= A xor B after 10 ns;
Z <= Tmp xor Cin after 10 ns; Cout Full Cin
Cout <= (A and B) or (Tmp and Cin) after 15 ns; Adder

W <= „0‟, „1‟ after 10 ns, „0‟ after 15 ns, „1‟ after 20 ns, Z
„0‟ after 28 ns, „1‟ after 40 ns, „0‟ after 50 ns;
Waveform

W t 0 10 15 20 28 40 50
driver v 0 1 0 1 0 1 0
W
(ns)
59
0 10 20 30 40 50 60 70
1.3. Conditional Signal Assignment 4 .4
• Syntax:
[<label>:] <signal> <= [delay_type]
{<expression|waveform> when <boolean expression> else}
< expression|waveform> [when <boolean expression>];

• Examples: process (Sel, A, B)

begin
if Sel = „0‟ then
S <= A;
S <= A when Sel = „0‟ else B;
= else
process (Sel2, E1, E2)
begin
S <= B;
if Sel2 = “00” then
Equivalent end if;
S <= E1;
Process end process;
elsif Sel2 = “11” then
S <= E2;
else
null;
S <= E1 when Sel2 = “00” else
E2 when Sel2 = “11” else
unnafected when others;
= end if;
end process;
Equivalent
Process
 1.4. Selective Signal Assignment 4 .4
• Syntax:
[<label>] with <expression> select
<signal> <= [delay_type]
{<expression|waveform> when <value>,}
<expression|waveform> when <value>;

• Examples:
process (Op1, Op2, Operation)
with Operation select begin
Result <= Op1 + Op2 when add, case Operation is
Op1 - Op2 when subs, when add => Result <= Op1 + Op2;
Op1 and Op2 when andL, = when subs => Result <= Op1 - Op2;
Op1 or Or2 when orL; when andL => Result <= Op1 and Op2;
when orL => Result <= Op1 or Op2;
end case;
Equivalent end process;
Process
Type opcode is (add, subs, andL, orL);
Signal operation : opcode; 61
 1.5. Components 4 .4
• Structural and hierarchical descriptions by using components defined somewhere else.
• Syntax for component declaration:
component <idname> [is]
[generic (<generic parameters list>);]
[port (<ports list>);]
end [component] [<idname>];

• Syntax for component reference or instantiation:

<label>: <idname>
[generic map (<parameters association list>);]
[port map (<ports association list>);]

• Examples:
Association lists by:
• position
component example is U2 : example port map (X, Y, W, Z)
port(a, b, c : in bit;
• name
d : out bit); U4 : example port map
end component example; (d=>Z, a=>X, b=>Y, c=>W);
1.5. Componentes 4 .4
entity FullAdder is
begin
port(X, Y, CIn : in bit; U1 U3
Cout, Sum : out bit); A
end FullAdder;
X Half OrG COut
Y Adder B C
architecture structural of FullAdder is Half
component HalfAdder Adder
port(I1, I2 : in std_logic; CIn Sum
COut, Sum : out std_logic); U2
end component;
component OrG
port(I1, I2 : in std_logic; I1 I2 Sum Cout
O : out std_logic); 0 0 0 0
end component; 0 1 1 0
Positional association list
signal A, B, C : std_logic; 1 0 1 0
begin 1 1 0 1
U1: HalfAdder port map (X, Y, A, B);
U2: HalfAdder port map (B, CIn, C, Sum); Sum <= I1 xor I2; Cout <= I1 and I2;
U3: OrG port map (O => COut, I1 => A, I2 => C);
end structural; 63
Nominal association list
1.6. Generate 4 .4
• Generally used to create “arrays” of component instances, but it could include any other
concurrent sentence.
• Syntax: <label>: {[for <range specification> | if <condition> ]}
generate
entity Register is Parallel in/out
{<concurrent sentences>}
generic (N: positive);
end generate; N-bits Register
port( Clk : in std_logic;
E : in std_logic_vector(N-1 downto 0);
S out std_logic_vector(N-1 downto 0));
• Example: end Register;
architecture structural of Register is
component DFF
E(N-1) E(N-2) E(0) port (Clk : in std_logic;
E : in std_logic;
S : out std_logic);
DFF DFF DFF end component;
variable I : integer;
begin
GenReg: for I in N-1 downto 0 generate
Clk S(N-1) S(N-2) S(0) Reg: DFF port map(Clk, E(I), S(I));
end generate;
end structural;
1.7. Assert, Procedure call & Function call 4 .4

• Same usage and behaviour as the equivalent sequential ones, but in the concurrent world.
[label:] assert <boolean expression>
[report <string of characters>]
[severity (note | warning | error |failure);

• “Function call” could be embedded in any expression inside a concurrent statement.

function Check_Timing(min_time, max_time, clk, sig_to_test) returns boolean;

assert Check_Timing(min_time, max_time, clk, sig_to_test)

report “Timing error”
severity (warning);

• Concurrent “Procedure call” is just like a process with procedure parameters in the sensitivity
list. [label:] <Procedure name> [(<parameters>)];

Check_Timing(min_time, max_time, clk, sig_to_test, testOK);

66
1.8. Procedure vs. Process in concurrent world 4 .4
• A process can be modelled by its equivalent procedure
o Signal in the process sensitivity list are moved to procedure formal parameters
o The procedure parameters must contain all the input/output signals on the process block

Signal rst, ck, d, q: std_logic; procedure FFD (signal rst, clk, d: in std_logic;
…/… …/… signal q: out std_logic);
FFD: process (rst, clk); begin
begin if rst = „1‟ then
if rst = „1‟ then Q <= „0‟;
Formal parameters
Q <= „0‟; elsif (clk‟event and clk=„1‟) then
elsif (clk‟event and clk=„1‟) then Q <= D;
Q <= D; end if; end if;
end if; end if; end procedure; D Flip-flop
end process; D Flip-flop
o Declared in a package accessed by “Use” sentence
o Simultaneous definition and usage o Used by instantiation with actual parameters  easy reuse
o Repeated usage  Cut & Paste of the process o Before simulation the procedures are moved to its
 Component & references to it equivalent processes 67
2 Modelling, Simulation and Synthesis 4 .4
package my_package is
type operation is (add,sub);
end my_package;
use work.my_package.all;
entity AddSub is
Port (signal a, b: in std_logic_vector(3 downto 0);
signal opcode : in operation;
signal sign : out std_logic;
signal z : out std_logic_vector(4 downto 0));
End entity AddSub;

Architecture Functional of AddSub is

Begin
Operate: process (a, b, opcode);
variable x, y : std_logic_vector(3 downto 0);
variable s : std_logic;
begin
if a >= b then x := a; y := b; s := „0‟;
else x := b; y := a; s := „1‟;
case opcode is
when add then z <= „0‟&x + „0‟&y; sign <= „0‟;
when sub then z <= „0‟&x – „0‟&y; sign <= s;
end case
end process Operate;
End Architecture Functional;
2 Modelling, Simulation and Synthesis 4 .4
Complete “Test_Bench” System
Stimuli
Generation
Input stimuli

Test Bench Module under Test

-MuT-

VHDL

VHDL
Results Output
Analysis results

Complete “Test_Bench” System

Stimuli
Generation
Input stimuli

Test Bench Module under Test

-MuT-
Output
VHDL results VHDL

69
 2 Modelling, Simulation and Synthesis 4 .4
Modulo a verificar (MuT) Banco de pruebas
Module under Test
use work.my_package.all; (Test_Bench)
entity AddSub is
Port (signal a, b: in std_logic_vector(3 downto 0);
signal opcode : in operation;
signal sign : out std_logic;
signal z : out std_logic_vector(4 downto 0));
End entity AddSub;

Architecture Functional of AddSub is

Begin
Operate: process (a, b, opcode);
variable x, y : std_logic_vector(3 downto 0);
variable s : std_logic;
begin
if a >= b then x := a; y := b; s := „0‟;
else x := b; y := a; s := „1‟;
case opcode is
when add then z <= „0‟&x + „0‟&y; sign <= „0‟;
when sub then z <= „0‟&x – „0‟&y; sign <= s;
end case
end process Operate;
End Architecture Functional; 70
 2 Modelling, Simulation and Synthesis 4 .4
Modulo a verificar (MuT) Banco de pruebas
Module under Test (Test_Bench)
use work.my_package.all;
entity AddSub is use work.my_package.all;
Port (signal a, b: in std_logic_vector(3 downto entity 0);TB_AddSub is end;
signal opcode : in operation;
signal sign : out std_logic; architecture Test_Bench of TB_AddSub is
signal z : out std_logic_vector(4 downto signal0));c, d : std_logic_vector(3 downto 0);
End entity AddSub; signal oper : operation; signal signo : std_logic;
signal res : std_logic_vector(4 downto 0);
Architecture Functional of AddSub is Begin
Module under Test
Begin MuT: entity work.AddSub(Functional)
Operate:Complete
process “TB_AddSub”
(a, b, opcode); system port map (c, d, oper, signo, res);
variable x, y : std_logic_vector(3 downto 0);
Stimuli c,d Input stimuli a,b
variable s : oper
std_logic; opcode Stimuli: process; Test vectors wavefroms
Generation
begin begin
if a Test
>= bBench:
then x := a; y := b; s := „0‟; c <= “0110”; d <= “0011”; oper <= add;
else x := b; y := MuT:
a; s AddSub
:= „1‟;
Stimuli: Process wait for 100 ns;
case opcode is oper <= sub; wait for 100 ns;
VHDL

when add
Results thenOutput
signo z <= „0‟&x
sign + „0‟&y; sign <= „0‟;
d <= “1001”; wait for 100 ns;
Analysis res
when sub thenresults
z <= „0‟&x – „0‟&y;
z VHDL sign <= s; <= add; wait;
oper
end case end process Stimuli;
end process Operate;
End Architecture Functional; end Test_Bench; 71
2 Modelling, Simulation and Synthesis 4 .4
Banco de pruebas
(Test_Bench)
use work.my_package.all;
entity TB_AddSub is end;
architecture Test_Bench of TB_AddSub is
signal c, d : std_logic_vector(3 downto 0);
signal oper : operation; signal signo : std_logic;
signal res : std_logic_vector(4 downto 0);
Begin
Module under Test
MuT: entity work.AddSub(Functional)
port map (c, d, oper, signo, res);

Stimuli: process; Test vectors wavefroms

begin
c <= “0110”; d <= “0011”; oper <= add;
wait for 100 ns;
oper <= sub; wait for 100 ns;
d <= “1001”; wait for 100 ns;
oper <= add; wait;
end process Stimuli;
end Test_Bench;
2 Modelling, Simulation and Synthesis 4 .4
Exercise
Next two stimuli generation processes, could be considered equivalent to generate stimuli for
the previous example?
Stimuli: process; Test vectors wavefroms
begin
c <= “0110”; d <= “0011”; oper <= add;
wait for 100 ns;
oper <= sub; wait for 100 ns;
d <= “1001”; wait for 100 ns;
oper <= add; wait;
end process Stimuli;

Stimuli: process; Test vectors wavefroms

begin
c <= “0110” after 0ns;
d <= “0011” after 0ns, “1001” after 200ns;
oper <= add after 0ns, sub after 100ns, add after 300ns;
wait for 100 ns;
wait for 100 ns;
wait for 100 ns;
wait;
end process Stimuli; 73
2 Modelling, Simulation and Synthesis 4 .4
Exercise (solution)
Next two stimuli generation processes, could be considered equivalent to generate stimuli for
the previous example?
Answer: YES Stimuli: process; Test vectors wavefroms
begin
On the first process we are providing new values to c <= “0110”; d <= “0011”; oper <= add;
inputs of AddSub module as simulation time wait for 100 ns;
oper <= sub; wait for 100 ns;
progresses. d <= “1001”; wait for 100 ns;
oper <= add; wait;
On the second process:
end process Stimuli;
- At the beginning we define the inputs of AddSub
Stimuli: process; Test vectors wavefroms
modules and load those values into the begin
related signal drivers. c <= “0110” after 0ns;
d <= “0011” after 0ns, “1001” after 200ns;
- Later on we use the sentence “wait” in oper <= add after 0ns, sub after 100ns, add after 300ns;
order to progress in time slots of 100ns wait for 100 ns;
wait for 100 ns;
accordingly to events in the input signal wait for 100 ns;
drivers. This way the input values are wait;
evaluated by the AddSub on due time. end process Stimuli;
2 Modelling, Simulation and Synthesis 4 .4
entity ParallelAdder is
generic (n : natural := 4);
port ( X, Y : in std_logic_vector(n-1 downto 0);
Cin : in std_logic;
Z : out std_logic_vector(n-1 downto 0);
Cout : out std_logic);
End ParallelAdder ;

achitecture Functional of ParallelAdder is

Begin
process (X, Y, Cin);
variable C : std_logic_vector(n downto 0);
variable tmp : std_logic;
variable I : integer;
begin
C(0) := Cin;
for I in 0 to n-1 loop
tmp := X(I) xor Y(I);
Z(I) <= tmp xor C(I);
C(I+1) := (tmp and C(I)) or (X(I) and Y(I));
end loop;
Cout <= C(n);
end process;
end Functional;
2 Modelling, Simulation and Synthesis 4 .4
entity ParallelAdder is
generic (n : natural := 4);
port ( X, Y : in std_logic_vector(n-1 downto 0);
Cin : in std_logic;
Z : out std_logic_vector(n-1 downto 0);
Cout : out std_logic);
End ParallelAdder ;
Logic Simulation
achitecture Functional of ParallelAdder is
Begin
process (X,X Y, Cin);
Y
variable Cin
C : std_logic_vector(n downto 0);
Z
variable tmp : std_logic;
variable I : integer;
begin
C(0) :=
CoutCin;
for I in 0 to n-1 loop
tmp := X(I) xor Y(I);
Z(I) <= tmp xor C(I);
C(I+1) := (tmp and C(I)) or (X(I) and Y(I));
end loop;
Cout <= C(n);
end process;
end Functional;
2 Modelling, Simulation and Synthesis 4 .4
entity ParallelAdder is
generic (n : natural := 4);
port ( X, Y : in std_logic_vector(n-1 downto 0);
Cin : in std_logic;
Z : out std_logic_vector(n-1 downto 0);
Cout : out std_logic);
End ParallelAdder ;
Logic Simulation
achitecture Functional of ParallelAdder is
Begin
process (X,X Y, Cin);
Y
variable Cin
C : std_logic_vector(n downto 0);
Z
variable tmp : std_logic;
variable I : integer;
begin
C(0) :=
CoutCin; Cout
for I in 0 to n-1 loop
tmp := X(I) xor Y(I);
X Z(I) <= tmp xor C(I);
C(I+1) := (tmp and C(I)) or (X(I) and Y(I));
end loop;
Z
Y Cout <= C(n);
end process;
end
Cin Functional; Logic Synthesis
SUMMARY 4 .4
• VHDL concurrent sentences (inside an architecture, block or entity)
 Selected sentences:
• Process • Components • Assert
• signal assignments (uncond. & cond.) • Generate • Functions & Procedures

• VHDL modelling, simulation & synthesis: basic concepts and flows

• VHDL Examples based learning

This ends our short introduction to VHDL language for its usage in the current…
“Digital Systems Course”

78