Computer Architecture and Organization

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 Syllabus

Number Representation and Arithmetic Operations, Character Representation, Memory

locations and addresses, Memory operations, Addressing modes, CISC and RISC.
Hardware for addition and subtraction, Multiplication, Hardware implementation,
Booth's algorithm, Division, Floating point representation, IEEE standard floating-point
representation. Bus organization, comparison of hardwired and micro-programmed
approach, hardwired control design, Booths multiplier design, Micro-programmed
multiplier control unit. Internal organization of memory chips, Structure of Larger
Memories, Cache mapping functions, Replacement algorithms, and Virtual memories.
Accessing I/O devices, Interrupts, Enabling and disabling Interrupts, DMA. Pipeline
Organization, Data dependencies, Handling data dependencies, Hardware
multithreading, SIMD Processing, Graphics processing units, Shared memory
multiprocessors, Interconnection Networks, Cache Coherence, Write-Through Protocol,
Write-Back protocol, Directory-Based Cache Coherence

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 References:

1. Carl Hamacher, Zvonko Vranesic and Safwat Zaky, Computer Organization and
Embedded Systems, (6e), McGraw Hill Publication, 2012.
2. William Stallings, Computer Organization and Architecture – Designing for
Performance, (9e), PHI, 2015.
3. Mohammed Rafiquzzaman and Rajan Chandra, Modern Computer Architecture,
Galgotia Publications Pvt. Ltd., 2010

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 Hardware implementation of
Arithmetic operation with signed
numbers

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Binary Number Representation

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Signed and Unsigned Binary

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Finding 1’s complement

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Inverters used to obtain 1’s complement of a binary
numbers

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Finding 2’s complement

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Finding 2’s complement

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Representation of the signed integers in Binary Three forms

Signed integers in Binary

Signed
1’s 2’s
Magnitude
Complement Complement
form

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Representation of the signed integers in Binary Three forms

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Representation of the signed integers in Binary Three forms

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Representation of the signed integers in Binary Three forms

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Representation of the signed integers in Decimal forms

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Representation of the signed integers in Decimal forms

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Range on 2’s complement representation

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• Arithmetic operation with
numbers Addition

Subtraction

Multiplication

Division
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Addition with Unsigned number

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Subtraction with Unsigned number

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Rules for Addition and Subtraction using Signed –
Magnitude Data

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Hardware for sign Magnitude addition and subtraction

When SW= 0 ,the output

of B is transferred to the
adder (Output=A+B)

When SW= 1 ,the 1’s

compliment of B is
applied to the adder
(Output=A+B’+1)

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Signed 2’s compliment addition and subtraction

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Hardware for signed 2’s compliment addition and
subtraction

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Overflow?

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Examples of Overflow

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Multiplication with Unsigned number

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Hardware Implementation of multiplication

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Example

Multiplicand = 10111
Multiplier = 10011

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 Booth’s Algorithm Multiplication with signed 2's complement
data
• Booth algorithm gives a procedure for multiplying binary integers in
signed 2’s complement representation in efficient way.

• less number of additions/subtractions required.

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Hardware
Implementation of
Booths Algorithm –

register as A, B and Q, AC, BR and

QR respectively.

Qn designates the least significant

bit of multiplier in the register QR.

An extra flip-flop Qn+1is appended

to QR to facilitate a double
inspection of the multiplier.

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 Booth’s
Algorithm
Flowchart –
AC and the appended bit Qn+1 are initially
cleared to 0

the sequence SC is set to a number n equal to

the number of bits in the multiplier.

The two bits of the multiplier in Qn and

Qn+1are inspected.

If the two bits are equal to 10, it means that

the first 1 in a string has been encountered.

This requires subtraction of the multiplicand

from the partial product in AC

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Example – A numerical example of booth’s algorithm , multiplication of -5 and -7.
BR = -5 = 1011,

BR' = 0100, <-- 1's Complement (change the values 0 to 1 and 1 to 0)

BR'+1 = 0101 <-- 2's Complement (add 1 to the Binary value obtained after 1's complement)

QR = -7 = 1001 <-- 2's Complement of 0111 (7 = 0111 in Binary)

The explanation of first step is as follows: Qn+1

AC = 0000, QR = 1001, Qn+1 = 0, SC = 4

Qn Qn+1 = 10

So, we do AC + (BR)'+1, which gives AC = 0101

On right shifting AC and QR, we get

AC = 0010, QR = 1100 and Qn+1 = 1

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 2's Complement of
0111

OPERATION AC QR Qn+1 SC
0000 1001 0 4
AC + BR’ + 1 0101 1001 0
ASHR 0010 1100 1 3
AC + BR 1101 1100 1
ASHR 1110 1110 0 2
ASHR 1111 0111 0 1
AC + BR’ + 1 0100 0111 0
ASHR 0010 0011 1 0

Product = AC QR
Product = 0010 0011 = 35
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 Problem

Multiply -9 and -13 by booth’s algorithm method

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 Problem

Multiply 7 and 3 by booth’s algorithm method

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Advantages
Faster than
traditional
multiplication

Efficient
Widely
for
used in
signed
hardware
numbers

Lower hardware
requirement

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Disadvantages

Complex to Limited
understand applicability

Higher
Higher
power
latency:.
consumption

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Division

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Hardware Implementation of division

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Flowchart of Division

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Example

Divisor B=10001,
Dividend = 0111000

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