Chapter 3 Computer Architecture
Chapter 3 Computer Architecture
A DMC SC 2023
Computer Architecture
CPU architecture refers to the internal logical structure and organisation of the computer hardware.
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The Arithmetic & Logic Unit (ALU) allows the required arithmetic or logic (e.g. AND, OR) operations
to be carried out while a program is being run.
Control Unit
Registers
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O Level Hardware: Computer Architecture © N.A DMC SC 2023
Memory
The address will uniquely identify every location in the memory and the contents will be the binary
value stored in each location.
How the MAR and MDR registers can be used when carrying out a read and write operation to and
from memory
• The address of location 1111 0001 to be read from is first written into the MAR (Memory
Address Register):
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We want to show how the value 1001 0101 was written into memory location 1111 1101:
• The data to be stored is first written into the MDR (Memory Data Register):
• This data has to be written into location with address: 1111 1101; so this address is now
written into the MAR:
• Finally, a ‘write signal’ is sent to the computer memory and the value 10010101 will then be
written into the correct memory location.
(System) buses
• (System) buses are used in computers as parallel transmission components.
• Each wire in the bus transmits one bit of data.
There are three common buses used in the von Neumann architecture:
i. address bus,
ii. data bus and
iii. control bus.
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Address bus
Data bus
• It is bidirectional (allowing data to be sent in both directions along the bus). This means data
can be carried from CPU to memory (and vice versa) and to and from input/output devices.
• The wider the bus, the larger the word length that can be transported.
Control bus
• It is bidirectional.
• It carries signals from the control unit (CU) to all the other computer components.
• It is usually 8-bits wide.
• There is no real need for it to be any wider since it only carries control signals.
Fetch–Decode–Execute cycle
To carry out a set of instructions,
• The CPU first of all fetches some data and instructions from memory.
• The CPU then stores them in suitable registers.
• Both the address bus and data bus are used in this process.
• Once this is done, each instruction needs to be decoded before finally being executed.
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O Level Hardware: Computer Architecture © N.A DMC SC 2023
Using a clock speed higher than the computer was designed for can lead to problems:
Instruction set
• Instruction sets are low-level language instructions that instruct the CPU how to carry out an
operation.
• A limited number of opcodes can be used by a computer.
• Instructions are a set of operations which are decoded in sequence.
• Each operation will instruct the ALU and CU (which are part of the CPU).
• An operation is made up of an opcode and an operand.
The operand is the data which needs to be acted on or it can refer to a register in the memory.
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O Level Hardware: Computer Architecture © N.A DMC SC 2023
Embedded systems
• An embedded system is a combination of hardware and software designed to carry out a
specific set of functions.
• The hardware is electronic, electrical or electro-mechanical.
• Embedded systems are either programmable or non-programmable.
• Microcontrollers
• Microprocessor
• system on chips (SoC)
i. connecting the device to a computer and allowing the download of updates to the software
ii. automatic updates via a Wi-Fi, satellite or cellular (mobile phone network) link
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References: Cambridge IGCSE & O Level Computer Science (D. Watson & H. Williams)
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