Module-4

CMOS Circuits
Performance
Analysis
Module 4: CMOS Circuits Performance Analysis
Delay Estimation, Logical Effort and Transistor Sizing, Performance Estimation -
Static & Dynamic Power Dissipation

Text Books:
•Neil H.Weste, Harris, A. Banerjee, CMOS VLSI Design, A circuits and System
Perspective, 2015, 4th Edition, Pearson Education, Noida, India.
•Sung-Mo Kang, Yusuf Liblebici, Chulwoo Kim, CMOS Digital Integrated Circuits:
Analysis and Design, 2019, Revised 4th Edition, Tata Mc Graw Hill, New Delhi, India.
Reference Books:
 Design and Analysis of VLSI Subsystems, Prof. Madhav Rao, NPTEL, IIT MADRAS
https://www.youtube.com/watch?v=bZyCbWS3lTo&list=PL5PDqJ5saHRIrtX-
rhGiAZzNrjX1MiU3q&index=25
 Jan M. Rabaey, Anantha Chadrakasan, Borivoje Nikolic, Digital Integrated Circuits: A
Design Perspective Paperback, 2016, 2rd Edition, Pearson Education, India.

Course Objective:
Describe the fundamental principles underlying digital design using CMOS logic and
analyze the performance characteristics of these digital circuits. 2
Course Outcome:
CO4: Analyse the various logic families and efficient techniques at circuit level for
improving power and speed of combinational and sequential logic.
Delay Definitions
Transistor sizing :: Resistance and Capacitances
If a pair of PMOS and NMOS FETs of same dimension are considered,
• The channel resistance offered by an NMOS is R.
• Whereas the channel resistance offered by the PMOS is at least 2R
(twice that of NMOS) due to its poor mobility of holes compared to
electrons.
• Hence, under same dimensions, PMOS offers less drive current than
NMOS.
• As a result, in a CMOS circuit with pull-up (PMOS) and pull-down
(NMOS) of same size (W/L of channel), the charging and discharging
times are not equal.
• The charging path (pull-up) resistance is greater than the discharge
path (pull-down) resistance. This in turn causes asymmetric circuit
design in CMOS logic.
• To design a symmetric CMOS circuit, it is necessary to improve the
drive strength of PMOS on par with NMOS by reducing the channel
resistance of PMOS FET.
 Transistor sizing :: Resistance and Capacitances
• To design a symmetric CMOS
circuit, it is necessary to
improve the drive strength of
PMOS on par with NMOS by
reducing the channel resistance
of PMOS FET (equating with
NMOS channel resistance).
• Channel resistance is
inversely proportional to
channel area (WL).
• Since channel length (L) is
fixed for a technology, the area • However, the capacitance of
of the channel and hence the MOSFET is proportional to area
channel resistance can be of the channel as shown above.
changed by changing the • In the above figure, k is the width
width (W) of the channel. multiplication factor.
 Transistor sizing :: Resistance and Capacitances
• In below figure, sizes are represented in terms of λ. Here, λ=L/2.
• For any MOSFET, the minimum width of the channel is twice its length.
• In PMOS FET, to bring down the channel resistance to R (equal to NMOS
resistance), minimum width (4λ=2L) is doubled to 8λ as shown below.
 Transistor sizing ::
CMOS Inverter – Symmetry by sizing

• In PMOS FET, to bring down the channel resistance to R (equal to NMOS

resistance), minimum width (4λ=2L) is doubled to 8λ as shown above.
• Hence, in the symmetric CMOS inverter (shown above), charging (pull-up
stage) and discharging (pull-down stage) path resistances are equal to R.
 Transistor sizing ::
CMOS Inverter – Symmetry by sizing
Examples of sizing: Sizing 2-input NAND and NOR gates
With reference inverter Wp:Wn=2:1
 RC model of transistor ::
CMOS Inverter approximated to RC circuit
• The width multiplication factor of
MOSFET is given as 2. Hence width of
PMOS is double the width of NMOS. So,
the resistance of PMOS is reduced to R
(before sizing, it was 2R).
• However, terminal capacitances of PMOS
are increased in same proportion as width.
• The terminal capacitances of MOSFET
show here are between Gate-Body,
Source-Body, and Drain-Body.
• Body terminals of PMOS and NMOS are
connected to their respective source
terminals for zero body effect.
• In NMOS, source/body is connected to
ground whereas in PMOS, source/body is
connected to VDD.
RC model of transistor :: with unit CMOS Inverter driving
another unit CMOS inverter
• Since body and source are at same potential, Source-Body capacitance
doesn’t charge/discharge in both PMOS and NMOS.
• So, Source-Body capacitances doesn’t contribute in propagation delay.
 RC model of transistor ::
Capacitance seen at the output of first stage of
unit CMOS Inverter driving another inverter
 RC model of transistor ::
Capacitance seen at the output of first stage of
unit CMOS Inverter driving another inverter

Figure: Capacitances at the output/load of

first stage for Inverter delay estimation
 RC model of transistor ::
Capacitance seen at the output of both stages of
unit CMOS Inverter driving another inverter

Figure: Capacitances at the output/load of

first stage for Inverter delay estimation
Delay estimation at output of first stage
of unit CMOS Inverter driving another
inverter
Delay estimation at output of second
stage of unit CMOS Inverter driving
another Inverter
Sizing a Transistors for a 3-Input NAND Gate and
Capacitance representation

Reference inverter
considered for sizing
NAND3
Sizing a Transistors for a 3-Input NAND Gate and
Capacitance representation
Sizing a Transistors for a 3-Input NAND Gate and
Capacitance representation
Sizing a Transistors for a 3-Input NAND Gate and
Capacitance representation
Sizing a Transistors for a 3-Input NAND Gate and
Capacitance representation

• The input (gate) terminals of pull-up and pull-down are tied together. So
Gate-Body capacitance at both gates are added as 2C+3C=5C.
• The output node (Y) is common point for drain terminals of all three
pull-up devices and one pull-down device. Hence, the Drain-Body
capacitances of all these devices (three pull-up and one pull-down) are
added as 2C+2C+2C+3C=9C.
Sizing a Transistors for a 3-Input NAND Gate and
RC equivalent at output for falling and rising
transition (worst case)

(a) (b)

The fall transition (a) shows that all the NMOS transistors need to be switched
ON while the rise transition (b) shows a worst-case where at least one PMOS is
switched ON while two NMOS transistors are ON, as well, contributing to the
total capacitance of the circuit.
Delay Estimation using Elmore delay model
 Delay Estimation using Elmore delay model :
Example 1
Compute the Elmore delay for Vout in the 2nd order RC system shown
in below figure

Solution:
The circuit has a source and two nodes. At node n1, the capacitance is C1 and
the resistance to the source is R1. At node Vout, the capacitance is C2 and the
resistance to the source is (R1 + R2).
Hence,
the propagation delay at node n1 is tpd = R1C1 + R1C2
In the above Elmore delay estimation at node n1, the OFF-path (path other
than required node) capacitance C2 is accounted for delay by multiplying it
with sharing resistance (R1 here). The OFF-path resistance R2 is ignored.
the propagation delay at node V is t = R C + (R + R )C
 Delay Estimation using Elmore delay model :
Example 2

Here the propagation delay (using Elmore model) at node 7 is calculated as,

• In the above propagation delay estimation (using Elmore model) at node

D7, the OFF-path (path other than required node) capacitances are
accounted for delay by multiplying them with total sharing resistance.
• The OFF-path resistances are ignored.
 Delay Estimation using Elmore delay model :
Example 2 (continued)

Here the propagation delay (using Elmore model) at node 5 is calculated as,

In Elmore delay model, the propagation delay from a switching source to an

ith branch node is given as the product of the capacitance “Ci” of the node with the
sum of the resistance from the source to the node, Ris.
Delay Estimation using Elmore delay model : Example3: NAND3

Sized as per reference

inverter of Wp:Wn=2:1
Propagation delay for falling at ‘Y’ : tpdf = (3C)(R/3) + (3C)(R/3 + R/3) +
(9C)(R/3 + R/3+ R/3) = 12RC.
Propagation delay for rising at ‘Y’ : tpdr = 9CR+3CR+3CR=15RC
• In above calculation, the OFF-path (path other than required node
‘Y’) capacitances are accounted (total capacitance = 9C) for delay
by multiplying them with total sharing resistance.
• The OFF-path resistances are ignored.
Delay Estimation using Elmore delay model : NAND3

For the 3-input NAND gate (shown above), if the output is loaded with h
identical NAND gates, then Propagation delay for falling and rising can be
estimated as
tpdf = (3C)(R/3) + (3C)(R/3 + R/3) + ((9 + 5h)C)(R/3 + R/3+ R/3) = 12RC + 5hRC.

tpdr = (9+5h)CR+3CR+3CR=15RC+5hRC

Since, each NAND gate input has 5C capacitance.

 Delay normalization
Example: NAND3 sized with 2:1 reference inverter
Normalized delay (d) is calculated by dividing the delay of the given circuit (after sizing)
with the delay of its reference inverter.
Example:
For the 3-input NAND gate whose output is loaded with h identical NAND gates, then
Propagation delay for falling and rising is estimated as
tpdf = 12RC + 5hRC tpdr = 15RC+5hRC

The 3-input NAND gate in the above example is sized with 2:1 reference inverter.
The fall and rise propagation delays (using Elmore delay model) of 2:1 reference inverter is
as follows,
tpdf = 3RC tpdr = 3RC

Then the normalized delay (d) for tpdf is Then the normalized delay (d) for tpdr is
d= =
d= =

Parasitic delay (p) Logical effort (g) fan out or Electrical effort (h)

Effort delay (f)=gh

Normalized delay (d) = p+gh = p+f
 Normalized delay (d)
Delay (normalized) of a gate ‘d’ has two components

d=p+f

• A fixed part due to its own parasitic capacitances called parasitic delay p

parasitic delay, p = Cout_of_circuit_without_load/Cout_inverter

• A part proportional to the load on the output called the effort delay or
stage effort ‘f’.

f=g*h
 Normalized delay (d) continued

f=g*h
g = logical effort which captures properties of the gate’s structure

Logical effort of a gate is defined as the ratio of the input

capacitance of the gate to the input
capacitance of an inverter that can deliver the same output
current.
Equivalently, logical effort
indicates how much worse a gate is at producing output current as
compared to an inverter, given that each input of the gate may only
present as much input capacitance as the inverter.

h = electrical effort or fanout which captures properties of load and

transistor sizes
Electrical effort or fan out, h = Cout_of circuit_due_to_total_load/Cin_circuit
Logical effort
Logical effort
Logical effort
Logical effort
Logical effort
Logical effort
 Self test for Module-3 and Moule-4
For the Boolean expression Y=(AB+C’)D ,

1. Draw the CMOS schematic (circuit).

2. Size the circuit with reference inverter Wp:Wn=3:1
3. Represent the R and C values of sized circuit.
4. Draw the equivalent RC network for worst case output falling and rising.
5. Draw the stick diagram for the schematic drawn in question-1.
6. Estimate the area of the stick diagram by counting number of horizontal
and vertical metal tracks.
Delay Estimation

• In Linear delay model, the inter node diffusion capacitances (if any) in
the on path (charging/discharging) is ignored.
• This model only consider the capacitances associated with output node.
• Hence the Liner delay is estimated using path resistance of on path and
output capacitance (it includes the total capacitance at output node).
 Delay Estimation using Linear delay model
Example 1: NAND3 sized with 2:1 inverter

For the 3-input NAND gate (shown above), if the output is loaded with h
identical NAND gates, then Propagation delay for falling and rising can be
estimated (using Linear delay model) as
tpdf = (9C + 5hC)(R/3 + R/3+ R/3) = 9RC + 5hRC tpdr = (9C + 5hC)R = 9RC + 5hRC

The normalized delay (d) for falling and rising is as follows,

d= = d= =
Comparison of Elmore and Linear delay models
Example 2: NAND3 sized with 2:1 inverter
 Normalized delay estimation using Linear delay model
Example 3: NOR3 sized with 2:1 inverter

Delay (normalized), d = p + f Effort delay f= g * h

parasitic delay, p = Cout_of_circuit_without_load/Cout_inverter
Logical effort, g = Cout_of circuit_due_to_single_identical_load/Cout_inverter
Electrical effort or fanout, h = Cout_of circuit_due_to_total_load/Cin_circuit
 Normalized delay estimation using Linear delay model
Examples 4: NAND2 & NOR2 sized with 2:1 inverter

Delay (normalized), d = p + f Effort delay f= g * h

parasitic delay, p = Cout_of_circuit_without_load/Cout_inverter
Logical effort, g = Cout_of circuit_due_to_single_identical_load/Cout_inverter
Electrical effort or fanout, h = Cout_of circuit_due_to_total_load/Cin_circuit
Delay
 Comparison of Elmore and Linear delay models
Example 5: Self test
Can you say, what is the reference inverter size (wp:wn) used for sizing
the below circuit ? Estimate the rise and fall propagation delay of the
given circuit using Elmore and linear delay models. (Find worst case
delay)
 Definitions of the Normalized delay (d):
Logical Effort (g)
g = logical effort which captures properties of the gate’s structure
Definitions of the Normalized delay (d):
Logical Effort (g)
Definitions of the Normalized delay (d):
Parasitic delay (p)
Definitions of the Normalized delay (d):
Parasitic delay (p)
 Generalization of formulas for
Parasitic delay (P) and Logical Effort (g)
Generalized formula for Parasitic delay (P) for any N-input gate is

P=N

Generalized formula for Logical effort (g) of N-input NAND gate is

𝑁 +2
gN_NAND = 3

Generalized formula for Logical effort (g) of N-input NOR gate is

2 𝑁 +1
gN_NOR = 3
Representation of Gate size or Gate input
capacitance
Delay estimation and gate size optimization Example 1
Estimate the delay of an inverter driving an identical inverter, as in the
ring oscillator shown in Figure. Estimate the normalized delay using
Linear delay model if not specified. Assume 2:1 inverter if not
specified.

Solution:
The inverter’s output is connected to the input of an identical inverter,
parasitic delay, p = Cout_of_circuit_without_load/Cout_inverter = 3/3 = 1
Logical effort, g = Cout_of circuit_due_to_single_identical_load/Cout_inverter = 3/3 = 1
Electrical effort or fanout, h = Cout_of circuit_due_to_total_load/Cin_circuit = 3/3 =1

Delay, d = p + gh =1+1x1=2
Delay estimation and gate size optimization Example 2
Estimate the delay of a fanout-of-4 (FO4) inverter, as shown in Figure.
Estimate the normalized delay using Linear delay model if not
specified. Assume 2:1 inverter if not specified.

Solution:
The inverter’s output is connected to the input of 4 identical inverters,
parasitic delay, p = Cout_of_circuit_without_load/Cout_inverter = 3/3 = 1
Logical effort, g = Cout_of circuit_due_to_single_identical_load/Cout_inverter = 3/3 = 1
Electrical effort or fanout, h = Cout_of circuit_due_to_total_load/Cin_circuit = 12/3 =4

Delay, d = p + gh =1+1x4=5
Delay estimation and gate size optimization Example 3
A four-input nor gate (NOR4) drives 10 identical gates, as shown in
Figure. What is the delay in the driving nor gate?. Estimate the
normalized delay using Linear delay model if not specified. Assume
2:1 inverter if not specified.

Solution:
The NOR4 output is connected to the input of 10 identical NOR4 gates,
parasitic delay, p = Cout_of_circuit_without_load/Cout_inverter = 12/3 = 4
Logical effort, g = Cout_of circuit_due_to_single_identical_load/Cout_inverter = 9/3 = 3
Electrical effort or fanout, h = Cout_of circuit_due_to_total_load/Cin_circuit = 90/9 =10

Delay, d = p + gh =4+3x10 = 34 delay units

Delay
Delay
Delay
Delay
Delay estimation & sizing Example 4 : Multi stage circuit
Optimize the circuit in Figure to obtain the least delay along the path from
A to B.
The values C, y,
and z indicated in
the figure at each
gate represents
their respective
input capacitances
(size).
Solution procedure:
It is asked to optimize the circuit. Which means, we have to
• Calculate the minimum delay (dmin) of the given path and
• Calculate the values/relation between C, y, and z such that the delay
offered by the path is minimum.
Calculation the minimum delay (dmin) of the given path:
Path parasitic delay, P = p1+p2+p3+…
p1,p2,p3,..= Parasitic delay at each stage.
Path logical effort, G =g1.g2.g3. ….
Delay estimation Example 4 : Multi stage circuit (continued)
Optimize the circuit in Figure to obtain the least delay along the path from
A to B.

Solution procedure (continued):

Calculation the minimum delay (dmin) of the given path:
Electrical effort or fanout of the path, H = h1.h2.h3. ….
h1,h2,h3,…=Electrical effort or fanout per stage.
Note:
• While calculating fanout of the path (H) in multistage circuits, total load
capacitance at each stage is equal to load due to on path gate.
• Which means, in the above figure, the fanout at stage –II is h2=z/y. It is
not 3z/y.
• The impact of off path load is accounted in to branch effort
Delay estimation Example 4 : Multi stage circuit (continued)
Optimize the circuit in Figure to obtain the least delay along the path from
A to B.

Solution procedure (continued):

Calculation the minimum delay (dmin) of the given path:
Branching effort at each stage, b = (Con_path+Coff_path)/Con_path
Path Branching effort, B = b1.b2 . ….
Path effort delay, F= BGH
N = number of stages in the path
minimum effort delay per stage, =
Minimum path Delay,
Delay estimation Example 4 : Multi stage circuit (continued)
Optimize the circuit in Figure to obtain the least delay along the path from
A to B.

Solution procedure (continued):

Calculate the values/relation between C, y, and z such that the delay
offered by the path is minimum:
Transistors be sized to achieve least delay:
• Transistor sizing should be done at each stage to get minimum delay per
stage. Hence it is possible to get least delay in the path.
• Equate the minimum effort delay per stage () with effort delay per stage
that is f=gh so as to find out the values/relation of C, y, and z.
Delay estimation Example 4 : Multi stage circuit (continued)
Optimize the circuit in Figure to obtain the least delay along the path from
A to B.

While calculating p
and g values,
Solution: consider the
Calculation of Minimum path Delay (): schematic of the
Stage :I Stage :II Stage :II gate (after sizing
with its reference
p1 = 6/3=2 p2 = 6/3=2 p3 = 6/3 inverter).
g1 = 4/3 g2 = 4/3 g3 = 4/3 While calculating h
h1 = y/C h2 = z/y h3 = 4.5C/z values, consider the
b1 = (y+y)/y = 2 b2 = (z+z+z)/z = 3 gate sizes (input
capacitances) of the
Path parasitic delay, P = p1+p2+p3 = 6 circuit given in
Electrical effort or fanout of the path, H = h1.h2.h3 = 4.5 your question.
Delay estimation Example 4 : Multi stage circuit (continued)
Optimize the circuit in Figure to obtain the least delay along the path from
A to B.

Solution (continued):
Path logical effort, G =g1.g2.g3=(4/3)3
Path Branching effort, B = b1.b2 = 2*3 = 6
Path effort delay, F= BGH = 6(4/3)34.5 = 64
N = number of stages in the path = 3
Let, = minimum effort delay per stage.
Minimum path Delay, = 6 + 3 (64) 1/3 = 18 delay units
Delay estimation Example 4 : Multi stage circuit (continued)
Optimize the circuit in Figure to obtain the least delay along the path from
A to B.
Solution (continued):
Transistors be sized to achieve least delay:
• Transistor sizing should be done at each stage to get minimum delay per
stage. Hence it is possible to get least delay in the path.
• Lets find out the sizes of C, y, z such that delay per stage and hence the
path delay are minimum.
minimum effort delay per stage = (64)1/3 = 4.
Starting from last stage, the effort delay per stage is
= gh = (4/3) (4.5C/z)
By equating, 4 = (4/3) (4.5C/z)
Then, z=1.5C
Similarly, for second stage, the effort delay per stage is
= gh = (4/3) (3z/y) = (4/3) ((3*1.5C)/y)
By equating, 4=(4/3) ((3*1.5C)/y). Then, y=1.5C
Which means, for least/minimum path delay, gates should be sized as
y=z=1.5C.
 Delay estimation & sizing Example 5 : Multi stage circuit
Consider the path from A to B involving three two-input NAND gates shown
in Figure. The input capacitance of the first gate is C, and the load
capacitance is also C. What is the least delay of this path, and how should
the transistors be sized to achieve least delay?

Solution:
Least/minimum delay of considered path (dmin):
Stage :I Stage :II Stage :II
While calculating p
p1 = 6/3=2p2 = 6/3=2p3 = 6/3 and g values, consider
g1 = 4/3 g2 = 4/3 g3 = 4/3 the schematic of the
h1 = y/C h2 = z/y h3 = C/z gate (after sizing with
its reference inverter).
Path parasitic delay, P = p1+p2+p3 = 6
While calculating h
Path Logical effort, G = g1.g2.g3 = (4/3)3= 2.37 values, consider the
Electrical effort (Fanout) of the path, H = h1.h2.h3 = 1 gate sizes (input
Branching effort, B = 1 (only one branch in the path) capacitances) of the
Path effort delay, F = BGH = 2.37 circuit given in your
question.
N = number of stages in the path = 3
 Delay estimation Example 5 : Multi stage circuit (continued)
Consider the path from A to B involving three two-input NAND gates shown
in Figure. The input capacitance of the first gate is C, and the load
capacitance is also C. What is the least delay of this path, and how should
the transistors be sized to achieve least delay?

Solution (continued):
Least/minimum delay of considered path (dmin)
minimum effort delay per stage, = = (2.37) 1/3 = 4/3
Minimum path Delay, = 6 + 3 (4/3) = 10 delay units
Delay estimation Example 5 : Multi stage circuit (continued)

Solution (continued):
Transistors be sized to achieve least delay:
• Transistor sizing should be done at each stage to get minimum delay per
stage. Hence it is possible to get least delay in the path.
• Lets find out the sizes of C, y, z such that delay per stage and hence the
path delay are minimum.
minimum effort delay per stage, = (2.37)1/3 = 4/3.
Starting from last stage, the effort delay per stage is
= gh = (4/3) (C/z)
By equating, 4/3 = (4/3) (C/z)
Then, z=C
Similarly, for second stage, the effort delay per stage is
= gh = (4/3) (z/y).
By equating, 4/3 = (4/3) (z/y). Then, y=z=C
Which means, for least/minimum path delay, gates at all the stages
should be equally sized to C.
Delay estimation & sizing Example 6 : Multi stage circuit

Size the circuit in Figure for minimum delay. Suppose the load is 20 microns
of gate capacitance and that the inverter has 10 microns of gate capacitance.

Solution:
Calculation of dmin :
The path has parasitic delay, P = 1 + (6/3) + (6/3) + 1 = 6.
The path has logical effort, G = 1 × (5/3) × (4/3) × 1 = 20/9.
The path electrical effort, H = (x/10µm) (y/x) (z/y) (20µm/z) = 2.
The branching effort, B=1 (only one branch is there).
Thus, path effort delay, F = GBH = 40/9,
Number of stages, N=4
minimum effort delay per stage, = = 1.45.
Minimum path Delay, = 6 + 4 (1.45) = 11.8 delay units
Delay estimation Example 6 : Multi stage circuit (continued)
Size the circuit in Figure for minimum delay. Suppose the load is 20 microns
of gate capacitance and that the inverter has 10 microns of gate capacitance.

Solution (continued):
Transistors be sized to achieve least delay:
minimum effort delay per stage, = 1.45.
Starting from last stage, the effort delay per stage is
= gh = (3/3) (20/z)
By equating, 1.45 = 20/z
Then, z=14
Similarly, for third stage, the effort delay per stage is
= gh = (4/3) (z/y).
By equating, 1.45 = (4/3) (14/y). Then, y=13
Similarly, for second stage, the effort delay per stage is
= gh = (5/3) (y/x).
By equating, 1.45 = (5/3) (13/x). Then, x=15
Number of
Stages

Designers often need to choose the fastest circuit topology and gate sizes for
a particular logic function and to estimate the delay of the design.
As has been stated, simulation or timing analysis are poor tools for this task
because they only determine how fast a particular implementation will
operate, not whether the implementation can be modified for better results
and if so, what to change.
Based on the linear delay model, it allows the designer to quickly estimate
the best number of stages for a path, the minimum possible delay for the
given topology, and the gate sizes that achieve this delay. The techniques of
Logical Effort will be revisited throughout this text to understand the delay
of many types of circuits.
Number of Stages
Number of Stages
Number of Stages
Number of Stages
Number of Stages
Number of Stages
Number of Stages
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power