VLSI Design

MODULE 2-Delay
Delay
Definitions
 Propagation delay time, tpd = maximum time from
the input crossing 50% to the output crossing 50%
(WORST CASE DELAY)
 Contamination delay time, tcd = minimum time from
the input crossing 50% to the output crossing 50%
(BEST CASE DELAY)
 Rise time, tr = time for a waveform to rise from 20%
to 80% of its steady-state value
 Fall time, tf = time for a waveform to fall from 80% to
20% of its steady-state value
 Edge rate, trf = (tr + tf )/2
Definitions
 When an input changes, the output will retain its old value for at
least the contamination delay and take on its new value in at
most the propagation delay.
 Delays for the output rising, tpdr /tcdr

 Delays for the output falling, tpdf /tcdf

 Propagation and contamination delay times are also called max-

time and min-time, respectively.
 Propagation delay is often called as delay.

 The gate that charges or discharges a node is called the driver

 the gates and wire being driven are called the load.
Definitions
 The timing analyzer computes the arrival times at
each node and checks that the outputs arrive by their
required time.

 The slack is the difference between the required and

arrival times.

 Positive slack means that the circuit meets timing.

 Negative slack means that the circuit is not fast

enough.
Definitions
 The Nodes are annotated with arrival times.
 If the outputs are all required at 200 ps, the
circuit has 60 ps of Positive slack.
Timing Optimization
 Some logic paths are not critical in the system when
it comes to speed.

 Critical paths limit the operating speed of the system

and require attention to timing details.

 The critical paths can be affected at four main levels:

 The architectural/ microarchitectural level
 The logic level
 The circuit level
 The layout level
Timing Optimization
The architectural/microarchitectural level
 The most control is achieved with a good microarchitecture.

 This requires a broad knowledge of both the algorithms that

implement the function and the technology being targeted.
 how many gate delays fit in a clock cycle
 how quickly addition occurs
 how fast memories are accessed
 how long signals take to propagate along a wire.

 Trade-offs at the microarchitectural level include

 the number of pipeline stages
 the number of execution units (parallelism)
 the size of memories.
Timing Optimization
The logic level
 Trade-offs at this level include
 types of functional blocks (e.g., ripple carry vs. lookahead adders)
 the number of stages of gates in the clock cycle number of
stages in a clock cycle refers to how many sequential operations are
performed in one clock cycle.
 the fan-in and fan-out of the gates Fan-in refers to the number of
inputs a gate can accept, and fan-out refers to the number of outputs it can
drive.

 The transformation from function to gates and registers ( This

refers to the process of converting a high-level functional description of a circuit
into the actual logic gates and registers that implement that functionality. ) can
be done
 by experience
 by experimentation
 by logic synthesis.

 Even with skillful logic design and timing optimization, the

underlying microarchitecture of the circuit plays a crucial role. If
Timing Optimization
The circuit level
 Once the logical elements and gates in the circuit has
been selected.
 The Designer can further tune the delay by adjusting the
sizes of the transistors within those gates or by selecting
different styles of CMOS (Complementary Metal-Oxide-
Semiconductor) logic.

 Transistor sizing and logic style choices can affect the speed
and power consumption of the circuit.

 For example, larger transistors can speed up the circuit but

may consume more power.
Timing Optimization
The layout level
 The layout of the digital circuit on the physical silicon
(usually referred to as the "floorplan") is of critical
importance.
 The way components are arranged in the floorplan directly
impacts the lengths of wires that need to be used to connect
different parts of the circuit.
 Wire lengths can significantly affect the delay in the circuit

 Parasitic capacitance refers to the unintended

capacitance that exists between wires, components,
or other conductive elements on the chip.
 It can have a negative impact on signal speed and power
consumption.
Timing Optimization- Challenges
 Many RTL designers never venture below the
microarchitectural level.
 RTL is higher level of abstraction
 Microarchitecture is at lower level of abstraction

 A common design practice is to write RTL code,

synthesize it and check if the results are fast enough.
 Synthesis is the process of converting RTL code into a gate-level
representation of the circuit.

 If they are not, the designer recodes the RTL with

more parallelism or pipelining, or changes the
algorithm and repeats until the timing constraints are
satisfied.
Timing Optimization- Challenges
 Timing analyzers are tools used to check whether the circuit
meets all the specified timing constraints.
 Timing constraints define the maximum allowed delay for various
paths within the circuit.
 Achieving "timing closure" means that the design meets all these
constraints.
 If timing closure is not achieved, it may lead to timing violations and
signal integrity issues.

 Some designers may not have a deep understanding of the

lower levels of abstraction where the synthesizer operates.
 This lack of understanding can make it difficult for designers to
troubleshoot and address timing issues and achieve Timing
Closures, especially in complex or challenging systems.
Transient Response
 The most fundamental way to compute delay is to
develop a physical model of the circuit of interest.

 Write a differential equation describing the output

voltage as a function of input voltage and time, and
solve the equation.

 The solution of the differential equation is called the

transient response.

 The delay is defined as the time it takes for the output

voltage to reach half of the supply voltage (VDD/2).
 Transient Response
 The differential equation is based on charging or discharging of the
capacitances in the circuit.

 The circuit takes time to switch because the capacitance cannot change its
voltage instantaneously.

 If capacitance C is charged with a current I, the voltage on the capacitor

varies as:

 It shows that the current flowing into the capacitance is directly proportional to
the rate of change of voltage.

 Capacitances in the circuit store and release charge, and it takes time for
them to charge or discharge, leading to the delay in signal propagation.
Transient Response
 Every real circuit has some capacitance.

 In an integrated circuit, it typically consists of the gate

capacitance (Cgs) of the load along with the diffusion
capacitance (Csb and Cdb) of the driver’s own transistors.
 The transistor current depends on the input (gate) and output
(source/drain) voltages.
Transient Response
Transient Response
 There are diffusion capacitances between the drain
and body of each transistor and between the source
and body of each transistor: Cdb and Csb .

 The source-to-body capacitors Csbn1 and Csbp1

have both terminals tied to constant voltages and
thus do not contribute to the switching capacitance.

 The gate capacitance of the transistors in X1 and the

diffusion capacitance of the transistors in X2 do not
matter because they do not connect to node B.
Transient Response
 Shows the equivalent circuit diagram in which all the capacitances
are lumped into a single Cout.
RC Delay Model
RC Delay Model
Equivalent RC Circuits
Equivalent RC Circuits
3 Input NAND Gate
Equivalent RC Circuits
3 Input NAND Gate
Equivalent RC Circuits
3 Input NAND Gate
Equivalent RC Circuits
3 Input NAND Gate
 Elmore Delay
 Most circuits of interest can be represented as an RC tree

 The root of the tree is the voltage source and the leaves
are the capacitors at the ends of the branches.

 The pullup or pulldown network is modeled as RC Ladder.

 Elmore Delay- Example
 Compute the Elmore delay for Vout in the 2nd order RC
system from Figure.

tpd = R1C1 + (R1 + R2)C2

Linear Delay Model
 the normalized delay of a gate can be expressed in
units of as

Where, p is the parasitic delay inherent to the gate when no load

is attached.
f is the effort delay or stage effort that depends on the
complexity and fanout of the gate
Logic Effort of
inverter is 1

Where, The complexity is represented by the logical effort, g

A gate driving h identical copies of itself is said to have a
fanout or electrical effort of h.
Linear Delay Model
 Fanout is the ratio of the output capacitance
of the logic gate to the input capacitance of
the gate.

Where, Cout is the capacitance of the external load being driven

Cin is the input capacitance of the gate
Logical Effort
 Logical effort of a gate is defined as the ratio of the
input capacitance of the gate to the input capacitance
of an inverter that can deliver the same output
current.

 The inverter presents 3 units of input capacitance on

the input, so the logical effort is 3/3.

 The NAND presents five units of capacitance on each

input, so the logical effort is 5/3.

 The NOR presents seven units of capacitance, so the

logical effort is 7/3.
Logical Effort
Logical Effort
Logical Effort
Logical Effort
 Logical effort of common gates is shown in the table
below,

 The Logical effort tends to increase with the increase in

the number of inputs.

 NAND gates are better than NOR gates because the

series transistor are nMOS rather than pMOS.
Parasitic Delay
 The parasitic delay of a gate is the delay of
the gate when it drives zero load.

 It can be estimated with RC delay models.

 The normalized parasitic delay pinv

 pinv is the ratio of diffusion capacitance to gate

capacitance of the Inverter.
 Parasitic Delay
Parasitic delay of common gates

• The 3-input NAND and NOR each have 9 units of

diffusion capacitance on the output, so the parasitic
delay is three times as great (3pinv, or simply 3)
Delay in a Logic Gate
 Use the linear delay model to estimate the
delay of the fanout-of-4 (FO4) inverter,
Assume the inverter is constructed in a 65 nm
process with = 3 ps.
Delay in a Logic Gate
 The logical effort of the inverter is g= 3/3= 1, by
definition.
 The electrical effort is 4 because the load is four
gates of equal size.
 The parasitic delay of an inverter is pinv = 3/3= 1.

 The total delay is

d = gh + p
d = 1 × 4 + 1 = 5, in normalized terms,
tpd = 15 ps, in absolute terms.
Logical Effort of Paths
 Based on the linear delay model, it
allows the designer to quickly
 Estimate the best number of stages for a path

 The minimum possible delay for the given

topology

 The gate sizes that achieve this delay.

Delay in Multistage Logic Networks
Without Branching

 Shows the logical and electrical efforts of

each stage in a multistage path as a function
of the sizes of each stage.

 Logical effort is independent of size.

 While electrical effort depends on sizes.

 Delay in Multistage Logic Networks
Without Branching

 The path logical effort G can be expressed as the

products of the logical efforts of each stage along
the path.

 The path electrical effort H can be given as the

ratio of the output capacitance the path must drive
divided by the input capacitance presented by the
path.
Delay in Multistage Logic Networks
Without Branching

 The path effort F is the product of the stage efforts

of each stage.
 Introduction
 Digital logic is divided into combinational and sequential
circuits.

 Combinational circuits are those whose outputs depend

only on the present inputs

 Sequential circuits have memory.

 The building blocks for combinational circuits are logic

gates
 The building blocks for sequential circuits are registers
and latches.
Introduction
 The vast majority of circuits use static CMOS because it
is robust, fast, energy-efficient, and easy to design.

 Certain circuits have particularly stringent speed,

power, or density restrictions that force another
solution.

 Such alternative CMOS logic configurations are called

circuit families.
 Circuit families
 Static CMOS logic is particularly popular because of its
robustness.
 Given the correct inputs, it will eventually produce the
correct output so long as there were no errors in logic
design or manufacturing.
 Static CMOS circuits with complementary nMOS
pulldown and pMOS pullup networks are used for the
vast majority of logic gates in integrated circuits.

 They have good noise margins, and are fast, low power,
insensitive to device variations, easy to design, widely
supported by CAD tools, and readily available in
standard cell libraries.
Static CMOS
 Designer must learn to use NAND and NOR
instead of AND and OR Gates to take
advantage of static CMOS.

 This is often done through bubble pushing in

manual circuit design.

 Compound gates are particularly useful to

perform complex functions with relatively low
logical efforts.
 Bubble Pushing
 CMOS stages are naturally inverting

 So, AND and OR functions must be built from

NAND and NOR gates.

 DeMorgan’s law helps with this conversion:

 Design a circuit to compute F = AB + CD
using NANDs and NORs.
The circuit consists of two The ANDs and ORs are converted to basic
ANDs and an OR CMOS stages.

Bubble pushing is used to simplify the logic to three NANDs.

The function F = AB + CD
AND-ORINVERT- 22 (AOI22) gate and an inverter
Logical effort of Unit Inverter
Logical effort of Compound Gates
Logical effort of Compound Gates
Logical effort of Compound Gates
 Ratioed Circuits
 Ratioed circuits depend on the proper size or resistance of devices for
correct operation.
 The ratioed gate consists of an nMOS pulldown network and some pullup
device called the static load.
 When the pulldown network is OFF, the static load pulls the output to 1.
 When the pulldown network turns ON, it fights the static load. The static
load must be weak enough that the output pulls down to an acceptable 0.
 pseudo-nMOS inverter
 Instead, the static load is built
from a single pMOS transistor
that has its gate grounded so it is
always ON.