MANIPAL SCHOOL OF INFORMATION SCIENCES

(A Constituent unit of MAHE, Manipal)

Design of AXI to APB Bridge using System Verilog

Reg. Number Name Branch
220138015 Susmit P Rajeev M.E. VLSI Design
221038019 M V R Kasyap M.E. VLSI Design

Under the guidance of

Dr. Prashanth Kumar Shetty

Associate Professor
Manipal School of Information Sciences,
MAHE, MANIPAL

1
 1 Contents
1 Introduction ........................................................................................................................ 6
2 Objectives .......................................................................................................................... 7
3 Architecture........................................................................................................................ 8
3.1 AMBA AXI Protocol: ................................................................................................. 8
3.2 AMBA APB Protocol ............................................................................................... 14
4 Block diagram .................................................................................................................. 18
5 Methodology .................................................................................................................... 19
6 Results .............................................................................................................................. 22
7 Conclusion ....................................................................................................................... 23
8 Future scope of the work.................................................................................................. 24
9 References ........................................................................................................................ 25

2
 LIST OF FIGURES
Figure 1 Read operation in the AXI bus .............................................................................. 14
Figure 2 Write operation in the AXI bus ............................................................................. 14
Figure 3 State diagram of APB for both read and write operation .................................. 16
Figure 4 Block diagram of AXI to APB bridge ................................................................... 18
Figure 5 Internal architecture of AXI to APB Bridge ........................................................ 18
Figure 6 Pin description of AXI to APB bridge .................................................................. 18
Figure 7 State diagram of WRITE operation in the AXI to APB bridge ........................ 20
Figure 8 State diagram of READ operation in the AXI to APB bridge ........................... 21
Figure 9 Simulation part 1 .................................................................................................... 22
Figure 10 Simulation part 2 .................................................................................................. 22

3
 LIST OF TABLES

Table 1 States in write operation in AXI to APB bridge………………..20

Table 2 States in read operation in AXI to APB bridge…………...…… 21

4
 ABBREVIATIONS

AMBA Advanced Microcontroller Bus Architecture

OCB On-Chip Bus
AXI Advanced Xtensible Interface
APB Advanced Peripheral Bus

5
 1 Introduction
In recent years, due to the miniaturization of semiconductor chips, constant customization in
the design of chip is required. So, with increase in the complexity of the design, an efficient
method of communication between components in an SoC should be developed.
In a complex SoC, there are two types of buses for communication those are On-chip and Off-
chip buses. The On-Chip bus protocol is crucial out of them, as the chip performance mainly
depends on it. Of all OCBs existing in the market, the AMBA bus system is widely used as the
de facto standard SoC bus.
The AMBA protocol is an open standard, on-chip interconnect specification for the connection
and management of functional blocks in a System-on-Chip (SoC). It facilitates right-first-time
development of multiprocessor designs with large numbers of controllers and peripherals.

The AMBA 4.0 specification defines five buses/interfaces.

• Advanced eXtensible Interface (AXI)
• Advanced High-performance Bus (AHB)
• Advanced System Bus (ASB)
• Advanced Peripheral Bus (APB)
• Advanced Trace Bus (ATB)

Advanced Extensible Interface Bus (AXI): AXI, the next generation AMBA interface defined
in AMBA 4.0 specification is targeted at high performance, high clock frequency system design
and includes features which make it very suitable for high speed sub micro meter
interconnect.
Advanced Peripheral Bus (APB): The AMBA APB is for low-power peripherals. AMBA APB
is optimized for minimal power consumption and reduced interface complexity to support
peripheral functions. APB can be used in conjunction with either version of the system bus.

To establish a connection between multi-channel, high-frequency AXI bus and single-channel,

low frequency APB bus, a bridge is required for efficient transfer of data between these two
different buses.

6
 2 Objectives
• To design a fully functional and synthesizable AXI to APB bridge using System
Verilog.
• To verify the designed AXI to APB bridge using stimulus generated using testbench
environment.

7
 3 Architecture
3.1 AMBA AXI Protocol:

Advanced eXtensible Interface (AXI) , the third generation of AMBA interface defined in the
AMBA 4 specification, is targeted at high performance, high clock frequency system designs.

The objectives of the latest generation AMBA interface are to:

• be suitable for high-bandwidth and low-latency designs
• enable high-frequency operation without using complex bridges
• meet the interface requirements of a wide range of components
• be suitable for memory controllers with high initial access latency
• provide flexibility in the implementation of interconnect architectures
• be backward-compatible with existing AHB and APB interfaces.

The key features of the AXI protocol are:

• separate address/control and data phases
• support for unaligned data transfers using byte strobes
• burst-based transactions with only start address issued
• separate read and write data channels to enable low-cost Direct Memory Access (DMA)
• ability to issue multiple outstanding addresses
• out-of-order transaction completion
• easy addition of register stages to provide timing closure.
As well as the data transfer protocol, the AXI protocol includes optional extensions that cover
signalling for low-power operation.

The AXI protocol is burst-based and defines the following independent transaction channels:

• Read address
• Read data
• Write address
• Write data
• Write response

8
Each of the five independent channels consists of a set of information signals and uses a two-
way VALID and READY handshake mechanism. The information source uses the VALID
signal to show when valid data or control information is available on the channel. The
destination uses the READY signal to show when it can accept the data. Both the read data
channel and the write data channel also include a LAST signal to indicate when the transfer of
the final data item within a transaction takes place.
Read and write address channels - Read and write transactions each have their own address
channel. The appropriate address channel carries all of the required address and control
information for a transaction.
Read data channel - The read data channel conveys both the read data and any read response
information from the slave back to the master.
Write data channel - The write data channel conveys the write data from the master to the
slave.
Write response channel - The write response channel provides a way for the slave to respond
to write transactions. All write transactions use completion signalling. The completion signal
occurs once for each burst, not for each individual data transfer within the burst.

AMBA AXI Signals

Global signals:
SIGNAL NAME SOURCE DESCRIPTION
ACLK Clock source Global clock signal. All
signals are sampled on the
rising edge of the global
clock.

ARESETn Reset source Global reset signal. This

signal is active LOW

Write address channel signals :

SIGNAL NAME SOURCE DESCRIPTION

AWADDR Master Write address. The write address bus gives the
address of the first transfer in a write burst
transaction. The associated control signals are used
to determine the addresses of the remaining
transfers in the burst.
AWLEN Master Burst length. The burst length gives the exact
number of transfers in a burst. This information

9
 determines the number of data transfers associated
with the address.
AWBURST[1:0] Master Burst type. The burst type, coupled with the size
information, details how the address for each
transfer within the burst is calculated.
AWVALID Master Write address valid. This signal indicates that valid
write address and control information are available:
1 = address and control information available 0 =
address and control information not available. The
address and control information remain stable until
the address acknowledge signal, AWREADY, goes
HIGH.

AWREADY Slave Write address ready. This signal indicates that the
slave is ready to accept an address and associated
control signals: 1 = slave ready 0 = slave not ready.

Read address channel signals:

SIGNAL NAME SOURCE DESCRIPTION
ARADDR Master Read address. The read address
bus gives the initial address of a
read burst transaction. Only the
start address of the burst is
provided and the control signals
that are issued alongside the
address detail how the address
is calculated for the remaining
transfers in the burst
ARLEN Master Burst length. The burst length
gives the exact number of
transfers in a burst. This
information determines the
number of data transfers
associated with the address.
ARSIZE Master Burst size. This signal indicates
the size of each transfer in the
burst.
ARBURST Master Burst type. The burst type,
coupled with the size
information, details how the
address for each transfer within
the burst is calculated.
ARVALID Master Read address valid. This signal
indicates, when HIGH, that the

10
 read address and control
information is valid and will
remain stable until the address
acknowledge signal,
ARREADY, is high

ARREADY Slave Read address ready. This signal

indicates that the slave is ready
to accept an address and
associated control signals:
1 = slave ready
0 = slave not ready.

Write data channel signals:

SIGNAL NAME SOURCE DESCRIPTION
WDATA Master Write data. The write data bus
can be 8, 16, 32, 64, 128, 256,
512, or 1024 bits wide.

WSTRB Master Write strobes. This signal

indicates which byte lanes to
update in memory. There is one
write strobe for each eight bits
of the write data bus. Therefore,
WSTRB[n] corresponds to
WDATA[(8 × n) + 7:(8 × n)].
WVALID Master Write valid. This signal
indicates that valid write data
and strobes are available: 1 =
write data and strobes available
0 = write data and strobes not
available.

WREADY Slave Write ready. This signal

indicates that the slave can
accept the write data: 1 = slave
ready 0 = slave not ready.

Read data channel signals:

SIGNAL NAME SOURCE DESCRIPTION
RDATA Slave Read data. The read data bus
can be 8, 16, 32, 64, 128, 256,
512, or 1024 bits wide
RRESP Slave Read response. This signal
indicates the status of the read

11
 transfer. The allowable
responses are OKAY,
EXOKAY, SLVERR, and
DECERR

RVALID Slave Read valid. This signal

indicates that the required read
data is available and the read
transfer can complete: 1 = read
data available 0 = read data not
available
RREADY Master Read ready. This signal
indicates that the master can
accept the read data and
response information:
1= master ready
0 = master not ready

Write Response channel signals:

SIGNAL NAME SOURCE DESCRIPTION
BRESP Slave Write response. This signal
indicates the status of the write
transaction. The allowable
responses are OKAY,
EXOKAY, SLVERR, and
DECERR
BVALID Slave Write response valid. This
signal indicates that a valid
write response is available:
1 = write response available
0 = write response not
available
BREADY Master Response ready. This signal
indicates that the master can
accept the response
information.
1 = master ready
0 = master not ready

Write address channel

The master can assert the AWVALID signal only when it drives valid address and control
information. It must remain asserted until the slave accepts the address and control
information and asserts the associated AWREADY signal. The default value of AWREADY

12
can be either HIGH or LOW. The recommended default value is HIGH, although if
AWREADY is HIGH then the slave must be able to accept any valid address that is presented
to it. A default AWREADY value of LOW is possible but not recommended, because it
implies that the transfer takes at least two cycles, one to assert AWVALID and another to
assert AWREADY.
Write data channel
During a write burst, the master can assert the WVALID signal only when it drives valid
write data. WVALID must remain asserted until the slave accepts the write data and asserts
the WREADY signal. The default value of WREADY can be HIGH, but only if the slave can
always accept write data in a single cycle. The master must assert the WLAST signal when it
drives the final write transfer in the burst. When WVALID is LOW, the WSTRB[3:0] signals
can take any value, although it is recommended that they are either driven LOW or held at
their previous value.
Write response channel
The slave can assert the BVALID signal only when it drives a valid write response. BVALID
must remain asserted until the master accepts the write response and asserts BREADY. The
default value of BREADY can be HIGH, but only if the master can always accept a write
response in a single cycle.
Read address channel
The master can assert the ARVALID signal only when it drives valid address and control
information. It must remain asserted until the slave accepts the address and control
information and asserts the associated ARREADY signal. The default value of ARREADY
can be either HIGH or LOW. The recommended default value is HIGH, although if
ARREADY is HIGH then the slave must be able to accept any valid address that is presented
to it. A default ARREADY value of LOW is possible but not recommended, because it
implies that the transfer takes at least two cycles, one to assert ARVALID and another to
assert ARREADY.
Read data channel
The slave can assert the RVALID signal only when it drives valid read data. RVALID must
remain asserted until the master accepts the data and asserts the RREADY signal. Even if a
slave has only one source of read data, it must assert the RVALID signal only in response to
a request for the data. The master interface uses the RREADY signal to indicate that it
accepts the data. The default value of RREADY can be HIGH, but only if the master is able
to accept read data immediately, whenever it performs a read transaction. The slave must
assert the RLAST signal when it drives the final read transfer in the burst.

13
 Figure 1 Read operation in the
AXI bus

Figure 2 Write operation in the AXI bus

3.2 AMBA APB Protocol

The Advanced Peripheral Bus (APB) is part of the Advanced Microcontroller Bus Architecture
(AMBA) protocol family. It defines a low-cost interface that is optimized for minimal power
consumption and reduced interface complexity. The APB protocol is not pipelined, use it to
connect to low-bandwidth peripherals that do not require the high performance of the AXI
protocol. The APB protocol relates a signal transition to the rising edge of the clock, to simplify
the integration of APB peripherals into any design flow. Every transfer takes at least two cycles.
The APB can interface with:
• AMBA Advanced High-performance Bus (AHB)
• AMBA Advanced High-performance Bus Lite (AHB-Lite)
• AMBA Advanced Extensible Interface Lite (AXI4-Lite)
It can be used to access the programmable control registers of peripheral devices.It is
optimized for low power, reduced complexity interface and low bandwidth operations which
is unpipelined protocol. It is supported only for a single master and multiple slaves and contains
only a single channel to communicate between master and slave.

14
Signals in the APB bus

SIGNAL SOURCE DESCRIPTION

PCLK Clock source Clock. The rising
edge of PCLK times
all transfers on the
APB.

PRESETn System bus Reset. The APB reset signal is

equivalent active LOW. This signal is
normally connected directly to
the system bus reset signal.

PADDR APB bridge Address. This is the APB

address bus. It can be up to 32
bits wide and is driven by the
peripheral bus bridge unit

PSELx APB bridge Select. The APB bridge unit

generates this signal to each
peripheral bus slave. It indicates
that the slave device is selected
and that a data transfer is
required. There is a PSELx
signal for each slave

PENABLE APB bridge Enable. This signal indicates

the second and subsequent
cycles of an APB transfer.

PWRITE APB bridge Direction. This signal indicates

an APB write access when
HIGH and an APB read access
when LOW

PWDATA APB bridge Write data. This bus is driven

by the peripheral bus bridge
unit during write cycles when
PWRITE is HIGH. This bus
can be up to 32 bits wide.

PSTRB APB bridge Write strobes. This signal

indicates which byte lanes to
update during a write transfer.
There is one write strobe for
each eight bits of the write data
bus. Therefore, PSTRB[n]
corresponds to PWDATA[(8n
+ 7):(8n)]. Write strobes must
not be active during a read

15
 transfer.

PREADY Slave interface Ready. The slave

uses this signal to
extend an APB
transfer.

PRDATA Slave interface Read Data. The selected slave

drives this bus during read
cycles when PWRITE is LOW.
This bus can be up to 32-bits
wide

The communication by PSELx signal. PSELx signal is a master signal which is used
to decide the number of slaves are used, PWRITE is a signal from master which
decides Read or write operation if PWRITE =1, for write operation and 0 for Read
operation. For any operation PADDR, PWDATAwhich is an address and data signal
is set on the bus, PSEL is high, PENABLE is master is signal is high for the next
clock cycle, when PREADY which is from Slave is high indicating data transfer is
completed.
PSLVERR is a master signal indicates an error condition on Read and Write operations.
The read and write operations in the APB can be delayed using wait states. These wait states
are achieved by using PREADY signals.

Figure 3 State diagram of APB for both read and write operation

16
The state machine operates through the following states:
IDLE:
This is the default state of the APB.
SETUP:
When a transfer is required the bus moves into the SETUP state, where the appropriate select
signal, PSELx, is asserted. The bus only remains in the SETUP state for one clock cycle and
always moves to the ACCESS state on the next rising edge of the clock.
ACCESS:
The enable signal, PENABLE, is asserted in the ACCESS state. The address, write, select, and
write data signals must remain stable during the transition from the SETUP to ACCESS state.
Exit from the ACCESS state is controlled by the PREADY signal from the slave:
• If PREADY is held LOW by the slave then the peripheral bus remains in the ACCESS state.
• If PREADY is driven HIGH by the slave then the ACCESS state is exited and the bus returns
to the IDLE state if no more transfers are required.
Alternatively, the bus moves directly to the SETUP state if another transfer follows.

AXI to APB Bridge:

The APB bridge provides an interface between the high-performance AXI domain
and the low-power APB domain. It appears as a slave on AXI bus but as a master on APB
that can access up to sixteen slave peripherals. Read and write transfers on the AXI bus are
converted into corresponding transfers on the APB.
AXI supports Out of order processing and multiple outstanding operations, these
shows AXI as an efficient protocol. AXI operates at high speeds and APB consists of slow
devices. There should be FIFOs on the Bridge to store the data and addresses. AXI devices
can communicate among themselves and bridge, but APB devices cannot communicate
themselves. APB devices communicate with bridge only. The master always initiates the
transaction. At one time, a master could access only one slave. A slave can be connected to
one master at a time.
The AXI protocol is burst-based, and the master begins each burst by driving transfer
control information and the address of the first byte in the transfer. As the burst transaction
progresses, it is the responsibility of the slave to calculate the addresses of subsequent
transfers in the burst.

17
 4 Block diagram

Figure 4 Block diagram of AXI to APB bridge

Figure 5 Internal architecture of AXI to APB Bridge

Figure 6 Pin description of AXI to APB bridge

18
 5 Methodology

BEHAVIOURAL MODELLING OF AXI2APB:

The operation of bridge starts from idle state(S0) in which all the initial values of all the
control signals are assigned to initial state.
When either ARVALID or AWVALID is high, it indicates that the valid address for the data
is received and it goes to next state either write address received state(S1) or read address
received state (S6).
If both the ARVALID and AWVALID are high, give preference to read operation. If both the
ARVALID and AWVALID are low, remain in the same state(S0) and wait until either of the
address valid signals are high. The outputs of this state are ARREADY and AWREADY
(high).

WRITE OPERATION:
Write operation starts with write address received state(S1), when WVALID is high, it
indicates that the sent data is valid. Since the written data is valid, proceed to next state i.e.
write data received state (S2). Remain in the same state until WVALlD is made high. The
output of this state is WREADY (high).
There is no specific condition to be checked in the write data received state(S2), once the data
is received, next step is to send this data to APB. The outputs of this state are PWRITE and
PSEL (high).
This process is done in the next state where the enable signal of APB (S3) is checked, if the
enable signal of APB is high then APB will accept the data, even the PREADY signal should
be high, if both these signals are high. The data will be transferred hence the next state is data
transferred state(S4).
The outputs of this state are PWRITE, PSEL and PENABLE (high).
In this state (S4)- data transferred state, the flow comes to this state until there is some data to
be transferred. If the data to be sampled is not zero (sampled_wlen!=0) and WVALID is high,
it will again to S2(Write data received state) and in the same case of (sampled_wlen!=0) and
WVALID is low, it will remain in the same state until the WVALID is made high, so that the
write operation can resume.
If there is no data to be transferred i.e. (sampled_wlen==0) (all the data is written on APB),
go to next state i.e. transfer complete state(S5). The outputs of this state are WREADY,
PSEL,PWRITE (high).
In this state (S5), the write response channel signal BREADY is used to assert that the
operation is complete and the AXI bus is free for next transfer. So, if the BREADY is high,
go to the S0 (Idle state) and repeat the process again. If the BREADY is low, remain in the
same state until the BREADY is made high. The output of this state is BVALID (high).
This completes the write operation i.e. transfer of data from AXI to APB

19
 Figure 7 State diagram of WRITE operation in the AXI to APB bridge

STATE STATE DESCRIPTION

S0 Idle state
S1 Write address received state
S2 Write data received state
S3 Enable and PREADY check
S4 Data transferred state
S5 Transfer complete state

Table 1 – States in write operation in AXI to APB bridge

READ OPERATION:
Read operation starts with read address received state(S6), here in case of read operation the
address that is received need not be checked if the address is valid or not because, this
address was verified during write operation of AXI. Even the APB doesn’t support RVALID
signal. The output of this state is PSEL (high).
There is no specific condition to be checked in the read address received state(S6), once the
address is received, next step is to send this data to AXI.
In this new state (S7), first the PREADY signal is checked, if it is high, it indicates that data
is transferred hence the next state is read data transferred state (S8).The outputs of this state
are PSEL and PENABLE (high).

The next state (S8) is read data transferred state, in this state the RREADY and sampled_rlen
is checked, if sampled_rlen is not zero and RREADY is high, it indicates that there is some

20
data to be read, hence got to read address received state(S6) again. If RREADY is low,
remain in the same state until the RREADY is asserted high. If the sampled_rlen is zero, it
indicates that there is no data to be read. All the data has been transferred from the APB bus
to AXI bus. The state output is RVALID (high).
The sampled_rlen will be same as sampled_wlen as the length of write data and read data will
be same.
This completes the write operation i.e., transfer of data from AXI to APB.

Figure 8 State diagram of READ operation in the AXI to APB bridge

STATE STATE DESCRIPTION

S0 Idle state
S6 Read address received state
S7 Enable and PREADY check state
S8 Read data transferred state

Table 2 - States in read operation in the AXI to APB bridge

21
 6 Results

Figure 9 Simulation part 1

Figure 10 Simulation part 2

22
 7 Conclusion
• The design of AXI to APB bridge was done using behavioural modelling.
• In case of write operation, the data was transferred from AXI to APB based on the
signal address write valid , data write valid.
• In case of read operation, the data was transferred from APB to AXI based on the
signals address read valid , enable signal.
• The important control signals to transfer data from either bus are PREADY ,
PENABLE, PSEL .
• The design and simulation of the bridge was done using Cadence software .
• The functionality of the bridge was verified using testbench with directed stimulus as
test vectors.

23
 8 Future scope of the work
The design of AXI to APB bridge was done using behavioural modelling based on the data
transfer between AXI and APB buses. This was done for both read and write operations.
For efficient synchronization of clock frequency between AXI and APB, the data that is
received need to be stored in memory. Hence further improvement in the bridge can be done
by implementing this design in FIFOs.

24
9 References
[1] DESGIN AND VERIFICATION OF AXI APB BRIDGE USING SYSTEM VERILOG
G.R.K.Prasad1 , Damarla Paradhasaradhi1 , G. Madan Sankar Reddy2 ,K.Srinivasa Rao3
Jour of Adv Research in Dynamical & Control Systems, Vol. 10, 06-Special Issue, 2018
[2] Design and Verification of APB Bridge Based on AMBA 4.0 G.SREENIVASULU1 ,
M.SANTOSH KRISHNA2
ISSN 2319-8885 Vol.04,Issue.57, December-2015
[3] https://developer.arm.com/documentation/ihi0022/hc/?lang=en
[4] https://developer.arm.com/documentation/ihi0024/latest/

25