cMOS Logic

4.4.7 Zipper . 1'd nticaJ to NORA CMOS except the clock sign J
Zipper CMOS is . e the generation of different clock si0na1 aJs. Th~ .
• 1 k requires . . o- • s fo ~tn.. ,
cMOS c oc transistors. General rucwt structure of zipper r '
and for pull down shown in Fig. 4.4.10. C~Os . -~
and dock signals are Cl?C\tit

Voo Voo Voo

"'1

pMOS nMOS
nMOS Logic
Logic Logic

(a) Zipper CMOS structure

4'
Voo ------
Voo - I Vr,p 1------iv;----- ~-----------
o---

:~ ====== -t-----:3---- -I
4'
i-----------l
(b) Clock signals for zipper CMOS

Fig. 4.4.10 Zipper CMOS circuit and clock signals

 "
1
0 .-t vo,d e"'t~~h~lv tl"rt-- dt11Q~
I•-;1>riving
I Large Capacitance loadl EW'l•Jl•E f.fMiMG
f 111115 of drMn9 large capacitive loada
driving large ca ·· ~.,
"f", for . paa.tive loads, inverters should pre!a{'nt tow pull (11,w n ,.,,.,
pull-up resistances. This, in turn means that MOS devices must be des!8ffed
W ratios to have low resistance values fo r Zp. • and Zp.a.· For this,
with low L : st
channels mu be made very wide to reduce resistance 11
valu<' which In
consequence makes the inverter occupy a larger area.
Another limitation on L ·is that it cannot be reduced below the minimum
' feature size which makes L : W ratio large. Hence the gate region area L x W
t,ecomes significant and a comparati~ely large capacitance is presented at the
jnput.
iflput. This in tum increases time required for transitions of voltages at the
cad•d lnvert.r
,; This situation Wt be improved· by U!llng N ea11eaded inverters, Ndt one ol
' which lR larger than the stage that It follows by a width factor r as shown ln
Fig, U.6 whl!N nMOS invt1Wl'l 1l'Q tlqn ill Ill l!Xllfflple,
 4-46
----=--------------------
VLSI Design
Gate l
t)ll~;_

!
::+:: CL

fig. 4.6.6 Driving large capacitance loads

'
GNo

• The capacitive load presented at the inverter input increases in

0
the increasing width factor and hence the area occupied also . Pr Porij0
same time the rate .at which the width increases (decided b Increases. Atn to
' . Y Valu th
influence the number N of stages reqwred to be cascaded to dri e of r) e
. '~
value of CL. Thus an optimwn number _of stages should be 'd a Pattiri,i I
. h . th i eni;" -""~
following procedure expIams ow to,,arnve at e optimum numb ' J..1 1ecl.. h
,.......--------. .. er of st (l\e
• Let t\ V:-n indicate a logic O to 1 transition and VV;n indicate a Io · ages.
1
1
transition of input voltage ½n. Then as per our earlier diseuss1on . 8Ic d to o
stage is rt for 6. V;n and 4 rt for VV;n, for the 4 : 1 nMOS inverter. lien
' elay Per
delay per nMOS pair is Srt. ce total
Similarly, delay per CMOS pair comes out to 7 rt. We define a variable

I x= ~=rN I ... (4.6.3)

So that the choice of N and rare interdependent r is called width facto r.

• To determine the value of r which will minimize the overall delay for a .
value of x. given

From equation 4.6.3

In(x) = N In (r)
N = In (x)
or
In (r)

Hence for N even,

N
Total delay z srr = 2.5N rr(nMOS)
2
N
or z 7 rr =3.5N rr(CMOS)
2
Thus the delay is directly proportional to N r t in all the cases, i.e.

delay oc N rt = ln(x) r 't

ln(r)
 l
;;;r"
r,oe si9 11 4 -47
Gate Level Design
1>1 / ,is is a ease of minimization of delay with r a s a parameter. Mathematically
• fl
1•t can be shown that total delay, td, · is minimized for r = e (base of n a tural
arithms). Thus the cha1u1.el of each in v e r ter st age s h o uld be approximately
times ,vider than the stage it follows, both for nMOS as w ell as CMOS
inverters. If r is set equal to e, N = ln ( x) and
fof r,J even t d "= 2.5 eN 1: (n!v10S)
- 3.5 eN T (nMOS)
tot N odd td = [2 .5 s. : · -1) +l] e't (nMOS)
= [3.5 (I' 1 -1) + 2] e 1: (CMOS)
} for V in
afld td =
=
[2.5 (N -1) +4] e-r .
[3.5 (N -1) + 5] e 1:
(nMOS)
(CMOS) 1 for V V in
4.6.4 Super Buffers ii f m . !f_.£ &'. &W-AC?& l!L W
 .. . q
v1.•r ,,_.,,,,.
formance of a bipo\
• Now, -. 1,L. - v8,,, d:~lln g the ,effective. v s, incre,, ~
c,,,_"
l..,.
,t/_ ,.. J""gh' wUh "'- h•lp ••• :.., ...,._, . .....~
,w- \\
redu ces the delay in crn,rgfn g at t h e Joad • SC.. tt..,
; m ore t1ynunrlrical trartsltlans. Cllpaata.r,ee Of 1. f/, l~:~ ~~""1.!~~t ·" ~ t>I\ .
-,.~
to
°"~~ -~ t,e
.'
6
A n a n •i n vertinS nM~ s u per b uffer
. .
ctrcu,. t . R ¾ \ ~,-.:~"~ \"<l,i
i
18
Fun ctioning a f which is Jeft to the reader to nd giv 'h.
efkctivenet1s af t1u per bu.Her d esj,gns, w e no~ eJ'Stanct . O i " - ~ ' - •·
th
5 µ m tec1tnal agy a re capable af driving capaci
5 n se<:-
at the s
l:ance o f 2 ;:;:<::tu_~
...l"i.g,
'tr\ ~¼~_
Vin
- - -, - - - - -~ VQDOQ_ \.vj ~
a
~
---¾;,
-
ti ~ .
~ .
'
'lf Fig. 4.6.9 Driving abi1~ of b\~--- v~ \
v.,.,, t,. t re
q uired to <:rull'\ge the ou..._
.
·, "-"•~~
"olta.ge \r
-~
•t-\lt
v,n ti'1'e ltage V;,, is • 111 by
" iJ'lf'tlt _ CL -....,\ ~ \
' tl'e t!,.t - gm
- - -- - - - - - ---GNO
Fig. 4.6.B Non-Inverting type nMOS suPer bu . the load capacitance and
ffer 1s g.,, the t-.._
,4.6.5 BIC/1110S Drivers . . • ,,. . efe Ci --18Cond~
• Since the BiCMOS technolo~ is e~ched With bi o . , I' of· t is small because the tr <:.e c,\ th~ ,
converu
·ent to use bipolar transistor drivers as the outpp lar tra .... _.
di . ut st ~"'!St
. i ioe of !:..
. r. "a
<ll\sconduct"'-
~•ce of th
bl'l'<:l\at
logic gate circuits. As a~ eady scussed, bipolar transisto age of . Ots, i j!te )ligPer, . e bi\)l)\ai:
characteristics especially the transconductance g and rs ~"e i"etter t is f-,~1 detailed analysis of the delay du \t<ll\sistot is
-'--~acteristics, as compared to those of MOS tr~ist the CUrre cit" su.h AJl'lorede up due to two main compon e to the bipolaJ: tr
uuu, , rugh t dri ors. By llt/itt t'el"i0t , . JPa char th b ents Viz T <lrlsisto
BiCMOS devices have curren ve capabilities ins . "irtu.e ei\ l; jt iS • ed to first ge e ase emitter jun . in and Tl-~ _t t~l!a\s that
smaller areas in silicon. . Ptte of ;:f
t1ies; re~iti1'. e is typically 2 ns for the BiCMOS Ctio~ of the bipolaJ: ,lixnei"' is that j •
\\
• • Cu.p . ' 'flli5 tilll tran.s\Stor-b ,n~)
• In the bipolar transistors, there is an exponential depend Yiiig ter part to this for the CMOS dri . ased dn~er. \ot.
J the base to emitter (" ence of ,..,.e coun ver 1s th •
(output) current c on . input) voltage V the cou , w ate capacitance and is of the orde f e titne t
bipolar transistors can be op~rated_ with much smaller input be- lieii.c t!ct0i- itll'ut dg 50-100 ps. Thus the T- for ~- o l ns. Tin in case of Go chat?e the
than MOS transistors and still switch larger currents Thi Voltage e the aroun rn 1polar transistors . aJ\s dnve1 is
15
~.4;,,,rmance is offset by the fact that a small amount ~f chas better sw~\\rhigs , mparison.
0 \he ni'6hest in
w •rge i itch;:· . th tim .
be moved during switching. s reqUired"'ig 'fhe tiJne TL is e e reqUU'ed to charge the outn t l
. . to l ) (1 / h ) C Thi . 't'u oad ca:pacitan C.
• Another consideration in bipolar devices lS that of the tem quals (V I Id fe L· s 1s less for the bipolar dri ce L l\l\d.
perature effect
input voltage V~. However, h ere too, one properIy that comest es cornpared t o MOS drivers. The parameter hf, is thever by . a factor oi hf•
O
that although V/Jc is logarithmically dependent on collector
several other parameters su ch as a..---
width, d oping level, electro
advanta1ta
CUrrent /c.,,.,llldia
atransistor. Thus TL for the bipolar transistor is 1:ss Thi gam oi \he bi.\lo\ar
higher value of T in. · 5 compensates for \he
_is aimply linHl'ly dependent on temperature. n ltlobillty, it A--other signifi'cant aspect while considering delay is the co\l.,,,. .
• ~ow the t.mp«•ture dlm:rencea acrou an ,. are not very high. Thua th
U- 1:c I l'U' • , . .l~,Ot teS\Stance
Re through which the charging ~ent tor CL flows. Hence a \\l.gh value of
valu• of the, bipolar dovlC'C!t 1prNd ovor the chJp l'QfflAin match..,,. e V;, R results into a longer propagation delay. The effect of value ot Re <m the
· · V\il Ind do C • • ,
dlHw by mortt tMn • lrN·,mmVm- " " -•
t3. not delay can be understood from F1g. 4.6.\0 which ahowa tn,ial,GIiiy ma at
\
>
 4
.
,
7 VLSI ·Ooelgn 4 -50
Gate l e.,,,
tw o va lu es of C b as a function of R e . The use of the
as lo buried----...:.:.____
~l~-
(BCCD) region in BiCMOS fabrication is to keep Re w as sllb
Possib c:ou
l~. "'"'''llr
1500 CL== 1 pF
en
.S 1000
>-
co
cv
D
CL==0.1pF
ol 1 1 1 1 1
200 400 600 800 1000 •
Collector resistance (Q)
Fig. 4.6.10 Gate delay as a function of collector resistance
• All these required features
.
discussed
. .
above are incorporated int0 the bi
devices under the B1CMOS fabrication process. The devices thus have hipolar h
high 11 -, and low Re . The . presence of s uch pffi·c·
;e
high g
. ,,, , • . 1ent ga ~,d
1c -
advantageous d evices on chip o ffers a grea t d c.1 1 of scope ~nd freedom to
VLSI d esigner .
 -------4-s~
4 •52
I
VLSI 0t1lgn acitance
,caP
riff \ capacitance
ll'era
ad0with Long Polysillcon Wire \ •.~, 1f"''
,ii) ,1111 to Fringing
. . ~\e\d1.
/p I<"
0
[)elay AsaOCllt , •~ ""'"'"'"· long P<>ly,iij"' ,... frinll"'& lields .• fu .....
4,6.7 , ," the ~ • PC .,,ltiog ;,ro Oowmg do"" <>I U. .. •I,, ,11,1 plat, cap"'""-·11. I> '
• s,,,,,l1,,tol ,.,;,, R:: wHh w;., ;, diffu,;o0 wh,~ the ,,,"1.'1\. I ' d • fr component of U. "''"11
01
¾... •
I,
•
O
. ,!so ""°'.' .
e<0mmeoded oot to h»es;g,,._ ,. %<>1 1 ¾,.'I ~,ti .,.1° , ;, U\ the ..,_ I ~ • I, i,.,' 1',
el!,<t •
""' hlgh<'r, H,ore
ver relatJvely
"r
. er,t d;,,.,...
. ls running over long polys11icon \\>i.
l ,......-
,""""g i,, '\,."I, ' r I O ""atton be ctllll\>~abt, "'"rn,<>I 1o,
, ' Ii,,,,,_,,
/ ; ••f\ce t'l\ ..:on of CIICUJ.t \)erfor,,..~ lht
• '"\",
Ill
...,
•Y , . ,, ..
o, ,
-
, Ioog .. . ,.
• cl buffers fur •.gospeeds
a up oigo,l propagaho0 "Id ... -., , "¾
Us d'tions because ,1 oduction of delays in signa1 Propa1> . t~ll. I~ ' c'-,~tt•' Wbe l
('
,.,e ,ial,au,ken into ""5iderat;,,_ ¾. •· ' ,
.•.,,,.
"'i ¾ ..._, '-_ ' ' I,
ron ·t,' 'vity to no,·,.· Iorrt noise This 1s. illustrated
signal more su .,.,
' • mthe •
.
th '

. Fig.
m . 4 .,aij°" ~c•
61
.gnal ' at the U\f'Ut of the """"' "< , , •,,
"- ·•
''""i
......
11.
\
•;·,
•'
"
\
\
....,_.
."
...,.ii,,._
"""-' \t•\ ._
...
• The slow rise tin1Ion pclysil"°". lioe """' _' "'Put >oltag, /• ..... Cff = '•' StO, I -,....___,,
drelali,ely
romrn long,r · m • ""':the.,,_
.t g from a g . th viaruty of Vin· This may allow Slh,11 'lvtQ
swihl, .ih state 1retw.,. ,0~,
-""' , · • • 1+
~~g:,
~h,~\, , 2d
~, (
I l+d'~\
I '
t
ho noise to mak . ollll Hence ti • -.y lo dtiv, I, 1 "'1 Io. \ ·)\
ue tpomt p · . vl\g p ()<~O . . .
own at the ou t avoids the effects of noise anct to spl>A,.) 0lysili ess of wue lmetallizatiO!\) l is ,.,;. la..~,
ass . buffee o Itµ -, •c1<o • , ' ""'...,,.
wfres by sudabl~ sign,! edges. I,'\, l tbi ,-ie.1otal vm, ....... "1 I \ '
time o1 propaga
lo lo t2 /#a¢ Cw = cff +c..,
\l~
I I
I
f
I I I
f'•
I I I
I
-
capacitances
I ~ : I •
1eoayer . .
iIO
I
R: r capaotances are unavoi.dable tO
r11 terlaye
I
R 1R .oceur
· , \!I .deration of the same has certain as-pects
co!ISlcitance between metal and po\ysilicon is :~ to \a!oUt. rill~~.~
I I Long polysilicon wire

,apa b trate.
al'd Sil s
t.1owe,
1
.,er it occurs only where layers ,-,.
I

gher than \hat\..._ ~\e,

-.v~ or when

"'I'll~ tne\al
, 1 ther. Thus interlayer capacitances are layout~ one \a1ei
Nolt : V1nv • Inverter thrnhold al'o ..,_,1 f d dil ~ent. iven ••-
..,,..\y accounttu or an tea y calculated for '°"'''·· •~,
ptOF· "fl\1111{ ~ .
Fig. 4.6.12 Possible effects of delays in long polyslllcon wires peripl19'11 Capacitance
\
,@Wiring Capacitance DiW:fDI.~ ,r1, source and drain terminals of n and pchannel devices '--'
g Apart horn the area capacitances associated with the lay,::::
. 'flcant sources. of capacitance are
from gate to channeI, other s1gn1 ate and

, 11,e • • are ,u1~ b n+

d p+ diffusions respectively. These form diodes wilh lhe !ubs\tate1r
:{fusion regions, each diode so formed has associated wilh \\ a \)er\~~:
side wa\\ capacitance. lts order is typically afew picofarads \)et uni\\•
encountered which contribute to the overall wiring capacitance. These canal~o
classified as : e The overall side wall capacitance may be conslderab\y gm\tt than !rt 11ea
i) Capacitance due to fringing fields ' acitance of the diffusion re~on to substrate. The ~~\I.era\ capad\antt
~ap HA!! with smaller &ource or drlln mu. The -ptr\phm\ . - m
11\ete-.~
 ·~
VLSI Design 4 • 54
. ,~,,°"
Gate L
'
required to be taken into account for total capacitance ralculati~o
~~ffi~
™~
Ctotal = Cperipheral +Carea
• 1be n-active and p-active regions formed by impurity implant at the
stlr
silicon have negligible depth and hence have negligible peripheral ca ~ace of
· heraI capac1·tance va1ues are given
· m · Table 4_ _Pacit~ ..1
Typical area and penp 6 1_ "' C'e.
Diffusion capacitance
Sµm
Area C (Carea) 1.0x10- 4 pF/µrrf 1.75:x:_1q- 4 pFl µrrf?
1:\
Periphery (Cperi;h) 8.0x 10- 4 pF/ µm -negligible* negligible•
Table 4.6.1 Typical values for diffusion capacitances
* Assuming implanted regions of negligible depth.
/"I
 ~· [xplam. '" "1,/
It tt
' .,, '"%,e,i
"'"°"" ..
4
, , , , - - - - ---- ----- •g ltrg, ht 1ll$J t/11#1/1 I
e"e •I of F.,n-ln f Fa"'"'GI.ft 0
....tSadctl

ffhe number of Inputs "

I

;~ .__/ . Propagauon Dtlay_

fl that a
, ,aN' resistance of a 8eries trallst•t, have Is <ailed a, P111-1r,. Tho ilddltlvi
1018
11t ~j
:/ !units the Pan-in of C!.tos fl"le8.
~,o maximum number of inJ>uts
01
fl , Th~ taining its output levels IVit•, th•thsame 1~~c fa:°'ilY that a gate can drive
{flat gate.
Jl1lllll ""' • Specified !units is called PilJl.out of
on propagation_delay.
input to CMOS logic gate ":quires two lr~tors, an nMOS and a pMOS ·
· t r· ~ is required. )
t , fJtate whereas for· other M()S logic.only one ·additionaJ
g ' OS logic gates, the effective U\put resistance is Very large (1012n) which
, ill aJinosi rio:current. B~t ea~ ~0§ inP~t typically p~ts a 5 pF load
fM
drawsdtance· to ground, This mcreasec1r input resistance ana capao.WIC.'e per 811'
c,pa pagation delay. ,· ·
]ltcte'ses P~tion delay can be compensal!d Jll!tiai!Y by atze scaling lllethod.
T)te propag in me, its cumnt driving' ctpabtllty ctt1, be Im~ but
' Wltll increlN • ·hence propagation
ct increases • , still ~creases with Fan-ln,
delay
ctpadtan in,. numwr At OU tputa of 1 ff
1..~ ur "•~ directly 1dd1 to l01d CIJ>idtfnct,
t AnlffltncrHN
ptoPlllffOf\ dollvI inma~ with Pin out,
I a,
 Choice of Layers
• Circuits are required to be optimally arranged on a silicon ar 'h
. thi ea. !Ile
several possible ways for domg s and the choice of the laye re c¾ b
. . rs on e
route data and control signals requues to be done as pet' cert ·~~ Which t
These guidelines are logical constraints pertaining to the electric ~n &uicteline 0
the layers. They are - a propel'ties ofs.

i) Long lengths 0f polysilicon should be incorporated only ft

consideration since' 1t· has relti'
a ve1y hih
g R5 value. Also it is ua ere
. arefu1
routing v55 and V0 0 except for very small distances. nsU.!table for
ii) Metal layers should be used as far as po~sible for distributing v
(GND). Wherever this is not' possible 'duck undei's' may be used poof anct V55
the diffusion !aver. ' re erabJYon
........

iii) If the above &11idelin~s are followed, usually the resistances asso .
o- . : . c1atect .
transistors turn out to be qrnte higher than any promment wiring . With
/ resistan
Hence there is no cause to worry for any voltage divider effects b ce.
· · and transIStor
wrrmg · · tances.
resIS etween
iv) Capacitive effects due to different layer combinations are the
consideration, especially for fast signal lines and the signals propagatin n:xt
wiring having relatively high values of R5 • In this context, diffusion (or g_ n
. active)
areas have relatively high values of capacitance to substrate and hence re .
. 'd . qUire
a harder drive. The signal may be tr~ated as bemg 1 entical at all points on the
wire over small equipotential regions. The delay associated with signal
propagation within a, region is very small as compared to gate delays and with
signal ,delays systems connected ~y wire~
• These r~ttictions have ·been standardized by limiting the maximum lengths of
communicati?n paths (wires) realized through different types of layers. They
are given in Table 4.8.1. _
 4-59 Gate Level Oesi,gn

Maximum length of communication wfre

Lambda-based (5 µm) µm-based (2 µm) µm-based (1.2 µm)

Chip wide Chip wide Chip wide
2,000 '),_ NA NA
Silicide

pofysilicon 200 '),_ 400 µm 250 ~lffi

OiffUsion (active) 20 '),_• 100 µm 60µm

Table 4.8.1 Electrical rules

, raking account of peripheral and area capacitances. NA = not applicable.
, The discussions on the guidelines for choice of layers are presented in a
tabular form in Table 4.8.2.

Layer R C Comments

V-Metal Low - .L~w, Good current capability without larAe v?ltage drop ···
.,, use for power distribution and global signals .
- Silicide Low Moderate Modest RC product. Reasonably long wir~ are .
possible. Silicide is used in place of polysihcon in
some nMOS processes.

High M~eriite- RC product is moderate; high IR drop.

Potysllicon
High Moderate IR drop but high C. Hence ha rd to drive.
[)ilfusion (active) Moderate
,_
Table 4.8.2 Choice of layers

Review Questions
1. Explain the criteria for choice of layers.
2. State the logical constraints for layers.

nnn