CMOS Inverter Design

Yu-Te Liao
Department of Electrical and Computer
Engineering
National Chiao Tung University

1
 Outline
 Operation of Inverter
 Design Metrics:
− Propagation delay
− Power consumption
 Design optimization
− Inverter chain sizing for optimal propagation delay
− Power consumption reduction

2
 Operation of an Inverter
 MOS transistors work as switches
 A fast gate is built either by keeping the output
capacitance small or by decreasing the on-
resistance of the transistor.

3
 VTC of an Inverter

IDSP = −IDSN
VGSn = Vin VGSp = Vin -VDD
VDSn = Vout VDSp = Vout -VDD

Assume VDD = 2.5V

Introduction to VLSI Design 2012

4
 Inverter VTC
 VTC: Voltage Transfer Characteristic

ID n
Vin = 0 Vin = 2.5

PMOS Vin = 0.5 Vin = 2 NMOS

Vin = 1 Vin = 1.5

Vin = 1.5 Vin = 1
Vin = 1.5 Vin = 1
Vin = 2 Vin = 0.5

Vin = 2.5 Vin = 0

Vout

5
 Inverter VTC
 Five regions of NMOS and PMOS transistor operation
 The sharp transition zone results in the high gain during
transition
Vout
NMOS off
2.5 PMOS res
NMOS s at
PMOS res
VIH and VIL are the
2

operational points NMOS sat VM: Threshold Voltage

1.5

𝜕𝑉𝑜𝑢𝑡 PMOS sat (Slope = 1 or Vin= Vout)

where = −1
𝜕𝑉𝑖𝑛
1

NMOS res
PMOS sat NMOS res
0.5

PMOS off

0.5 1 1.5 2 2.5 Vin

Introduction to VLSI Design 2012

6
 Switching Threshold
 The switching threshold is defined as the point
where Vin = Vout
 Velocity saturation region:
𝑉𝐷𝑆𝐴𝑇
𝐼𝐷𝑆 = 𝑘𝑛𝑉𝐷𝑆𝐴𝑇 𝑉𝐺𝑆 − 𝑉𝑡ℎ −
2
VDSATn VDSATp
I DS  k nVDSATn (VM  VTn  )  k pVDSATp (VM  VDD  VTp  )
2 2
𝑉𝐷𝑆𝐴𝑇𝑛 𝑉𝐷𝑆𝐴𝑇𝑝
𝑉𝑡𝑛 + + 𝑟(𝑉𝐷𝐷 + 𝑉𝑇𝑃 + ) 𝑟𝑉𝐷𝐷
𝑉𝑀 = 2 2 ≈
1+𝑟 1+𝑟
𝑘𝑝𝑉𝐷𝑆𝐴𝑇𝑝 𝜐𝑠𝑎𝑡𝑝𝑊𝑃
𝑟= =
𝑘𝑛𝑉𝐷𝐴𝑆𝑇𝑛 𝜐𝑠𝑎𝑡𝑛𝑊𝑁
7
 Switching Threshold (cont.)

 Switching threshold set by the ratio r, which

compares the relative driving strengths of the
PMOS and NMOS transistors

W / L P '
k n' VDSATn (VM  VTn  VDSATn / 2)
(W / L) N k pVDSATp (VDD  VM  VTp  VDSATp / 2)

VTP and VDSATP are negative values

 To have comparable high and low noise margins,

VM = VDD/2 , resulting in r  1.
8
 Quiz
 Which curve means PMOS has better driving
strength?

(3) (2)
(1)

9
 Skewed Inverter
 A skewed inverter can be used to shape the noisy
signal.

10
 Noise Margin
 In a digital circuit, the noise margin is the amount
by which the signal exceeds the threshold for a
proper '0' or '1'.
NMH = VDD - VIH
NML = VIL

VIH = VM - VM /g
VIL = VM + (VDD - VM )/g

So high gain in the transition

region is very desirable
A piece-wise linear approximation of VTC

11
 Effective Resistor in Transition
 Short channel devices

𝑉𝐷𝐷 /2
1 𝑉 3 𝑉𝐷𝐷
𝑅𝑒𝑞 = 𝑑𝑉 =
−𝑉𝐷𝐷 /2 𝑉𝐷𝐷 𝐼𝐷𝑆𝐴𝑇 4 𝐼𝐷𝑆𝐴𝑇

𝑘′𝑊 𝑉2𝐷𝑆𝐴𝑇
𝐼𝐷𝑆𝐴𝑇 = ( 𝑉𝐷𝐷 − 𝑉𝑇 𝑉𝐷𝑆𝐴𝑇 − )
𝐿 2 12
 Propagation delay
3 𝐶𝐿𝑉𝐷𝐷
 𝑇𝑝𝐻𝐿 = 𝑅𝐶 × ln 2 = 0.69 × =
4 𝐼𝐷𝑆𝐴𝑇
𝐶𝐿𝑉𝐷𝐷 𝐶𝐿
 0.52 𝑊 𝑉𝐷𝑆𝐴𝑇 ≈ 0.52 𝑊
𝑘′𝑉 𝐷𝑆𝐴𝑇
(𝑉𝐷𝐷−𝑉𝑡𝑛− ) ( )𝑘′𝑉𝐷𝑆𝐴𝑇
𝐿 2 𝐿

(Assume VDD >> Vtn + ½ VDSAT )

The delay is insensitive

to supply variations for
high value VDD

13
Capacitance of an Inverter Chain

C L  Cdb 2  Cdb1  Cw  C g 4  C g 3  2C gd 12
VDD VDD
Cgp
Cdbp

In Cgd Out

Cdbn
Cw
Cgn

14
 Propagation Delay (cont.)
 Minimize propagation delay(PD)
− Reduce CL : reduce interconnection capacitance and
transistor intrinsic capacitance (minimize drain diffusion
areas)
− Reduce Ron: Increase W/L. however, the gate sizing
stops help when the gate capacitance dominates.(self-
loading)
− Increase VDD: trade off with power dissipation, oxide
breakdown, and hot electron effect

15
 Transistor Sizing
Loaded by an identical inverter.
𝐶𝐿 = 𝐶𝑑𝑝1 + 𝐶𝑑𝑛1 + 2𝐶𝑔𝑑1 + 𝐶𝑔𝑝2 + 𝐶𝑔𝑛2 + 𝐶𝑤
= 1 + 𝛽 𝐶𝑑𝑛1 + 𝐶𝑔𝑛2 + 2𝐶𝑔𝑑1 + 𝐶𝑤

0.69 Reqp
𝑇𝑝 = ( 1 + 𝛽 𝐶𝑑𝑛1 + 𝐶𝑔𝑛2 + 2𝐶𝑔𝑑𝑛1 + 𝐶𝑤)(Reqn + )
2 β
γ
= 0.345( 1 + 𝛽 𝐶𝑑𝑛1 + 2𝐶𝑔𝑑𝑛1 + 𝐶𝑔𝑛2 + 𝐶𝑤)Reqn(1 + )
β
𝜇𝑛 𝑊𝑝 𝜕𝑇𝑝
𝛾= 𝛽= =0
𝑢𝑝 𝑊𝑛 𝜕𝛽

𝐶𝑤
𝛽𝑜𝑝𝑡 = 𝛾(1 + )
𝐶𝑑𝑛1 𝐶𝑔𝑛2
+

16
 Transistor Sizing (cont.)
 PD of CMOS inverter is as a function of the PMOS-
to-NMOS ratio
x 10-11
5
Symmetric
4.5 design
Tp(sec)

3.5
Minimum Tp
3
1 1.5 2 2.5 3 3.5 4 4.5 5
b
17
 Inverter Sizing for Different Loading
 S is the size ratio between designed inverter and
referenced inverter
𝐶𝑒𝑥𝑡
𝑇𝑝 = 0.69𝑅𝑖𝑛𝑡𝐶𝑖𝑛𝑡(1 + ) (Delay(intrinsic) + Delay(external))
𝐶𝑖𝑛𝑡
𝑅𝑟𝑒𝑓 𝐶𝑒𝑥𝑡
𝑇𝑝 = 0.69( )(𝑆𝐶𝑖𝑟𝑒𝑓 )(1 + )
𝑆 𝑆𝐶𝑖𝑟𝑒𝑓

𝐶𝑒𝑥𝑡 𝐶𝑒𝑥𝑡
𝑇𝑝 = 0.69𝑅𝑟𝑒𝑓 𝐶𝑖𝑟𝑒𝑓 1+ = 𝑇𝑝0(1 + )
𝑆𝐶𝑖𝑟𝑒𝑓 𝑆𝐶𝑖𝑟𝑒𝑓
 Tp0 is independent of the sizing of the gate
 S is sufficiently large Tp = Tp0

18
 Sizing a Chain of Inverters

𝐶𝑖𝑛𝑡 = 𝛾𝐶𝑔

𝐶𝑒𝑥𝑡 𝑓
𝑇𝑝 = 𝑇𝑝0 1+ = 𝑇𝑝0(1 + )
𝛾𝐶𝑔 𝛾

 Only a function of the ratio between its external

load capacitance and its input capacitance
 f: effective fan-out

19
 Sizing a Chain of Inverters
When each stage has the same size fN=F=CL/Cg,1 ,
the inverter chain achieves a minimum propagation
delay.
𝑁
𝐶𝑔, 𝑗 + 1 𝜕𝑇𝑝
𝑇𝑝 = 𝑇𝑝0 (1 + ) =0
𝛾𝐶𝑔, 𝑗 𝜕𝐶𝑔, 𝑗
𝑗=1

𝐶𝑔, 𝑗 + 1 𝐶𝑔 , 𝑗
= 𝐶𝑔, 𝑗 = 𝐶𝑔𝑗 + 1𝐶𝑔𝑗 − 1
𝐶𝑔, 𝑗 𝐶𝑔, 𝑗 − 1

𝑁
𝑁 𝐶𝐿 𝐹
𝑓= =
𝑁
𝐹 𝑇𝑝 = 𝑁𝑇𝑝0(1 + )
𝐶𝑔, 1 𝛾
20
 Example

In Out
1 f f2 CL= 8 C1
C1

CL/C1 has to be evenly distributed across N = 3

stages: 3
f  82

21
 Optimal Stages
 𝛾 = 0 Nopt = ln 𝐹
 𝛾 = 1 Nopt = 3.6 usually select optimum fan-out = 4
 Select fan-out less than 4 does not affect the Tp too
much.
𝑁
𝐹
𝜕𝑇𝑝 𝜕𝑁𝑇𝑝0(1 + 𝛾 )
= =0
𝜕𝑁 𝜕𝑁
𝑁 𝛾
𝑁 𝐹 𝑙𝑛𝐹 (1+ )
𝛾+ 𝐹−
𝑁
=0 𝑓= 𝑒 𝑓

22
 Example
 Size inverter 2 and 3

2 3

2 3

2 3

1 2 3

Cg1 64Cg1

4𝐶𝑔2 4𝐶𝑔3 64𝐶𝑔1

= =
𝐶𝑔1 𝐶𝑔2 𝐶𝑔3 𝐶𝑔3 = 2.52𝐶𝑔2 = 6.35𝐶𝑔1

23
 Sizing of an Inverter Chain

Cg1 1 f f2 fN-1 CL

𝐶𝑒𝑥𝑡 (Cascaded two

𝑇𝑝 = 0.69𝑅𝑒𝑞 𝐶𝑜𝑢𝑡 + 𝐶𝑒𝑥𝑡 = 0.69𝑅𝑒𝑞𝐶𝑜𝑢𝑡(1 + ) inverters)
𝐶𝑜𝑢𝑡
𝑁
𝐶 𝑓 𝐹 𝐶𝐿
𝑇𝑝 = 𝑇𝑝0 1 + 𝑒𝑥𝑡 = 𝑇𝑝0 1 + 𝑇𝑝 = 𝑁𝑇𝑝0 1 + ,𝐹 =
𝛾𝐶𝑔 𝛾 𝛾 𝐶𝑔1
−1 𝑓𝑁 − 1 𝐹−1
𝐴𝑑𝑟𝑖𝑣𝑒𝑟 = 1 + 𝑓 + 𝑓2 + ⋯ + 𝑓𝑁 𝐴𝑚𝑖𝑛 = 𝐴𝑚𝑖𝑛 = 𝐴𝑚𝑖𝑛
𝑓−1 𝑓−1
−1 𝐹−1 𝐶𝐿 2
𝐸𝑑𝑟𝑖𝑣𝑒𝑟 = 1 + 𝑓 + 𝑓2 + ⋯ + 𝑓𝑁 𝐶𝑖𝑉 𝐷𝐷 =
2 𝐶𝑖𝑉 𝐷𝐷 ≈
2 𝑉 𝐷𝐷
𝑓−1 𝑓−1
Large f can reduce power dissipation at the cost of large area!!
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 Power Dissipation in Static CMOS Logics
 Static CMOS logics are almost no power
consumption in steady-state operation mode
 Dynamic power consumption
− Charge and discharge capacitors
 Short circuit current
− Short circuit path between supply rails during switching
 Leakage current
− Leaking diode and transistor

25
 Power Dissipation
 Dynamic power
  dvin v
E in   i in (t)vin (t)dt  V  C dt  CV  dvin  CV 2
0 0 dt 0
  dv out v 1
E C   i out (t)v out (t)dt   C vout dt  C  v out dv out  CVout
2
0 0 dt 0 2
2𝐸𝑑𝑦𝑛 Reducing Vdd has a quadratic effect on
𝑃𝑑𝑦𝑛 = = 𝐶𝐿𝑉2𝐷𝐷𝑓
𝑡𝑝𝐿𝐻 + 𝑡𝑝𝐻𝐿 dynamic power dissipation
Vout

iDD

Vout
iDD

Charge Discharge
26
Dissipation Due to Direct Path Current
 The finite slope of the input signal causes a direct
current path between VDD and gnd

ts

Vin VDD -VT

iSC Vout VT

Ishort

𝑉𝐷𝐷 − 2𝑉𝑇
𝑇𝑠ℎ𝑜𝑟𝑡 = 𝑡𝑠
𝑉𝐷𝐷
27
 Reduce Short Circuit Current
 Making the output rise/fall time larger than input
rise/fall time (Increase CL)  cause the problems in
the following stages
 Lower supply voltage: VDD< Vtn+|Vtp|

Large CL

iSC Vout

Small CL

28
 Static Power Consumption
 CMOS inverter has almost zero static power
dissipation except leakage current from diodes in
the CMOS process
 Leakage current degrades the noise margins since
logic levels are not equal to the supply rails

VDD

Vout =VDD
Ileakage

Isubthreshold
29
 Supply Voltage Scaling
 Power consumption reduction
 Low Speed
 DC characteristic becomes sensitive to variation in the
device parameters.
 Reduce signal swing (signals become sensitive to noise)

2.5 0.2
high supply low supply
2
voltage (>Vth) 0.15 voltage (<Vth)
1.5
Vout (V)

Vout (V)
0.1
1

0.05
0.5

0 0
0 0.5 1 1.5 2 2.5 0 0.05 0.1 0.15 0.2
Vin (V) Vin (V)
30
 Multiple Vth Design
 To reduce power consumption, we can turn off the
unused circuits.
 Use high Vt transistor in the standby switch, leading
to small leakage current.
VDD

Standby
High VT

Virtual VDD

Logic
device
Cbypass

31
 Tristate Inverter
 Tristate inverter is used to control the signal path
and provide a high impedance when it is off.
 EN = 0 inverter
 EN = 1 floating output (High impedance )

EN

EN
Vin Vout Vin Vout

ENb

ENb

(a) (b)
32
 Energy-delay Product
 Energy-delay product (EDP) = Power-delay
2
𝐶 𝑉
productor (PDP) x Tp = 𝑃𝑎𝑣 × 𝑇𝑝2 = 𝐿 𝐷𝐷 𝑇𝑝
2
𝛼𝐶𝐿𝑉𝐷𝐷
 𝑇𝑝 ≈
𝑉𝐷𝐷−𝑉𝑇𝐻 −𝑉𝐷𝑆𝐴𝑇/2

𝛼𝐶2𝐿𝑉3𝐷𝐷
 𝐸𝐷𝑃 =
2(𝑉𝐷𝐷−𝑉𝑇𝐻−𝑉𝐷𝑆𝐴𝑇/2)

𝜕𝐸𝐷𝑃 3 𝑉𝐷𝑆𝐴𝑇
 =0 𝑉𝐷𝐷𝑜𝑝𝑡 = (𝑉𝑇𝐻 + )
𝜕𝑉𝐷𝐷 2 2

33
 Power Consumption Reduction
 Voltage reduction
 Reduce switching activity
 Reduce physical capacitance

34
 Conclusion
 Review of the supply voltage scaling effect in
inverter design
 Propagation delay of inverter
 Sizing of inverter
 Power consumption of inverter
 Next lecture: wire and interconnection (Chap 4 and
9)

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