U20ECCJ12 DIGITAL ELECTRONICS UNIT2 IMPORTANT QUESTIONS WITH ANSWERS

UNIT2 SYLLABUS

Unit II Combinational Circuit Design

• Analysis Procedure,
• Design Procedure,
• Binary Adder-Subtractor,
• Carry look ahead Adder,
• Decimal Adder,
• BCD Adder,
• Binary Multiplier,
• Magnitude Comparator,
• Decoders, Encoders,
• Priority Encoder,
• Multiplexers,
• Boolean function Implementation
•
Important questions

1
 ANALYSIS PROCEDURE OF COMBINATIONAL CIRCUIT DESIGN
1).Briefly explain the analysis procedure of combinational circuit design(8)
Answer: 3).Obtain the truth table for the outputs of those gates that are a function of the input variables
• Analysis of a combinational circuit is starts with a given logic diagram and culminates with a only.
set of Boolean functions, a truth table, or a verbal explanation of the circuit operation. 4).Proceed to obtain the truth table for the outputs of those gates that are a function of
• The first step in the analysis is to make sure that the given circuit is combinational circuit. The previously defined values until the columns for all outputs are determined.
logic diagram of a combinational circuit has logic gates with no feedback paths. • The following table1 shows truth table for the logic diagram shown in figure1.
• Once the logic diagram is verified as a combinational circuit, then we can proceed to obtain
the Boolean function and its truth table.
• To obtain Boolean function from a logic diagram, proceed as follows.
1).Label with arbitrary symbols all gate outputs that are a function of the input variables.
Obtain the Boolean functions for each gate.
2).Label with other arbitrary symbols those gates that are a function of input variables and/or
previously labeled gates. Find the Boolean functions for these gates.
3).Repeat the process outlined in step2 until the outputs of the circuit are obtained.
4).By repeated substitution of previously defined functions, obtain the output Boolean
functions in terms of input variables only.
Example: Explain the analysis procedure of the combinational circuit in figure1 given below with the
proposed procedure.
• Inspection of the truth table combinations for 𝐴𝐴, 𝐵𝐵, 𝐶𝐶, 𝐹𝐹1 , and 𝐹𝐹2 of table 4.2 shows that it is
identical to the truth table of the full-adder shown in figure.1.

• For this example, note that the circuit is a full-adder, with output 𝐹𝐹1 being the sum output and
𝐹𝐹2 the carry output. 𝐴𝐴, 𝐵𝐵, and 𝐶𝐶 are the three inputs added arithmetically.
• The Boolean functions for outputs 𝐹𝐹2 , 𝑇𝑇1 and 𝑇𝑇2 are
𝐹𝐹2 = 𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐴𝐴 + 𝐵𝐵𝐵𝐵
𝑇𝑇1 = 𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶
𝑇𝑇2 = 𝐴𝐴𝐴𝐴𝐴𝐴
• Obtain 𝐹𝐹1 output as follows
𝐹𝐹1 = 𝑇𝑇3 + 𝑇𝑇2 = 𝐹𝐹2′ 𝑇𝑇2 + 𝐴𝐴𝐴𝐴𝐴𝐴 = (𝐴𝐴𝐴𝐴 + 𝐴𝐴𝐴𝐴 + 𝐵𝐵𝐵𝐵)′ (𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶) + 𝐴𝐴𝐴𝐴𝐴𝐴
= (𝐴𝐴′ + 𝐵𝐵′ )(𝐴𝐴′ + 𝐶𝐶 ′ )(𝐴𝐴 + 𝐵𝐵 + 𝐶𝐶)
= (𝐴𝐴′ + 𝐵𝐵′ 𝐶𝐶 ′ )(𝐴𝐴𝐵𝐵′ + 𝐴𝐴𝐶𝐶 ′ + 𝐵𝐵𝐶𝐶 ′ + 𝐵𝐵′ 𝐶𝐶) + 𝐴𝐴𝐴𝐴𝐴𝐴
= 𝐴𝐴′ 𝐵𝐵𝐶𝐶 ′ + 𝐴𝐴′ 𝐵𝐵′ 𝐶𝐶 + 𝐴𝐴𝐵𝐵′ 𝐶𝐶 ′ + 𝐴𝐴𝐴𝐴𝐴𝐴
• To obtain the truth table from the logic diagram, proceed as follows.
1).Determine the number of input variables to the circuit. For 𝑛𝑛 inputs, form the 2𝑛𝑛 possible
input combinations of 1’s and 0’s by listing the binary numbers from 0 to 2𝑛𝑛 − 1.
2).Label the outputs of selected gates with arbitrary symbols.

2
 DESIGN PROCEDURE OF COMBINATIONAL CIRCUIT DESIGN
1).Briefly explain the design procedure of combinational circuit design(6)
Answer:
• The design of combinational circuits starts from the verbal outline of the problem and ends in
a logic circuit diagram or a set of Boolean functions from which the logic diagram can be
easily obtained.
• The procedure involves the following steps.
1). The problem is stated.
2). The number of available input variables and required output variables is determined.
3). The input and output variables are assigned letter symbols.
4). The truth table that defines the required relationships between inputs and outputs is
derived.
5). The simplified Boolean function for each output is obtained.
6). The logic diagram is drawn.

• A truth table for a combinational circuit consists of input columns and output columns.
• The 1’s and 0’s in the input columns are obtained from the 2𝑛𝑛 binary combinations available
for 𝑛𝑛 input variables.
• The output functions specified in the truth table give the exact definition of the combinational
circuit.
• The output Boolean functions from the truth table are simplified by any available method such
as algebraic manipulation, the map method, or the tabulation procedure.
• A practical design method would have to consider such constraints as
1). Minimum number of gates
2).Minimum number of inputs to a gate
3).Minimum propagation time of the signal through the circuit
4).Minimum number of interconnections
5).Limitations of the driving capabilities of each gate.
• In practice, designers tend to go from the Boolean functions to a wiring list that shows the
interconnections among various standard logic gates. In that case , the design need not go
any further than the required simplified output Boolean functions. However, a logic diagram is
helpful for visualizing the gate implementation of the expressions.

3
 Binary Adder-Subtractor Carry look ahead Adder
Example: Design and implement of 4 bit binary Adder-Subtractor circuit (8). Example: Design and implement of Carry look ahead Adder circuit (8).
Answer: Answer:
• A 4-bit adder-subtractor circuit is shown in figure1 given below. • The construction of a 4-bit parallel adder with a look-ahead carry scheme is shown in figure1
given below.

• In this circuit, the mode input 𝑀𝑀 controls the operation. When 𝑀𝑀 = 0, the circuit is an adder,
and when 𝑀𝑀 = 1, the circuit becomes a subtractor.
• Here, each exclusive OR gate receives input 𝑀𝑀 and one of the inputs of 𝐵𝐵.

E ×

• In this circuit, each sum output requires two exclusive-OR gates. The output of the first
exclusive-OR gate generates the 𝑃𝑃𝑖𝑖 variable, and the AND gate generates the 𝐺𝐺𝑖𝑖 variable. All
the 𝑃𝑃′𝑠𝑠 and 𝐺𝐺′𝑠𝑠 are generated in two gate levels.
• The carries are propagated through the look-ahead carry generator and applied as inputs to
the second exclusive-OR gate. After the 𝑃𝑃 and 𝐺𝐺 signals settle into their steady state values,
all output carries are generated after a delay of two-level gates. Thus, outputs 𝑆𝑆2 through 𝑆𝑆4
have equal propagation delay times.

×
4
 Decimal Adder or Decimal BCD Adder
Briefly explain decimal BCD adder with its circuit diagram and truth table.(8) • In this table, the first column lists the binary sums as they appear in the outputs of a 4-bit
Answer: binary adder.
• The circuit diagram for addition of two decimal digits in decimal BCD adder is shown in • The output sum of two decimal digits must be represented in BCD and should appear in the
figure1 given below. form listed in the second column of the table.
• A decimal parallel adder that adds 𝑛𝑛 decimal digits needs 𝑛𝑛 BCD adder stages.
• The output carry from one stage must be connected to the input carry of the next higher order
stage.

E ×

• In this circuit, Boolean function of output carry can be expressed by

𝐶𝐶 = 𝐾𝐾 + 𝑍𝑍8 𝑍𝑍4 + 𝑍𝑍8 𝑍𝑍2
• The truth table of this BCD adder circuit is shown in table given below.

5
 MAGNITUDE COMPARATOR
Briefly explain a magnitude comparator circuit in details(8)
Answer:
• A magnitude comparator is a combinational circuit that compares two numbers, 𝐴𝐴 and 𝐵𝐵, and
determines their relative magnitudes.
• The outcome of the comparison is specified by three binary variables that indicate whether
𝐴𝐴 > 𝐵𝐵, 𝐴𝐴 = 𝐵𝐵, or 𝐴𝐴 < 𝐵𝐵.
• A 4-bit magnitude comparator circuit is shown in figure.1 given below.

• In this circuit, the four 𝑥𝑥 outputs are generated with exclusive-NOR circuits and applied to an
AND gate to give the output binary variable (𝐴𝐴 = 𝐵𝐵).
• The other two outputs use the 𝑥𝑥 variables to generate the Boolean functions
(𝐴𝐴 > 𝐵𝐵) = 𝐴𝐴3 𝐵𝐵3′ + 𝑥𝑥3 𝐴𝐴2 𝐵𝐵2′ + 𝑥𝑥3 𝑥𝑥2 𝐴𝐴1 𝐵𝐵1′ + 𝑥𝑥3 𝑥𝑥2 𝑥𝑥1 𝐴𝐴0 𝐵𝐵0′
(𝐴𝐴 < 𝐵𝐵) = 𝐴𝐴′3 𝐵𝐵3 + 𝑥𝑥3 𝐴𝐴′2 𝐵𝐵2 + 𝑥𝑥3 𝑥𝑥2 𝐴𝐴1′ 𝐵𝐵1 + 𝑥𝑥3 𝑥𝑥2 𝑥𝑥1 𝐴𝐴′0 𝐵𝐵0

• The symbols(𝐴𝐴 > 𝐵𝐵) and (𝐴𝐴 < 𝐵𝐵) are binary output variables that are equal to 1 when 𝐴𝐴 > 𝐵𝐵
or 𝐴𝐴 < 𝐵𝐵 respectively.

E ×
6
 Decoders and Encoders
Briefly explain 3-to-8 line Decoder circuit in details(8)
Answer:
• A decoder is a combinational circuit that converts binary information from 𝑛𝑛 input lines to a
maximum of 2𝑛𝑛 unique output lines.
• A 3-to-8 line decoder circuit is shown in figure1 given below.

• A 4 × 16 decoder circuit which is constructed with two 3 × 8 decoders are shown in figure.2
given below.

• This decoder circuit shows that its three inputs are decoded into eight outputs, each output
representing one of the minterms of the 3-input variables. E ×
• The truth table of this decoder circuit is shown in table1 given below.

7
 Encoders
Briefly explain 3-to-8 line Encoder circuit in details(8)
• An encoder has 2𝑛𝑛 input lines and 𝑛𝑛 output lines.
• An octal-to-binary encoder circuit is implement with three OR gates are shown in figure.1
given below.

• The operation of the priority encoder is such that if two or more inputs are equal to 1 at the
same time, the input having the highest priority will take precedence.
• This priority encoder is implemented in figure.2 according to the following Boolean functions.
𝑥𝑥 = 𝐷𝐷2 + 𝐷𝐷3
𝑦𝑦 = 𝐷𝐷3 + 𝐷𝐷1 𝐷𝐷2′
• The truth table of this octal-to-binary encoder circuit is shown in table.1 given below. 𝑉𝑉 = 𝐷𝐷0 + 𝐷𝐷1 + 𝐷𝐷2 + 𝐷𝐷3

• The truth table of a four-input priority encoder is shown in table2 given below.

• A 4-bit priority encoder circuit that includes the priority function is shown in figure.2 given
below.
• Here a valid-output indicator, designated by 𝑉𝑉, is set to 1 only when one or more of the inputs
are equal to 1.
• If all inputs are 0, 𝑉𝑉 is equal to 0, and the other two outputs of the circuit are not used.

8
 Multiplexers
Briefly explain Multiplexer circuit in details(8) • In this circuit, each of the four input lines , 𝐼𝐼0 to 𝐼𝐼3 , is applied to one input of an AND gate.
Answer: Selection lines 𝑠𝑠1 and 𝑠𝑠0 are decoded to select a particular AND gate.
• A multiplexer is a combinational circuit that has 2𝑛𝑛 input lines, 𝑛𝑛 selection lines and a single • The truth table for the above circuit is shown in table1 given below.
output line.
• The block diagram of 4-to-1 multiplexer is shown in figure1 given below.

• A quadrauple 2-to-1-line multiplexer circuit is shown in figure2 given below.

• A 4-to-1 line multiplexer circuit is shown in figure2 given below.

• This circuit has four multiplexers, each capable of selecting one of two input lines. Its function
table1 shows its operation.

9
 Boolean function Implementation
Example: Implement the Boolean function 𝐹𝐹(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∑(1,3,5,6) with a 4 × 1 multiplexer.(8)
Answer: Given
𝐹𝐹(𝐴𝐴, 𝐵𝐵, 𝐶𝐶) = ∑(1,3,5,6) …(1)

• Truth table for the given function in eqn.(1) is shown in table1 given below.

• The implementation table for the Boolean function in eqn.(1) is shown in table2 given below.

• From this implementation table2 we can obtain the multiplexer connections as shown in
figure1 given below.

E ×

10
11