56F801

Data Sheet
Preliminary Technical Data

56F800
16-bit Digital Signal Controllers

DSP56F801
Rev. 17
09/2007

freescale.com
 Document Revision History

Version History Description of Change

Rev. 17 Added revision history.

Added this text to footnote 2 in Table 3-8: “However, the high pulse width does not have to
be any particular percent of the low pulse width.”
56F801 General Description

• Up to 30 MIPS operation at 60MHz core frequency • 8K × 16-bit words (16KB) Program Flash
• Up to 40 MIPS operation at 80MHz core frequency • 1K × 16-bit words (2KB) Program RAM
• DSP and MCU functionality in a unified, • 2K × 16-bit words (4KB) Data Flash
C-efficient architecture • 1K × 16-bit words (2KB) Data RAM
• MCU-friendly instruction set supports both DSP and • 2K × 16-bit words (4KB) Boot Flash
controller functions: MAC, bit manipulation unit, 14
addressing modes • General Purpose Quad Timer
• Hardware DO and REP loops • JTAG/OnCETM port for debugging
• 6-channel PWM Module • On-chip relaxation oscillator
• Two 4-channel, 12-bit ADCs • 11 shared GPIO
• Serial Communications Interface (SCI) • 48-pin LQFP Package
• Serial Peripheral Interface (SPI)

6
PWM Outputs
PWMA

Fault Input RESET

VCAPC VDD VSS VDDA VSSA
IRQA 6
2 4 5*

JTAG/ Digital Reg Analog Reg

OnCE
Port Low Voltage
A/D1
4 Supervisor
A/D2 ADC
4 VREF
Interrupt
Controller Data ALU
Program Controller Address Bit
16 x 16 + 36 → 36-Bit MAC
and Generation Manipulation
Three 16-bit Input Registers
Hardware Looping Unit Unit Unit
Two 36-bit Accumulators

Program Memory
•
PAB
8188 x 16 Flash PLL
Quad Timer C 1024 x 16 SRAM
• PDB
• 16-Bit
Clock Gen
Quad Timer D Boot Flash 56800 or Optional GPIOB3/XTAL
or GPIO 2048 x 16 Flash Core Internal
3 XDB2 GPIOB2/EXTAL
Relaxation Osc.
Data Memory
• CGDB
• •
•
2048 x 16 Flash XAB1
1024 x 16 SRAM
•
XAB2
INTERRUPT IPBB
SCI0 CONTROLS CONTROLS
or 16 16
2 GPIO COP/
Watchdog COP RESET
Applica- MODULE CONTROLS
SPI tion-Specific IPBus Bridge
ADDRESS BUS [8:0]
or
Memory & (IPBB)
4 GPIO DATA BUS [15:0]
Peripherals
*includes TCS pin which is reserved for factory use and is tied to VSS

56F801 Block Diagram

56F801 Technical Data, Rev. 17

Freescale Semiconductor 3
Part 1 Overview
1.1 56F801 Features
1.1.1 Digital Signal Processing Core
• Efficient 16-bit 56800 family controller engine with dual Harvard architecture
• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Two 36-bit accumulators including extension bits
• 16-bit bidirectional barrel shifter
• Parallel instruction set with unique processor addressing modes
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Controller style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/OnCE debug programming interface

1.1.2 Memory
• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
• On-chip memory including a low-cost, high-volume Flash solution
— 8K × 16 bit words of Program Flash
— 1K × 16-bit words of Program RAM
— 2K × 16-bit words of Data Flash
— 1K × 16-bit words of Data RAM
— 2K × 16-bit words of Boot Flash
• Programmable Boot Flash supports customized boot code and field upgrades of stored code through a
variety of interfaces (JTAG, SPI)

1.1.3 Peripheral Circuits for 56F801

• Pulse Width Modulator (PWM) with six PWM outputs, two Fault inputs, fault-tolerant design with deadtime
insertion; supports both center- and edge-aligned modes
• Two 12-bit, Analog-to-Digital Converters (ADCs), which support two simultaneous conversions with two
4-multiplexed inputs; ADC and PWM modules can be synchronized
• General Purpose Quad Timer: Timer D with three pins (or three additional GPIO lines)
• Serial Communication Interface (SCI) with two pins (or two additional GPIO lines)
• Serial Peripheral Interface (SPI) with configurable four-pin port (or four additional GPIO lines)

56F801 Technical Data, Rev. 17

4 Freescale Semiconductor
 56F801 Description

• Eleven multiplexed General Purpose I/O (GPIO) pins

• Computer-Operating Properly (COP) watchdog timer
• One dedicated external interrupt pin
• External reset pin for hardware reset
• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
• Oscillator flexibility between either an external crystal oscillator or an on-chip relaxation oscillator for
lower system cost and two additional GPIO lines

1.1.4 Energy Information

• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
• Uses a single 3.3V power supply
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available

1.2 56F801 Description

The 56F801 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and
compact program code, the 56F801 is well-suited for many applications. The 56F801 includes many
peripherals that are especially useful for applications such as motion control, smart appliances, steppers,
encoders, tachometers, limit switches, power supply and control, automotive control, engine
management, noise suppression, remote utility metering, and industrial control for power, lighting, and
automation.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C compilers to enable rapid
development of optimized control applications.
The 56F801 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F801 also provides one external
dedicated interrupt lines and up to 11 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.
The 56F801 controller includes 8K words (16-bit) of Program Flash and 2K words of Data Flash (each
programmable through the JTAG port) with 1K words of both Program and Data RAM. A total of 2K
words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines
that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash
memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory
can also be either bulk or page erased.

56F801 Technical Data, Rev. 17

Freescale Semiconductor 5
A key application-specific feature of the 56F801 is the inclusion of a Pulse Width Modulator (PWM)
module. This modules incorporates six complementary, individually programmable PWM signal outputs
to enhance motor control functionality. Complementary operation permits programmable dead-time
insertion, and separate top and bottom output polarity control. The up-counter value is programmable to
support a continuously variable PWM frequency. Both edge- and center-aligned synchronous pulse width
control (0% to 100% modulation) are supported. The device is capable of controlling most motor types:
ACIM (AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM
(Switched and Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection
and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard
opto-isolators. A “smoke-inhibit”, write-once protection feature for key parameters is also included. The
PWM is double-buffered and includes interrupt control to permit integral reload rates to be programmable
from 1 to 16. The PWM modules provide a reference output to synchronize the Analog-to-Digital
Converters.
The 56F801 incorporates an 8 input, 12-bit Analog-to-Digital Converter (ADC). A full set of standard
programmable peripherals is provided that include a Serial Communications Interface (SCI), a Serial
Peripheral Interface (SPI), and two Quad Timers. Any of these interfaces can be used as General-Purpose
Input/Outputs (GPIO) if that function is not required. An on-chip relaxation oscillator provides flexibility
in the choice of either on-chip or externally supplied frequency reference for chip timing operations.
Application code is used to select which source is to be used.

1.3 State of the Art Development Environment

• Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
• The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.

56F801 Technical Data, Rev. 17

6 Freescale Semiconductor
 Product Documentation

1.4 Product Documentation

The four documents listed in Table 1-1 are required for a complete description and proper design with the
56F801. Documentation is available from local Freescale distributors, Freescale semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.

Table 1-1 56F801 Chip Documentation

Topic Description Order Number

56800E Detailed description of the 56800 family architecture, and 56800EFM

Family Manual 16-bit core processor and the instruction set
DSP56F801/803/805/807 Detailed description of memory, peripherals, and interfaces DSP56F801-7UM
User’s Manual of the 56F801, 56F803, 56F805, and 56F807
56F801 Electrical and timing specifications, pin descriptions, and DSP56F801
Technical Data Sheet package descriptions (this document)
56F801 Details any chip issues that might be present 56F801E
Errata

1.5 Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.

“asserted” A high true (active high) signal is high or a low true (active low) signal is low.

“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.

Examples: Signal/Symbol Logic State Signal State Voltage1

PIN True Asserted VIL/VOL

PIN False Deasserted VIH/VOH

PIN True Asserted VIH/VOH

PIN False Deasserted VIL/VOL

1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

56F801 Technical Data, Rev. 17

Freescale Semiconductor 7
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F801 are organized into functional groups, as shown in Table 2-1
and as illustrated in Figure 2-1. In Table 2-2 through Table 2-12, each table row describes the signal or
signals present on a pin.

Table 2-1 Functional Group Pin Allocations

Number of Detailed
Functional Group
Pins Description

Power (VDD or VDDA) 5 Table 2-2

Ground (VSS or VSSA) 6 Table 2-3

Supply Capacitors 2 Table 2-4

PLL and Clock 2 Table 2-5

Interrupt and Program Control 2 Table 2-6

Pulse Width Modulator (PWM) Port 7 Table 2-7

Serial Peripheral Interface (SPI) Port1 4 Table 2-8

Serial Communications Interface (SCI) Port1 2 Table 2-9

Analog-to-Digital Converter (ADC) Port 9 Table 2-10

Quad Timer Module Port 3 Table 2-11

JTAG/On-Chip Emulation (OnCE) 6 Table 2-12

1. Alternately, GPIO pins

56F801 Technical Data, Rev. 17

8 Freescale Semiconductor
 Introduction

VDD
Power Port 4
VSS
Ground Port 5*
VDDA
Power Port 1
VSSA
Ground Port 1

VCAPC PWMA0-5
Other
2 6
Supply
Port 1 FAULTA0

PLL and Clock EXTAL (GPIOB2)

1
or GPIO XTAL (GPIOB3)
1
56F801
1 SCLK (GPIOB4)
1 MOSI (GPIOB5) SPI Port
1 MISO (GPIOB6) or GPIO
1 SS (GPIOB7)

1 TXD0 (GPIOB0) SCI0 Port

1 RXD0 (GPIOB1) or GPIO

8 ANA0-7
1 ADCA Port
VREF

Quad
3 TD0-2 (GPIOA0-2)
Timer D
or GPIO
TCK
1
TMS
1 1 IRQA
TDI Interrupt/
JTAG/OnCE™ 1 Program
Port TDO Control
1 1 RESET
TRST
1
DE
1

*includes TCS pin which is reserved for factory use and is tied to VSS

Figure 2-1 56F801 Signals Identified by Functional Group1

1. Alternate pin functionality is shown in parenthesis.

56F801 Technical Data, Rev. 17

Freescale Semiconductor 9
2.2 Power and Ground Signals
Table 2-2 Power Inputs
No. of Pins Signal Name Signal Description

4 VDD Power—These pins provide power to the internal structures of the chip, and should all be
attached to VDD.

1 VDDA Analog Power—This pin is a dedicated power pin for the analog portion of the chip and
should be connected to a low noise 3.3V supply.

Table 2-3 Grounds

No. of Pins Signal Name Signal Description

4 VSS GND—These pins provide grounding for the internal structures of the chip, and should all
be attached to VSS.

1 VSSA Analog Ground—This pin supplies an analog ground.

1 TCS TCS—This Schmitt pin is reserved for factory use and must be tied to VSS for normal use.
In block diagrams, this pin is considered an additional VSS.

Table 2-4 Supply Capacitors and VPP

No. of Signal Signal State

Signal Description
Pins Name Type During Reset

2 VCAPC Supply Supply VCAPC—Connect each pin to a 2.2 μFor greater bypass capacitor in order
to bypass the core logic voltage regulator (required for proper chip
operation). For more information, refer to Section 5.2.

2.3 Clock and Phase Locked Loop Signals

Table 2-5 PLL and Clock
No. of Signal Signal State
Signal Description
Pins Name Type During Reset

1 EXTAL Input Input External Crystal Oscillator Input—This input should be connected to an
8MHz external crystal or ceramic resonator. For more information, please
refer to Section 3.5.

GPIOB2 Input/ Input Port B GPIO—This multiplexed pin is a General Purpose I/O (GPIO) pin that
Output can be programmed as an input or output pin. This I/O can be utilized when
using the on-chip relaxation oscillator so the EXTAL pin is not needed.

56F801 Technical Data, Rev. 17

10 Freescale Semiconductor
 Interrupt and Program Control Signals

Table 2-5 PLL and Clock (Continued)

No. of Signal Signal State
Signal Description
Pins Name Type During Reset

1 XTAL Output Chip- Crystal Oscillator Output—This output should be connected to an 8MHz
driven external crystal or ceramic resonator. For more information, please refer to
Section 3.5.

This pin can also be connected to an external clock source. For more
information, please refer to Section 3.5.3.

GPIOB3 Input/ Input Port B GPIO—This multiplexed pin is a General Purpose I/O (GPIO) pin that
Output can be programmed as an input or output pin. This I/O can be utilized when
using the on-chip relaxation oscillator so the XTAL pin is not needed.

2.4 Interrupt and Program Control Signals

Table 2-6 Interrupt and Program Control Signals

No. of Signal Signal State
Signal Description
Pins Name Type During Reset

1 IRQA Input Input External Interrupt Request A—The IRQA input is a synchronized
(Schmitt) external interrupt request that indicates that an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge- triggered.
1 RESET Input Input Reset—This input is a direct hardware reset on the processor. When
(Schmitt) RESET is asserted low, the controller is initialized and placed in the
Reset state. A Schmitt trigger input is used for noise immunity. When the
RESET pin is deasserted, the initial chip operating mode is latched from
the EXTBOOT pin. The internal reset signal will be deasserted
synchronous with the internal clocks, after a fixed number of internal
clocks.

To ensure complete hardware reset, RESET and TRST should be

asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.

2.5 Pulse Width Modulator (PWM) Signals

Table 2-7 Pulse Width Modulator (PWMA) Signals

No. of Signal Signal State During

Signal Description
Pins Name Type Reset

6 PWMA0-5 Output Tri-stated PWMA0-5— These are six PWMA output pins.

1 FAULTA0 Input Input FAULTA0— This fault input pin is used for disabling selected PWMA
(Schmitt) outputs in cases where fault conditions originate off-chip.

56F801 Technical Data, Rev. 17

Freescale Semiconductor 11
2.6 Serial Peripheral Interface (SPI) Signals
Table 2-8 Serial Peripheral Interface (SPI) Signals
No. of Signal Signal State During
Signal Description
Pins Name Type Reset

1 MISO Input/Output Input SPI Master In/Slave Out (MISO)—This serial data pin is an input to
a master device and an output from a slave device. The MISO line of
a slave device is placed in the high-impedance state if the slave
device is not selected.
Input/Output
GPIOB6 Input Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as input or output pin.

After reset, the default state is MISO.

1 MOSI Input/Output Input SPI Master Out/Slave In (MOSI)—This serial data pin is an output
from a master device and an input to a slave device. The master
device places data on the MOSI line a half-cycle before the clock
edge that the slave device uses to latch the data.

Input/Output Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
GPIOB5 Input be individually programmed as input or output pin.

After reset, the default state is MOSI.

1 SCLK Input/Output Input SPI Serial Clock—In master mode, this pin serves as an output,
clocking slaved listeners. In slave mode, this pin serves as the data
clock input.
Input/Output
GPIOB4 Input Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
be individually programmed as an input or output pin.

After reset, the default state is SCLK.

1 SS Input Input SPI Slave Select—In master mode, this pin is used to arbitrate
multiple masters. In slave mode, this pin is used to select the slave.

Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can
GPIOB7 Input/Output Input be individually programmed as an input or output pin.

After reset, the default state is SS.

56F801 Technical Data, Rev. 17

12 Freescale Semiconductor
 Serial Communications Interface (SCI) Signals

2.7 Serial Communications Interface (SCI) Signals

Table 2-9 Serial Communications Interface (SCI0) Signals

No. of Signal Signal State During
Signal Description
Pins Name Type Reset

1 TXD0 Output Input Transmit Data (TXD0)—SCI0 transmit data output

GPIOB0 Input/Output Input Port B GPIO—This pin is a General Purpose I/O (GPIO) pin that
can be individually programmed as an input or output pin.

After reset, the default state is SCI output.

1 RXD0 Input Input Receive Data (RXD0)—SCI0 receive data input

GPIOB1 Input/Output Input Port B GPIO—This pin is a General Purpose I/O (GPIO) pin that
can be individually programmed as an input or output pin.

After reset, the default state is SCI input.

2.8 Analog-to-Digital Converter (ADC) Signals

Table 2-10 Analog to Digital Converter Signals
No. of Signal Signal State During
Signal Description
Pins Name Type Reset

4 ANA0-3 Input Input ANA0-3—Analog inputs to ADC, channel 1

4 ANA4-7 Input Input ANA4-7—Analog inputs to ADC, channel 2
1 VREF Input Input VREF—Analog reference voltage for ADC. Must be set to
VDDA-0.3V for optimal performance.

2.9 Quad Timer Module Signals

Table 2-11 Quad Timer Module Signals

No. of Signal State During
Signal Type Signal Description
Pins Name Reset

3 TD0-2 Input/Output Input TD0-2—Timer D Channel 0-2

Input/Output
GPIOA0-2 Input Port A GPIO—This pin is a General Purpose I/O (GPIO) pin that
can be individually programmed as an input or output pin.

After reset, the default state is the quad timer input.

56F801 Technical Data, Rev. 17

Freescale Semiconductor 13
2.10 JTAG/OnCE

Table 2-12 JTAG/On-Chip Emulation (OnCE) Signals

No. of Signal Signal State During
Signal Description
Pins Name Type Reset

1 TCK Input Input, pulled Test Clock Input—This input pin provides a gated clock to synchronize the
(Schmitt) low internally test logic and shift serial data to the JTAG/OnCE port. The pin is connected
internally to a pull-down resistor.

1 TMS Input Input, pulled Test Mode Select Input—This input pin is used to sequence the JTAG
(Schmitt) high internally TAP controller’s state machine. It is sampled on the rising edge of TCK and
has an on-chip pull-up resistor.

Note: Always tie the TMS pin to VDD through a 2.2K resistor.

1 TDI Input Input, pulled Test Data Input—This input pin provides a serial input data stream to the
(Schmitt) high internally JTAG/OnCE port. It is sampled on the rising edge of TCK and has an
on-chip pull-up resistor.

1 TDO Output Tri-stated Test Data Output—This tri-statable output pin provides a serial output data
stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR
controller states, and changes on the falling edge of TCK.

1 TRST Input Input, pulled Test Reset—As an input, a low signal on this pin provides a reset signal to
(Schmitt) high internally the JTAG TAP controller. To ensure complete hardware reset, TRST should
be asserted whenever RESET is asserted. The only exception occurs in a
debugging environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert RESET,
but do not assert TRST.

Note: For normal operation, connect TRST directly to VSS. If the design is to be
used in a debugging environment, TRST may be tied to VSS through a 1K resistor.

1 DE Output Output Debug Event—DE provides a low pulse on recognized debug events.

Part 3 Specifications
3.1 General Characteristics
The 56F801 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The
term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology,
to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V- compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.

56F801 Technical Data, Rev. 17

14 Freescale Semiconductor
 General Characteristics

The 56F801 DC and AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.

CAUTION

This device contains protective circuitry to guard against

damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.

Table 3-1 Absolute Maximum Ratings

Characteristic Symbol Min Max Unit

Supply voltage VDD VSS – 0.3 VSS + 4.0 V

All other input voltages, excluding Analog inputs VIN VSS – 0.3 VSS + 5.5V V
Voltage difference VDD to VDDA ΔVDD - 0.3 0.3 V
Voltage difference VSS to VSSA ΔVSS - 0.3 0.3 V

Analog inputs ANA0-7 and VREF VIN VSSA– 0.3 VDDA+ 0.3 V

Analog inputs EXTAL, XTAL VIN VSSA– 0.3 VSSA+ 3.0 V

Current drain per pin excluding VDD, VSS, & PWM ouputs I — 10 mA

Table 3-2 Recommended Operating Conditions

Characteristic Symbol Min Typ Max Unit

Supply voltage, digital VDD 3.0 3.3 3.6 V

Supply Voltage, analog VDDA 3.0 3.3 3.6 V

Voltage difference VDD to VDDA ΔVDD -0.1 - 0.1 V
Voltage difference VSS to VSSA ΔVSS -0.1 - 0.1 V

ADC reference voltage1 VREF 2.7 – 3.3V V

Ambient operating temperature TA –40 – 85 °C

1. VREF must be 0.3 below VDDA.

56F801 Technical Data, Rev. 17

Freescale Semiconductor 15
 Table 3-3 Thermal Characteristics6
Value
Characteristic Comments Symbol Unit Notes
48-pin LQFP

Junction to ambient RθJA 50.6 °C/W 2

Natural convection

Junction to ambient (@1m/sec) RθJMA 47.4 °C/W 2

Junction to ambient Four layer board (2s2p) RθJMA 39.1 °C/W 1,2
Natural convection (2s2p)

Junction to ambient (@1m/sec) Four layer board (2s2p) RθJMA 37.9 °C/W 1,2

Junction to case RθJC 17.3 °C/W 3

Junction to center of case ΨJT 1.2 °C/W 4, 5

I/O pin power dissipation P I/O User Determined W

Power dissipation PD P D = (IDD x VDD + P I/O) W

Junction to center of case PDMAX (TJ - TA) /RθJA W 7

Notes:
1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.
2. Junction to ambient thermal resistance, Theta-JA (RθJA) was simulated to be equivalent to the JEDEC
specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on
a thermal test board with two internal planes (2s2p where s is the number of signal layers and p is the number
of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the
non-single layer boards is Theta-JMA.
3. Junction to case thermal resistance, Theta-JC (RθJC ), was simulated to be equivalent to the measured values
using the cold plate technique with the cold plate temperature used as the "case" temperature. The basic cold
plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal
metric to use to calculate thermal performance when the package is being used with a heat sink.
4. Thermal Characterization Parameter, Psi-JT (ΨJT ), is the "resistance" from junction to reference point
thermocouple on top center of case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction
temperature in steady state customer environments.
5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
board thermal resistance.
6. See Section 5.1 from more details on thermal design considerations.
7. TJ = Junction Temperature
TA = Ambient Temperature

56F801 Technical Data, Rev. 17

16 Freescale Semiconductor
 DC Electrical Characteristics

3.2 DC Electrical Characteristics

Table 3-4 DC Electrical Characteristics

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic Symbol Min Typ Max Unit

Input high voltage (XTAL/EXTAL) VIHC 2.25 — 2.75 V

Input low voltage (XTAL/EXTAL) VILC 0 — 0.5 V

Input high voltage [GPIOB(2:3)]1 VIH[GPIOB(2:3)] 2.0 — 3.6 V

Input low voltage [GPIOB(2:3)]1 VIL[GPIOB(2:3)] -0.3 — 0.8 V

Input high voltage (Schmitt trigger inputs)2 VIHS 2.2 — 5.5 V

Input low voltage (Schmitt trigger inputs)2 VILS -0.3 — 0.8 V

Input high voltage (all other digital inputs) VIH 2.0 — 5.5 V

Input low voltage (all other digital inputs) VIL -0.3 — 0.8 V

Input current high (pullup/pulldown resistors disabled, VIN=VDD) IIH -1 — 1 μA

Input current low (pullup/pulldown resistors disabled, VIN=VSS) IIL -1 — 1 μA

Input current high (with pullup resistor, VIN=VDD) IIHPU -1 — 1 μA

Input current low (with pullup resistor, VIN=VSS) IILPU -210 — -50 μA

Input current high (with pulldown resistor, VIN=VDD) IIHPD 20 — 180 μA

Input current low (with pulldown resistor, VIN=VSS) IILPD -1 — 1 μA

Nominal pullup or pulldown resistor value RPU, RPD 30 KΩ

Output tri-state current low IOZL -10 — 10 μA

Output tri-state current high IOZH -10 — 10 μA

Input current high (analog inputs, VIN=VDDA)3 IIHA -15 — 15 μA

Input current low (analog inputs, VIN=VSSA)3 IILA -15 — 15 μA

Output High Voltage (at IOH) VOH VDD – 0.7 — — V

Output Low Voltage (at IOL) VOL — — 0.4 V

Output source current IOH 4 — — mA

Output sink current IOL 4 — — mA

PWM pin output source current4 IOHP 10 — — mA

PWM pin output sink current5 IOLP 16 — — mA

Input capacitance CIN — 8 — pF

Output capacitance COUT — 12 — pF

56F801 Technical Data, Rev. 17

Freescale Semiconductor 17
 Table 3-4 DC Electrical Characteristics (Continued)
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic Symbol Min Typ Max Unit

VDD supply current IDDT6

Run7 (80MHz operation) — 120 130 mA

Run7 (60MHz operation) — 102 111 mA

Wait8 — 96 102 mA

Stop — 62 70 mA

Low Voltage Interrupt, external power supply9 VEIO 2.4 2.7 3.0 V

Low Voltage Interrupt, internal power supply10 VEIC 2.0 2.2 2.4 V

Power on Reset11 VPOR — 1.7 2.0 V

1. Since the GPIOB[2:3] signals are shared with the XTAL/EXTAL function, these inputs are not 5.5 volt tolerant.
2. Schmitt Trigger inputs are: FAULTA0, IRQA, RESET, TCS, TCK, TMS, TDI, and TRST.
3. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
4. PWM pin output source current measured with 50% duty cycle.
5. PWM pin output sink current measured with 50% duty cycle.
6. IDDT = IDD + IDDA (Total supply current for VDD + VDDA)
7. Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as
inputs; measured with all modules enabled.
8. Wait IDD measured using external square wave clock source (fosc = 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads;
less than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD;
measured with PLL enabled.
9. This low voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same potential as VDD
via separate traces. If VDDA drops below VEIO, an interrupt is generated. Functionality of the device is guaranteed under transient
conditions when VDDA>VEIO (between the minimum specified VDD and the point when the VEIO interrupt is generated).
10. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator
drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated
unless the external power supply drops below the minimum specified value (3.0V).
11. Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping
up, this signal remains active for as long as the internal 2.5V is below 1.5V typical no matter how long the ramp up rate is. The
internally regulated voltage is typically 100 mV less than VDD during ramp up until 2.5V is reached, at which time it self regulates.

56F801 Technical Data, Rev. 17

18 Freescale Semiconductor
 AC Electrical Characteristics

160

IDD Digital IDD Analog IDD Total

120
IDD (mA)

80

40

0 10 20 30 40 50 60 70 80

Freq. (MHz)

Figure 3-1 Maximum Run IDD vs. Frequency (see Note 7. in Table 3-15)

3.3 AC Electrical Characteristics

Timing waveforms in Section 3.3 are tested using the VIL and VIH levels specified in the DC Characteristics
table. In Figure 3-2 the levels of VIH and VIL for an input signal are shown.

VIH Low High

90%
Input Signal Midpoint1 50%
10%
Fall Time VIL Rise Time

Note: The midpoint is VIL + (VIH – VIL)/2.

Figure 3-2 Input Signal Measurement References

Figure 3-3 shows the definitions of the following signal states:

• Active state, when a bus or signal is driven, and enters a low impedance state.
• Tri-stated, when a bus or signal is placed in a high impedance state.
• Data Valid state, when a signal level has reached VOL or VOH.
• Data Invalid state, when a signal level is in transition between VOL and VOH.

56F801 Technical Data, Rev. 17

Freescale Semiconductor 19
 Data1 Valid Data2 Valid Data3 Valid

Data1 Data2 Data3

Data
Data Invalid State
Tri-stated
Data Active Data Active

Figure 3-3 Signal States

3.4 Flash Memory Characteristics

Table 3-5 Flash Memory Truth Table

Mode XE1 YE2 SE3 OE4 PROG5 ERASE6 MAS17 NVSTR8

Standby L L L L L L L L
Read H H H H L L L L
Word Program H H L L H L L H
Page Erase H L L L L H L H
Mass Erase H L L L L H H H
1. X address enable, all rows are disabled when XE = 0
2. Y address enable, YMUX is disabled when YE = 0
3. Sense amplifier enable
4. Output enable, tri-state Flash data out bus when OE = 0
5. Defines program cycle
6. Defines erase cycle
7. Defines mass erase cycle, erase whole block
8. Defines non-volatile store cycle

Table 3-6 IFREN Truth Table

Mode IFREN = 1 IFREN = 0

Read Read information block Read main memory block

Word program Program information block Program main memory block
Page erase Erase information block Erase main memory block
Mass erase Erase both block Erase main memory block

56F801 Technical Data, Rev. 17

20 Freescale Semiconductor
 Flash Memory Characteristics

Table 3-7 Flash Timing Parameters

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic Symbol Min Typ Max Unit Figure

Program time Tprog* 20 – – us Figure 3-4

Erase time Terase* 20 – – ms Figure 3-5

Mass erase time Tme* 100 – – ms Figure 3-6

Endurance1 ECYC 10,000 20,000 – cycles

Data Retention1 DRET 10 30 – years

The following parameters should only be used in the Manual Word Programming Mode

PROG/ERASE to NVSTR set Tnvs* – 5 – us Figure 3-4,

up time Figure 3-5,
Figure 3-6

NVSTR hold time Tnvh* – 5 – us Figure 3-4,

Figure 3-5

NVSTR hold time (mass erase) Tnvh1* – 100 – us Figure 3-6

NVSTR to program set up time Tpgs* – 10 – us Figure 3-4

Recovery time Trcv* – 1 – us Figure 3-4,

Figure 3-5,
Figure 3-6

Cumulative program Thv – 3 – ms Figure 3-4

HV period2

Program hold time3 Tpgh – – – Figure 3-4

Address/data set up time3 Tads – – – Figure 3-4

Address/data hold time3 Tadh – – – Figure 3-4

1. One cycle is equal to an erase program and read.
2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be
programmed twice before next erase.
3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.
*The Flash interface unit provides registers for the control of these parameters.

56F801 Technical Data, Rev. 17

Freescale Semiconductor 21
 IFREN

XADR

XE
Tadh

YADR

YE

DIN

Tads
PROG
Tnvs Tprog Tpgh

NVSTR

Tpgs Tnvh
Trcv
Thv

Figure 3-4 Flash Program Cycle

IFREN

XADR

XE

YE=SE=OE=MAS1=0

ERASE
Tnvs

NVSTR

Tnvh
Terase Trcv

Figure 3-5 Flash Erase Cycle

56F801 Technical Data, Rev. 17

22 Freescale Semiconductor
 External Clock Operation

IFREN

XADR

XE

MAS1

YE=SE=OE=0

ERASE
Tnvs

NVSTR

Tnvh1
Tme Trcv

Figure 3-6 Flash Mass Erase Cycle

3.5 External Clock Operation

The 56F801 device clock is derived from either 1) an internal crystal oscillator circuit working in
conjunction with an external crystal, 2) an external frequency source, or 3) an on-chip relaxation oscillator.
To generate a reference frequency using the internal crystal oscillator circuit, a reference crystal external
to the chip must be connected between the EXTAL and XTAL pins. Paragraphs 3.5.1 and 3.5.4 describe
these methods of clocking. Whichever type of clock derivation is used provides a reference signal to a
phase-locked loop (PLL) within the 56F801. In turn, the PLL generates a master reference frequency that
determines the speed at which chip operations occur.
Application code can be set to change the frequency source between the relaxation oscillator and crystal
oscillator or external source, and power down the relaxation oscillator if desired. Selection of which clock
is used is determined by setting the PRECS bit in the PLLCR (phase-locked loop control register) word
(bit 2). If the bit is set to 1, the external crystal oscillator circuit is selected. If the bit is set to 0, the internal
relaxation oscillator is selected, and this is the default value of the bit when power is first applied.

3.5.1 Crystal Oscillator

The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in Table 3-10. Figure 3-7 shows a recommended crystal
oscillator circuit. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal
parameters determine the component values required to provide maximum stability and reliable start-up.
The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL
pins to minimize output distortion and start-up stabilization time. The internal 56F80x oscillator circuitry

56F801 Technical Data, Rev. 17

Freescale Semiconductor 23
is designed to have no external load capacitors present. As shown in Figure 3-8 no external load capacitors
should be used.
The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a
capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and
process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF
as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as
determined by the following equation:

CL1 * CL2 12 * 12
CL = + Cs = + 3 = 6 + 3 = 9pF
CL1 + CL2 12 + 12

This is the value load capacitance that should be used when selecting a crystal and determining the actual
frequency of operation of the crystal oscillator circuit.

EXTAL XTAL Recommended External Crystal

Parameters:
Rz
Rz = 1 to 3 MΩ
fc = 8MHz (optimized for 8MHz)
fc

Figure 3-7 External Crystal Oscillator Circuit

3.5.2 Ceramic Resonator

It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. In Figure 3-8, a typical ceramic resonator circuit is
shown. Refer to supplier’s recommendations when selecting a ceramic resonator and associated
components. The resonator and components should be mounted as close as possible to the EXTAL and
XTAL pins. The internal 56F80x oscillator circuitry is designed to have no external load capacitors
present. As shown in Figure 3-7 no external load capacitors should be used.

EXTAL XTAL Recommended Ceramic Resonator

Rz Parameters:
Rz = 1 to 3 MΩ
fc = 8MHz (optimized for 8MHz)
fc

Figure 3-8 Connecting a Ceramic Resonator

Note: Freescale recommends only two terminal ceramic resonators vs. three terminal resonators
(which contain an internal bypass capacitor to ground).

56F801 Technical Data, Rev. 17

24 Freescale Semiconductor
 External Clock Operation

3.5.3 External Clock Source

The recommended method of connecting an external clock is given in Figure 3-9. The external clock
source is connected to XTAL and the EXTAL pin is grounded.

56F801
XTAL EXTAL

External Clock VSS

Figure 3-9 Connecting an External Clock Signal

Table 3-8 External Clock Operation Timing Requirements3

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C
Characteristic Symbol Min Typ Max Unit

Frequency of operation (external clock driver)1 fosc 0 — 802 MHz

Clock Pulse Width3, 4 tPW 6.25 — — ns

1. See Figure 3-9 for details on using the recommended connection of an external clock driver.
2. May not exceed 60MHz for the DSP56F801FA60 device.
3. The high or low pulse width must be no smaller than 6.25ns or the chip will not function. However, the high pulse width
does not have to be any particular percent of the low pulse width.
4. Parameters listed are guaranteed by design.

VIH
External 90% 90%
50% 50%
Clock 10% 10%
VIL
tPW tPW

Note: The midpoint is VIL + (VIH – VIL)/2.

Figure 3-10 External Clock Timing

3.5.4 Use of On-Chip Relaxation Oscillator

An internal relaxation oscillator can supply the reference frequency when an external frequency source or
crystal are not used. During a 56F801 boot or reset sequence, the relaxation oscillator is enabled by default,
and the PRECS bit in the PLLCR word is set to 0 (Section 3.5). If an external oscillator is connected, the
relaxation oscillator can be deselected instead by setting the PRECS bit in the PLLCR to 1. When this
occurs, the PRECSS bit in the PLLSR (prescaler clock select status register) data word also sets to 1. If a
changeover between internal and external oscillators is required at startup, internal device circuits

56F801 Technical Data, Rev. 17

Freescale Semiconductor 25
compensate for any asynchronous transitions between the two clock signals so that no glitches occur in the
resulting master clock to the chip. When changing clocks, the user must ensure that the clock source is not
switched until the desired clock is enabled and stable.
To compensate for variances in the device manufacturing process, the accuracy of the relaxation oscillator
can be incrementally adjusted to within ±0.25% of 8MHz by trimming an internal capacitor. Bits 0-7 of
the IOSCTL (internal oscillator control) word allow the user to set in an additional offset (trim) to this
preset value to increase or decrease capacitance. The default value of this trim is 128 units, making the
power-up default capacitor size 432 units. Each unit added or deleted changes the output frequency by
about 0.2%, allowing incremental adjustment until the desired frequency accuracy is achieved.

Table 3-9 Relaxation Oscillator Characteristics

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C
Characteristic Symbol Min Typ Max Unit

Frequency Accuracy1 Δf — +2 +5 %

Frequency Drift over Temp Δf/Δt — +0.1 — %/oC

Frequency Drift over Supply Δf/ΔV — 0.1 — %/V

Trim Accuracy ΔfT — +0.25 — %

1. Over full temperature range.

56F801 Technical Data, Rev. 17

26 Freescale Semiconductor
 External Clock Operation

8.2

8.1

8.0
Output Frequency

7.9

7.8

7.7

7.6
-40 -25 -5 15 35 55 75 85

Temperature (oC)

Figure 3-11 Typical Relaxation Oscillator Frequency vs. Temperature

(Trimmed to 8MHz @ 25oC)

11

10

5
0 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0

Figure 3-12 Typical Relaxation Oscillator Frequency vs. Trim Value @ 25oC

56F801 Technical Data, Rev. 17

Freescale Semiconductor 27
3.5.5 Phase Locked Loop Timing

Table 3-10 PLL Timing

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C
Characteristic Symbol Min Typ Max Unit

External reference crystal frequency for the PLL1 fosc 4 8 10 MHz

PLL output frequency2 fout/2 40 — 803 MHz

PLL stabilization time4 0o to +85oC tplls — 10 — ms

PLL stabilization time4 -40o to 0oC tplls — 100 200 ms

1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the
User Manual. ZCLK = fop
3. Will not exceed 60MHz for the DSP56F801FA60 device.
4. This is the minimum time required after the PLL setup is changed to ensure reliable operation.

56F801 Technical Data, Rev. 17

28 Freescale Semiconductor
 Reset, Stop, Wait, Mode Select, and Interrupt Timing

3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 5
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic Symbol Min Max Unit See

RESET Assertion to Address, Data and Control tRAZ — 21 ns Figure 3-13

Signals High Impedance

Minimum RESET Assertion Duration2 tRA Figure 3-13

OMR Bit 6 = 0 275,000T — ns
OMR Bit 6 = 1 128T — ns

RESET De-assertion to First External Address tRDA 33T 34T ns Figure 3-13
Output
Edge-sensitive Interrupt Request Width tIRW 1.5T — ns Figure 3-14

IRQA, IRQB Assertion to External Data Memory tIDM 15T — ns Figure 3-15
Access Out Valid, caused by first instruction
execution in the interrupt service routine
IRQA, IRQB Assertion to General Purpose Output tIG 16T — ns Figure 3-15
Valid, caused by first instruction execution in the
interrupt service routine
IRQA Low to First Valid Interrupt Vector Address tIRI 13T — ns Figure 3-16
Out recovery from Wait State3

IRQA Width Assertion to Recover from Stop State4 tIW 2T — ns Figure 3-17

Delay from IRQA Assertion to Fetch of first tIF Figure 3-17

instruction (exiting Stop)
OMR Bit 6 = 0 — 275,000T ns
OMR Bit 6 = 1 — 12T ns
Duration for Level Sensitive IRQA Assertion to tIRQ Figure 3-18
Cause the Fetch of First IRQA Interrupt Instruction
(exiting Stop)
OMR Bit 6 = 0 — 275,000T ns
OMR Bit 6 = 1 — 12T ns
Delay from Level Sensitive IRQA Assertion to First tII Figure 3-18
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0 — 275,000T ns
OMR Bit 6 = 1 — 12T ns
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
the minimum required so that the IRQA interrupt is accepted.
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
5. Parameters listed are guaranteed by design.

56F801 Technical Data, Rev. 17

Freescale Semiconductor 29
 RESET

tRA
tRAZ tRDA

A0–A15, First Fetch

D0–D15

PS, DS, First Fetch

RD, WR

Figure 3-13 Asynchronous Reset Timing

IRQA,
IRQB
tIRW

Figure 3-14 External Interrupt Timing (Negative-Edge-Sensitive)

A0–A15,
PS, DS, First Interrupt Instruction Execution
RD, WR
tIDM

IRQA,
IRQB

a) First Interrupt Instruction Execution

General
Purpose
I/O Pin
tIG

IRQA,
IRQB

b) General Purpose I/O

Figure 3-15 External Level-Sensitive Interrupt Timing

56F801 Technical Data, Rev. 17

30 Freescale Semiconductor
 Reset, Stop, Wait, Mode Select, and Interrupt Timing

IRQA,
IRQB
tIRI

A0–A15, First Interrupt Vector

PS, DS, Instruction Fetch
RD, WR

Figure 3-16 Interrupt from Wait State Timing

tIW
IRQA

tIF

A0–A15,
PS, DS, First Instruction Fetch
Not IRQA Interrupt Vector
RD, WR

Figure 3-17 Recovery from Stop State Using Asynchronous Interrupt Timing

tIRQ

IRQA

tII
A0–A15
First IRQA Interrupt
PS, DS,
Instruction Fetch
RD, WR

Figure 3-18 Recovery from Stop State Using IRQA Interrupt Service

56F801 Technical Data, Rev. 17

Freescale Semiconductor 31
3.7 Serial Peripheral Interface (SPI) Timing

Table 3-12 SPI Timing1

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic Symbol Min Max Unit See Figure

Cycle time tC Figures 3-19, 3-20,

Master 50 — ns 3-21, 3-22
Slave 25 — ns
Enable lead time tELD Figure 3-22
Master — — ns
Slave 25 — ns
Enable lag time tELG Figure 3-22
Master — — ns
Slave 100 — ns
Clock (SCK) high time tCH Figures 3-19, 3-20,
Master 17.6 — ns 3-21, 3-22
Slave 12.5 — ns
Clock (SCK) low time tCL Figures 3-19, 3-20,
Master 24.1 — ns 3-21, 3-22
Slave 25 — ns
Data setup time required for inputs tDS Figures 3-19, 3-20,
Master 20 — ns 3-21, 3-22
Slave 0 — ns
Data hold time required for inputs tDH Figures 3-19, 3-20,
Master 0 — ns 3-21, 3-22
Slave 2 — ns
Access time (time to data active from tA Figure 3-22
high-impedance state) 4.8 15 ns
Slave
Disable time (hold time to high-impedance state) tD Figure 3-22
Slave 3.7 15.2 ns
Data Valid for outputs tDV Figures 3-19, 3-20,
Master — 4.5 ns 3-21, 3-22
Slave (after enable edge) — 20.4 ns
Data invalid tDI Figures 3-19, 3-20,
Master 0 — ns 3-21, 3-22
Slave 0 — ns
Rise time tR Figures 3-19, 3-20,
Master — 11.5 ns 3-21, 3-22
Slave — 10.0 ns
Fall time tF Figures 3-19, 3-20,
Master — 9.7 ns 3-21, 3-22
Slave — 9.0 ns
1. Parameters listed are guaranteed by design.

56F801 Technical Data, Rev. 17

32 Freescale Semiconductor
 Serial Peripheral Interface (SPI) Timing

SS SS is held High on master

(Input)
tC tR
tF
tCL
SCLK (CPOL = 0)
(Output) tF
tCH

tCL tR

SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS

MISO
(Input) MSB in Bits 14–1 LSB in

tDI tDV tDI(ref)

MOSI Master MSB out Bits 14–1 Master LSB out

(Output)
tF tR

Figure 3-19 SPI Master Timing (CPHA = 0)

SS SS is held High on master

(Input)
tF
tC
tR

tCL
SCLK (CPOL = 0)
(Output) tCH
tF
tCL

SCLK (CPOL = 1)
(Output)
tCH tDS
tR
tDH
MISO
(Input) MSB in Bits 14–1 LSB in
tDI tDV
tDV(ref)

MOSI Master MSB out Bits 14– 1 Master LSB out

(Output)
tF tR

Figure 3-20 SPI Master Timing (CPHA = 1)

56F801 Technical Data, Rev. 17

Freescale Semiconductor 33
 SS
(Input)
tC
tF tELG
tCL
tR
SCLK (CPOL = 0)
(Input) tCH
tELD
tCL

SCLK (CPOL = 1)
(Input)
tA tCH tR tF
tD

MISO
(Output) Slave MSB out Bits 14–1 Slave LSB out
tDS
tDV tDI tDI
tDH

MOSI MSB in Bits 14–1 LSB in

(Input)

Figure 3-21 SPI Slave Timing (CPHA = 0)

SS
(Input)
tC
tF
tCL tR
SCLK (CPOL = 0)
(Input) tCH
tELD tELG
tCL

SCLK (CPOL = 1)
(Input) tDV
tCH tR
tF tD
tA

MISO
(Output) Slave MSB out Bits 14–1 Slave LSB out

tDS tDV
tDI
tDH

MOSI MSB in Bits 14–1 LSB in

(Input)

Figure 3-22 SPI Slave Timing (CPHA = 1)

56F801 Technical Data, Rev. 17

34 Freescale Semiconductor
 Quad Timer Timing

3.8 Quad Timer Timing

Table 3-13 Timer Timing1, 2

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic Symbol Min Max Unit

Timer input period PIN 4T+6 — ns

Timer input high/low period PINHL 2T+3 — ns

Timer output period POUT 2T — ns

Timer output high/low period POUTHL 1T — ns

1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.

Timer Inputs
PIN PINHL PINHL

Timer Outputs
POUT POUTHL POUTHL

Figure 3-23 Timer Timing

3.9 Serial Communication Interface (SCI) Timing

Table 3-14 SCI Timing4

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic Symbol Min Max Unit

Baud Rate1 BR — (fMAX*2.5)/(80) Mbps

RXD2 Pulse Width RXDPW 0.965/BR 1.04/BR ns

TXD3 Pulse Width TXDPW 0.965/BR 1.04/BR ns

1. fMAX is the frequency of operation of the system clock in MHz.

2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4. Parameters listed are guaranteed by design.

56F801 Technical Data, Rev. 17

Freescale Semiconductor 35
 RXD
SCI receive
data pin
RXDPW
(Input)

Figure 3-24 RXD Pulse Width

TXD
SCI receive
data pin
TXDPW
(Input)

Figure 3-25 TXD Pulse Width

3.10 Analog-to-Digital Converter (ADC) Characteristics

Table 3-15 ADC Characteristics

Characteristic Symbol Min Typ Max Unit

ADC input voltages VADCIN 01 — VREF2 V

Resolution RES 12 — 12 Bits

Integral Non-Linearity3 INL — +/- 4 +/- 5 LSB4

Differential Non-Linearity DNL — +/- 0.9 +/- 1 LSB4

Monotonicity GUARANTEED

ADC internal clock5 fADIC 0.5 — 5 MHz

Conversion range RAD VSSA — VDDA V

Conversion time tADC — 6 — tAIC cycles6

Sample time tADS — 1 — tAIC cycles6

Input capacitance CADI — 5 — pF6

Gain Error (transfer gain)5 EGAIN 1.00 1.10 1.15 —

Offset Voltage5 VOFFSET +10 +230 +325 mV

56F801 Technical Data, Rev. 17

36 Freescale Semiconductor
 Analog-to-Digital Converter (ADC) Characteristics

Table 3-15 ADC Characteristics (Continued)

Characteristic Symbol Min Typ Max Unit

Total Harmonic Distortion5 THD 55 60 — dB

Signal-to-Noise plus Distortion5 SINAD 54 56 — dB

Effective Number of Bits5 ENOB 8.5 9.5 — bit

Spurious Free Dynamic Range5 SFDR 60 65 — dB

Bandwidth BW — 100 — KHz

ADC Quiescent Current (both ADCs) IADC — 50 — mA

VREF Quiescent Current (both ADCs) IVREF — 12 16.5 mA

1. For optimum ADC performance, keep the minimum VADCIN value > 250mV. Inputs less than 250mV volts may convert to
a digital output code of 0 or cause erroneous conversions.
2. VREF must be equal to or less than VDDA - 0.3V and must be greater than 2.7V.
3. Measured in 10-90% range.
4. LSB = Least Significant Bit.
5. Guaranteed by characterization.
6. tAIC = 1/fADIC

ADC analog input 3

1 2 4

1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
4. Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only connected to it at
sampling time. (1pf)

Figure 3-26 Equivalent Analog Input Circuit

56F801 Technical Data, Rev. 17

Freescale Semiconductor 37
3.11 JTAG Timing

Table 3-16 JTAG Timing 1, 3

Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic Symbol Min Max Unit

TCK frequency of operation2 fOP DC 10 MHz

TCK cycle time tCY 100 — ns

TCK clock pulse width tPW 50 — ns

TMS, TDI data setup time tDS 0.4 — ns

TMS, TDI data hold time tDH 1.2 — ns

TCK low to TDO data valid tDV — 26.6 ns

TCK low to TDO tri-state tTS — 23.5 ns

TRST assertion time tTRST 50 — ns

DE assertion time tDE 8T — ns

1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5ns.
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.

tCY
tPW tPW
VIH
VM VM
TCK
(Input)
VIL
VM = VIL + (VIH – VIL)/2

Figure 3-27 Test Clock Input Timing Diagram

56F801 Technical Data, Rev. 17

38 Freescale Semiconductor
 JTAG Timing

TCK
(Input)
tDS tDH

TDI
TMS Input Data Valid
(Input) tDV

TDO
(Output) Output Data Valid
tTS

TDO
(Output)
tDV

TDO Output Data Valid

(Output)

Figure 3-28 Test Access Port Timing Diagram

TRST
(Input)
tTRST

Figure 3-29 TRST Timing Diagram

DE
tDE

Figure 3-30 OnCE—Debug Event

56F801 Technical Data, Rev. 17

Freescale Semiconductor 39
Part 4 Packaging
4.1 Package and Pin-Out Information 56F801
This section contains package and pin-out information for the 48-pin LQFP configuration of the 56F801.

VCAPC1
PWMA5
PWMA4
PWMA3
PWMA2
PWMA1

PWMA0
ANA7
ANA6
ANA5
VDD
VSS
ORIENTATION
TDO MARK ANA4
TD1
PIN 37 ANA3
TD2 PIN 1 VREF
/SS ANA2
MISO ANA1
MOSI ANA0
SCLK FAULTA0
TXDO VSS
VSS VDD
VDD VSSA
PIN 25
RXD0 PIN 13 VDDA
DE RESET
TCS
TCK
TMS
IREQA
TDI

EXTAL
XTAL
TDO
TRST
VCAPC2
VSS
VDD

Figure 4-1 Top View, 56F801 48-pin LQFP Package

56F801 Technical Data, Rev. 17

40 Freescale Semiconductor
 Package and Pin-Out Information 56F801

Table 4-1 56F801 Pin Identification by Pin Number

Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name

1 TD0 13 TCS 25 RESET 37 ANA5

2 TD1 14 TCK 26 VDDA 38 ANA6

3 TD2 15 TMS 27 VSSA 39 ANA7

4 SS 16 IREQA 28 VDD 40 PWMA0

5 MISO 17 TDI 29 VSS 41 VCAPC1

6 MOSI 18 VCAPC2 30 FAULTA0 42 VDD

7 SCLK 19 VSS 31 ANA0 43 VSS

8 TXD0 20 VDD 32 ANA1 44 PWMA1

9 VSS 21 EXTAL 33 ANA2 45 PWMA2

10 VDD 22 XTAL 34 VREF 46 PWMA3

11 RXD0 23 TDO 35 ANA3 47 PWMA4

12 DE 24 TRST 36 ANA4 48 PWMA5

56F801 Technical Data, Rev. 17

Freescale Semiconductor 41
 NOTES:
4X 1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
0.200 AB T-U Z 2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE AB IS LOCATED AT BOTTOM
DETAIL Y OF LEAD AND IS COINCIDENT WITH THE
9 A P LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING
A1 LINE.
48 37 4. DATUMS T, U, AND Z TO BE DETERMINED AT
DATUM PLANE AB.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE AC.
1 36
6. DIMENSIONS A AND B DO NOT INCLUDE
T U MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 PER SIDE. DIMENSIONS
A AND B DO INCLUDE MOLD MISMATCH AND
B V ARE DETERMINED AT DATUM PLANE AB.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
AE AE PROTRUSION. DAMBAR PROTRUSION
B1 SHALL NOT CAUSE THE D DIMENSION TO
V1 EXCEED 0.350.
12 25 8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076.
9. EXACT SHAPE OF EACH CORNER IS
13 24 OPTIONAL.

Z MILLIMETERS
S1 DIM MIN MAX
T, U, Z A 7.000 BSC
A1 3.500 BSC
S B 7.000 BSC
DETAIL Y B1 3.500 BSC
4X C 1.400 1.600
D 0.170 0.270
0.200 AC T-U Z
E 1.350 1.450
F 0.170 0.230
G 0.500 BSC
H 0.050 0.150
J 0.090 0.200
G 0.080 AC K 0.500 0.700
AB L 0 ° 7°
M 12 ° REF
N 0.090 0.160
P 0.250 BSC
R 0.150 0.250
S 9.000 BSC
AD S1 4.500 BSC
AC V 9.000 BSC
V1 4.500 BSC
BASE METAL M° W 0.200 REF
AA 1.000 REF
TOP & BOTTOM
R GAUGE PLANE

N J
0.250

C E
F
D
0.080 M AC T-U Z
SECTION AE-AE H W
L°
DETAIL AD K
CASE 932-03
ISSUE F AA

Figure 4-2 48-pin LQFP Mechanical Information

Please see www.freescale.com for the most current case outline.

56F801 Technical Data, Rev. 17

42 Freescale Semiconductor
 Thermal Design Considerations

Part 5 Design Considerations

5.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
Equation 1: TJ = T A + ( P D × RθJA )

Where:
TA = ambient temperature °C
RθJA = package junction-to-ambient thermal resistance °C/W
PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:
Equation 2: RθJA = R θJC + R θCA

Where:
RθJA = package junction-to-ambient thermal resistance °C/W
RθJC = package junction-to-case thermal resistance °C/W
RθCA = package case-to-ambient thermal resistance °C/W
RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where
the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the
device thermal performance may need the additional modeling capability of a system level thermal
simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether
the thermal performance is adequate, a system level model may be appropriate.
Definitions:
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
• Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the
chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation
across the surface.

56F801 Technical Data, Rev. 17

Freescale Semiconductor 43
 • Measure the thermal resistance from the junction to where the leads are attached to the case. This definition
is approximately equal to a junction to board thermal resistance.
• Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case
determined by a thermocouple.
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.

5.2 Electrical Design Considerations

CAUTION

This device contains protective circuitry to guard against

damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.

Use the following list of considerations to assure correct operation:

• Provide a low-impedance path from the board power supply to each VDD pin on the controller, and from the
board ground to each VSS (GND) pin.
• The minimum bypass requirement is to place 0.1 μF capacitors positioned as close as possible to the
package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of
the ten VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better
performance tolerances.
• Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND)
pins are less than 0.5 inch per capacitor lead.

56F801 Technical Data, Rev. 17

44 Freescale Semiconductor
 Electrical Design Considerations

• Bypass the VDD and VSS layers of the PCB with approximately 100 μF, preferably with a high-grade
capacitor such as a tantalum capacitor.
• Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal.
• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and GND circuits.
• Take special care to minimize noise levels on the VREF, VDDA and VSSA pins.
• Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or
debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means
to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs
that do not require debugging functionality, such as consumer products, TRST should be tied low.
• Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an
interface to this port to allow in-circuit Flash programming.

56F801 Technical Data, Rev. 17

Freescale Semiconductor 45
Part 6 Ordering Information
Table 6-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor
sales office or authorized distributor to determine availability and to order parts.

Table 6-1 56F801 Ordering Information

Ambient
Supply Pin
Part Package Type Frequency Order Number
Voltage Count
(MHz)

56F801 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) 48 80 DSP56F801FA80
56F801 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) 48 60 DSP56F801FA60

56F801 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) 48 80 DSP56F801FA80E*
56F801 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) 48 60 DSP56F801FA60E*

*This package is RoHS compliant.

56F801 Technical Data, Rev. 17

46 Freescale Semiconductor
 Electrical Design Considerations

56F801 Technical Data, Rev. 17

Freescale Semiconductor 47
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Inc. All other product or service names are the property of their respective owners.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2005. All rights reserved.

DSP56F801
Rev. 17
09/2007