56854

Data Sheet
Technical Data

56800E
16-bit Digital Signal Controllers

DSP56854
Rev. 6
01/2007

freescale.com
56854 General Description

• 120 MIPS at 120MHz • Serial Port Interface (SPI)

• 16K x 16-bit Program SRAM • 8-bit Parallel Host Interface
• 16K x 16-bit Data SRAM • General Purpose 16-bit Quad Timer
• 1K x 16-bit Boot ROM • JTAG/Enhanced On-Chip Emulation (OnCE™) for
• Access up to 2M words of program or 8M data memory unobtrusive, real-time debugging
• Chip Select Logic for glue-less interface to ROM and • Computer Operating Properly (COP)/Watchdog Timer
SRAM • Time-of-Day (TOD)
• Six (6) independent channels of DMA • 128 LQFP package
• Enhanced Synchronous Serial Interfaces (ESSI) • Up to 41 GPIO
• Two (2) Serial Communication Interfaces (SCI)

VDDIO VDD VSSIO VSS VDDA VSSA

6
11 6 10 6

JTAG/
Enhanced
16-Bit
OnCE DSP56800E Core
Program Controller Address Data ALU Bit
and Generation Unit 16 x 16 + 36 → 36-Bit MAC Manipulation
Hardware Looping Unit Three 16-bit Input Registers Unit
Four 36-bit Accumulators

PAB
PDB
CDBR
CDBW

Memory
XDB2
Program Memory XAB1
16,384 x 16 SRAM
XAB2
System DMA
Boot ROM PAB Bus 6 channel
Core CLK

1024 x 16 ROM
PDB
Control
Data Memory CDBR
16,384 x 16 SRAM
CDBW
DMA Requests

IPBus Bridge (IPBB)

IPWDB

IPRDB
IPAB

Decoding
Peripherals IPBus CLK
POR
3
CLKO
MODEA-C or
System (GPIOH0-H2)
COP/TOD CLK Integration
RSTO
A0-20 [20:0] External Address Module
Bus Switch RESET

D0-D15 [15:0] External Data External Bus

Bus Switch Interface Unit EXTAL
2 SCI ESSI0 Quad SPI Host Interrupt COP/ Time Clock
RD Enable or or Timer or Interface Controller Watch- of Generator XTAL
WR Enable Bus Control GPIOE GPIOC or GPIOF or dog Day
GPIOG GPIOB OSC PLL
CS0-CS3[3:0] or
GPIOA0-GPIOA3[3:0]
4 6 4 4 16
IRQA
IRQB

56854 Block Diagram

56854 Technical Data, Rev. 6

Freescale Semiconductor 3
Part 1 Overview
1.1 56854 Features
1.1.1 Digital Signal Processing Core
• Efficient 16-bit engine with dual Harvard architecture
• 120 Million Instructions Per Second (MIPS) at 120MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four (4) 36-bit accumulators including extension bits
• 16-bit bidirectional shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three (3) internal address buses and one (1) external address bus
• Four (4) internal data buses and one (1) external data bus
• Instruction set supports both DSP and controller functions
• Four (4) hardware interrupt levels
• Five (5) software interrupt levels
• Controller-style addressing modes and instructions for compact code
• Efficient C Compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/Enhanced OnCE debug programming interface

1.1.2 Memory
• Harvard architecture permits up to three (3) simultaneous accesses to program and data memory
• On-Chip Memory
— 16K × 16-bit Program SRAM
— 16K × 16-bit Data SRAM
— 1K × 16-bit Boot ROM
• Off-Chip Memory Expansion (EMI)
— Access up to 2M words of program memory or up to 8M words of data memory
— Chip Select Logic for glue-less interface to ROM and SRAM

1.1.3 Peripheral Circuits for 56854

• General Purpose 16-bit Quad Timer*
• Two (2) Serial Communication Interfaces (SCI)*
• Serial Peripheral Interface (SPI) Port*
• Enhanced Synchronous Serial Interface (ESSI) module*
• Computer Operating Properly (COP)/Watchdog Timer

56854 Technical Data, Rev. 6

4 Freescale Semiconductor
 56854 Description

• JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging

• Six (6) independent channels of DMA
• 8-bit Parallel Host Interface*
• Time of Day
• Up to 41 GPIO
* Each peripheral I/O can be used alternately as a General Purpose I/O if not needed

1.1.4 Energy Information

• Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs
• Wait and Stop modes available

1.2 56854 Description

The 56854 is a member of the 56800E core-based family of controllers. It combines, on a single chip, the
processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a
flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56854 is well-suited for many applications. The
56854 includes many peripherals that are especially useful for low-end Internet appliance applications and
low-end client applications such as telephony; portable devices; Internet audio; and point-of-sale systems,
such as noise suppression; ID tag readers; sonic/subsonic detectors; security access devices; remote
metering; sonic alarms.
The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact DSP and
control code. The instruction set is also highly efficient for C Compilers, enabling rapid development of
optimized control applications.
The 56854 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56854 also provides two external
dedicated interrupt lines, and up to 41 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56854 controller includes 16K words of Program RAM, 16K words of Data RAM, and 1K words of
Boot ROM. It also supports program execution from external memory.
This controller also provides a full set of standard programmable peripherals that include an 8-bit parallel
Host Interface, Enhanced Synchronous Serial Interface (ESSI), one Serial Peripheral Interface (SPI), two
Serial Communications Interfaces (SCIs), and a Quad Timer. The Host Interface, ESSI, SPI, SCI, four chip
selects and quad timer can be used as General Purpose Input/Outputs (GPIOs) if its primary function is not
required.

56854 Technical Data, Rev. 6

Freescale Semiconductor 5
1.3 State of the Art Development Environment
• Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
• The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.

1.4 Product Documentation

The four documents listed in Table 1-1 are required for a complete description of and proper design with
the 56854. Documentation is available from local Freescale distributors, Freescale Semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.

Table 1-1 56854 Chip Documentation

Topic Description Order Number

DSP56800E Detailed description of the 56800E architecture, 16-bit DSP56800ERM

Reference Manual controller core processor and the instruction set
DSP56854 Detailed description of memory, peripherals, and DSP5685xUM
User’s Manual interfaces of the 56854
DSP56854 Electrical and timing specifications, pin descriptions, DSP56854
Technical Data Sheet and package descriptions
DSP56854 Details any chip issues that might be present DSP56854E
Errata

56854 Technical Data, Rev. 6

6 Freescale Semiconductor
 Data Sheet Conventions

1.5 Data Sheet Conventions

This data sheet uses the following conventions:

OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.

“asserted” A high true (active high) signal is high or a low true (active low) signal is low.

“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.

Examples: Signal/Symbol Logic State Signal State Voltage1

PIN True Asserted VIL/VOL

PIN False Deasserted VIH/VOH

PIN True Asserted VIH/VOH

PIN False Deasserted VIL/VOL

1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.

56854 Technical Data, Rev. 6

Freescale Semiconductor 7
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56854 are organized into functional groups, as shown in Table 2-1 and
as illustrated in Figure 2-1. In Table 3-1, each table row describes the package pin and the signal or
signals present.

Table 2-1 Functional Group Pin Allocations

Functional Group Number of Pins

Power (VDD, VDDIO, or VDDA) (6, 11, 1)1

Ground (VSS, VSSIO,or VSSA) (6, 10, 1)1

PLL and Clock 3

External Bus Signals 39

External Chip Select* 4

Interrupt and Program Control 72

Host Interface (HI)* 163

Enhanced Synchronous Serial Interface (ESSI0) Port* 6

Serial Communications Interface (SCI0) Ports* 2

Serial Communications Interface (SCI1) Ports* 2

Serial Peripheral Interface (SPI) Port* 4

Quad Timer Module Port* 4

JTAG/Enhanced On-Chip Emulation (EOnCE) 6

*Alternately, GPIO pins

1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA
2. MODA, MODB and MODC can be used as GPIO after the bootstrap process has completed.
3. The following Host Interface signals are multiplexed: HRWB to HRD, HDS to HWR, HREQ to HTRQ and HACK to HRRQ.

56854 Technical Data, Rev. 6

8 Freescale Semiconductor
 Introduction

RXDO (GPIOE0)
VDD 1 SCI 0
Logic 6 TXDO (GPIOE1)
Power VSS 1
6

RXD1 (GPIOE2)
1 SCI 2
TXD1 (GPIOE3)
VDDIO 1
I/O 11
Power VSSIO
10 STD0 (GPIOC0)
1
Analog VDDA SRD0 (GPIOC1)
1
Power1 1 SCK0 (GPIOC2)
VSSA 1 ESSI 0
1 SC00 (GPIOC3)
1
SC01 (GPIOC4)
1
56854 SC02 (GPIOC5)
A0 - A20 1
21
D0 - D15
External 16
Bus RD
1
WR
1

Chip
Select CS0 - CS3 (GPIOA0 - A3) 4

HD0 - HD7 (GPIOB0 - B7)

8 MISO (GPIOF0)
HA0 - HA2 (GPIOB8 - B10) 1
3
MOSI (GPIOF1)
HRWB (HRD) (GPIOB11) 1
1 SPI
Host SCK (GPIOF2)
HDS (HWR) (GPIOB12) 1
Interface 1
SS (GPIOF3)
HCS (GPIOB13) 1
1
HREQ (HTRQ) (GPIOB14)
1
HACK (HRRQ) (GPIOB15)
1 XTAL
1
EXTAL PLL /
Timer 1
TIO0 - TIO3 (GPIOG0 - G3) Clock
Module 4 CLKO
1

IRQA TCK
1
1
IRQB TDI
1 1
TDO JTAG /
Interrupt / MODA, MODB, MODC 1
(GPIOH0 - H2) Enhanced
Program 3 TMS OnCE
1
Control RESET TRST
1 1
RSTO DE
1 1

Figure 2-1 56854 Signals Identified by Functional Group2

1. Specifically for PLL, OSC, and POR.

2. Alternate pin functions are shown in parentheses.

56854 Technical Data, Rev. 6

Freescale Semiconductor 9
Part 3 Signals and Package Information
All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are
enabled by default. Exceptions:
1. When a pin has GPIO functionality, the pull-up may be disabled under software control.
2. MODE A, MODE B and MODE C pins have no pull-up.
3. TCK has a weak pull-down circuit always active.
4. Bidirectional I/O pullups automatically disable when the output is enabled.
This table is presented consistently with the Signals Identified by Functional Group figure.
1. BOLD entries in the Type column represents the state of the pin just out of reset.
2. Output(Z) means an output in a High-Z condition.

Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP

Pin No. Signal Name Type Description

13 VDD VDD Power (VDD)—These pins provide power to the internal structures
of the chip, and should all be attached to VDD.
47 VDD

64 VDD

79 VDD

80 VDD

112 VDD

14 VSS VSS Ground (VSS)—These pins provide grounding for the internal
structures of the chip and should all be attached to VSS.
48 VSS

63 VSS

81 VSS

96 VSS

113 VSS

56854 Technical Data, Rev. 6

10 Freescale Semiconductor
 Introduction

Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)

Pin No. Signal Name Type Description

5 VDDIO VDDIO Power (VDDIO)—These pins provide power for all I/O and ESD
structures of the chip, and should all be attached to VDDIO (3.3V).
18 VDDIO

41 VDDIO

55 VDDIO

61 VDDIO

72 VDDIO

91 VDDIO

92 VDDIO

100 VDDIO

114 VDDIO

124 VDDIO

6 VSSIO VSSIO Ground (VSSIO)—These pins provide grounding for all I/O and ESD
structures of the chip and should all be attached to VSS.
19 VSSIO

42 VSSIO

56 VSSIO

62 VSSIO

74 VSSIO

93 VSSIO

102 VSSIO

115 VSSIO

125 VSSIO

22 VDDA VDDA Analog Power (VDDA)—These pins supply an analog power

source.

23 VSSA VSSA Analog Ground (VSSA)—This pin supplies an analog ground.

56854 Technical Data, Rev. 6

Freescale Semiconductor 11
 Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)

Pin No. Signal Name Type Description

9 A0 Output(Z) Address Bus (A0-A20)—These signals specify a word address for

external program or data memory access.
10 A1

11 A2

12 A3

26 A4

27 A5

28 A6

29 A7

43 A8

44 A9

45 A10

46 A11

57 A12

58 A13

59 A14

60 A15

67 A16

68 A17

69 A18

70 A19

71 A20

56854 Technical Data, Rev. 6

12 Freescale Semiconductor
 Introduction

Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)

Pin No. Signal Name Type Description

73 D0 Input/Output(Z) Data Bus (D0-D15)—These pins provide the bidirectional data for
external program or data memory accesses.
86 D1

87 D2

88 D3

89 D4

90 D5

107 D6

108 D7

109 D8

110 D9

111 D10

122 D11

123 D12

126 D13

127 D14

128 D15

7 RD Output Read Enable (RD) —is asserted during external memory read
cycles.

This signal is pulled high during reset.

8 WR Output Write Enable (WR)— is asserted during external memory write

cycles.

This signal is pulled high during reset.

75 CS0 Output External Chip Select (CS0)—This pin is used as a dedicated GPIO.

GPIOA0 Input/Output Port A GPIO (0) —This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.

76 CS1 Output External Chip Select (CS1)—This pin is used as a dedicated GPIO.

GPIOA1 Input/Output Port A GPIO (1) —This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.

56854 Technical Data, Rev. 6

Freescale Semiconductor 13
 Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)

Pin No. Signal Name Type Description

77 CS2 Output External Chip Select (CS2)—This pin is used as a dedicated GPIO.

GPIOA2 Input/Output Port A GPIO (2) —This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.

78 CS3 Output External Chip Select (CS3)—This pin is used as a dedicated GPIO.

GPIOA3 Input/Output Port A GPIO (3)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.

30 HD0 Input Host Address (HD0)—This input provides data selection for HI
registers.

This pin is disconnected internally during reset.

GPIOB0 Input/Output Port B GPIO (0)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.

31 HD1 Input Host Address (HD1)—This input provides data selection for HI
registers.

This pin is disconnected internally during reset.

GPIOB1 Input/Output Port B GPIO (1)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.

32 HD2 Input Host Address (HD2)—This input provides data selection for HI
registers.

This pin is disconnected internally during reset.

GPIOB2 Input/Output Port B GPIO (2)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.

36 HD3 Input Host Address (HD3)—This input provides data selection for HI
registers.

This pin is disconnected internally during reset.

GPIOB3 Input/Output Port B GPIO (3)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.

37 HD4 Input Host Address (HD4)—This input provides data selection for HI
registers.

This pin is disconnected internally during reset.

GPIOB4 Input/Output Port B GPIO (4)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.

56854 Technical Data, Rev. 6

14 Freescale Semiconductor
 Introduction

Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)

Pin No. Signal Name Type Description

38 HD5 Input Host Address (HD5)—This input provides data selection for HI
registers.

This pin is disconnected internally during reset.

GPIOB5 Input/Output Port B GPIO (5)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.

39 HD6 Input Host Address (HD6)—This input provides data selection for HI
registers.

This pin is disconnected internally during reset.

GPIOB6 Input/Output Port B GPIO (6)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.

40 HD7 Input Host Address (HD7)—This input provides data selection for HI
registers.

This pin is disconnected internally during reset.

GPIOB7 Input/Output Port B GPIO (7)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.

82 HA0 Input Host Address (HA0)—These inputs provide the address selection
for HI registers.

These pins are disconnected internally during reset.

GPIOB8 Input/Output Port B GPIO (8)—These pins are General Purpose I/O (GPIO) pins
when not configured for host port usage.

83 HA1 Input Host Address (HA0)—These inputs provide the address selection
for HI registers.

These pins are disconnected internally during reset.

GPIOB9 Input/Output Port B GPIO (9)—These pins are General Purpose I/O (GPIO) pins
when not configured for host port usage.

84 HA2 Input Host Address (HA0)—These inputs provide the address selection
for HI registers.

These pins are disconnected internally during reset.

GPIOB10 Input/Output Port B GPIO (10)—These pins are General Purpose I/O (GPIO)
pins when not configured for host port usage.

56854 Technical Data, Rev. 6

Freescale Semiconductor 15
 Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)

Pin No. Signal Name Type Description

85 HRWB Input Host Read/Write (HRWB)—When the HI08 is programmed to

interface to a single-data-strobe host bus and the HI function is
selected, this signal is the Read/Write input.

These pins are disconnected internally.

HRD Input Host Read Data (HRD)—This signal is the Read Data input when
the HI08 is programmed to interface to a double-data-strobe host
bus and the HI function is selected.

GPIOB11 Input/Output Port B GPIO (11)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.

103 HDS Input Host Data Strobe (HDS)—When the HI08 is programmed to
interface to a single-data-strobe host bus and the HI function is
selected, this input enables a data transfer on the HI when HCS is
asserted.

These pins are disconnected internally.

HWR Input Host Write Enable (HWR)—This signal is the Write Data input
when the HI08 is programmed to interface to a double-data-strobe
host bus and the HI function is selected.

GPIOB12 Input/Output Port B GPIO (12)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.

104 HCS Input Host Chip Select (HCS)—This input is the chip select input for the
Host Interface.

These pins are disconnected internally.

GPIOB13 Input/Output Port B GPIO (13)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.

105 HREQ Open Drain Host Request (HREQ)—When the HI08 is programmed for
Output HRMS=0 functionality (typically used on a single-data-strobe bus),
this open drain output is used by the HI to request service from the
host processor. The HREQ may be connected to an interrupt
request pin of a host processor, a transfer request of a DMA
controller, or a control input of external circuitry.

These pins are disconnected internally.

HTRQ Open Drain Transmit Host Request (HTRQ)—This signal is the Transmit Host
Output Request output when the HI08 is programmed for HRMS=1
functionality and is typically used on a double-data-strobe bus.

GPIOB14 Input/Output Port B GPIO (14)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.

56854 Technical Data, Rev. 6

16 Freescale Semiconductor
 Introduction

Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)

Pin No. Signal Name Type Description

106 HACK Input Host Acknowledge (HACK)—When the HI08 is programmed for
HRMS=0 functionality (typically used on a single-data-strobe bus),
this input has two functions: (1) provide a Host Acknowledge signal
for DMA transfers or (2) to control handshaking and provide a Host
Interrupt Acknowledge compatible with the MC68000 family
processors.

These pins are disconnected internally.

HRRQ Open Drain Receive Host Request (HRRQ)—This signal is the Receive Host
Output Request output when the HI08 is programmed for HRMS=1
functionality and is typically used on a double-data-strobe bus.

GPIOB15 Input/Output Port B GPIO(15)—This pin is a General Purpose I/O (GPIO) pin
when not configured for host port usage.

101 TIO0 Input/Output Timer Input/Outputs (TIO0)—This pin can be independently

configured to be either a timer input source or an output flag.

GPIOG0 Input/Output Port G GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as an input or output pin.

99 TIO1 Input/Output Timer Input/Outputs (TIO1)—This pin can be independently

configured to be either a timer input source or an output flag.

GPIOG1 Input/Output Port G GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as an input or output pin.

98 TIO2 Input/Output Timer Input/Outputs (TIO2)—This pin can be independently

configured to be either a timer input source or an output flag.

GPIOG2 Input/Output Port G GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as an input or output pin.

97 TIO3 Input/Output Timer Input/Outputs (TIO3)—This pin can be independently

configured to be either a timer input source or an output flag.

GPIOG3 Input/Output Port G GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as an input or output pin.

20 IRQA Input External Interrupt Request A and B—The IRQA and IRQB inputs
are asynchronous external interrupt requests that indicate that an
21 IRQB external device is requesting service. A Schmitt trigger input is used
for noise immunity. They can be programmed to be level-sensitive
or negative-edge- triggered. If level-sensitive triggering is selected,
an external pull-up resistor is required for Wired-OR operation.

56854 Technical Data, Rev. 6

Freescale Semiconductor 17
 Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)

Pin No. Signal Name Type Description

15 MODA Input Mode Select (MODA)—During the bootstrap process MODA

selects one of the eight bootstrap modes.

GPIOH0 Input/Output Port H GPIO (0)—This pin is a General Purpose I/O (GPIO) pin
after the bootstrap process has completed.

16 MODB Input Mode Select (MODB)—During the bootstrap process MODB

selects one of the eight bootstrap modes.

GPIOH1 Input/Output Port H GPIO (1)—This pin is a General Purpose I/O (GPIO) pin
after the bootstrap process has completed.

17 MODC Input Mode Select (MODC)—During the bootstrap process MODC

selects one of the eight bootstrap modes.

GPIOH2 Input/Output Port H GPIO (2)—This pin is a General Purpose I/O (GPIO) pin
after the bootstrap process has completed.

35 RESET Input Reset (RESET)—This input is a direct hardware reset on the

processor. When RESET is asserted low, the device is initialized
and placed in the Reset state. A Schmitt trigger input is used for
noise immunity. When the RESET pin is deasserted, the initial chip
operating mode is latched from the MODA, MODB, and MODC
pins.

To ensure complete hardware reset, RESET and TRST should be

asserted together. The only exception occurs in a debugging
environment when a hardware reset is required and it is necessary
not to reset the JTAG/Enhanced OnCE module. In this case, assert
RESET, but do not assert TRST.

34 RSTO Output Reset Output (RSTO)—This output is asserted on any reset

condition (external reset, low voltage, software or COP).

65 RXD0 Input Serial Receive Data 0 (RXD0)—This input receives byte-oriented

serial data and transfers it to the SCI 0 receive shift register.

GPIOE0 Input/Output Port E GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.

66 TXD0 Output(Z) Serial Transmit Data 0 (TXD0)—This signal transmits data from
the SCI 0 transmit data register.

GPIOE1 Input/Output Port E GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.

94 RXD1 Input Serial Receive Data 1 (RXD1)—This input receives byte-oriented

serial data and transfers it to the SCI 1 receive shift register.

GPIOE2 Input/Output Port E GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.

56854 Technical Data, Rev. 6

18 Freescale Semiconductor
 Introduction

Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)

Pin No. Signal Name Type Description

95 TXD1 Output(Z) Serial Transmit Data 1 (TXD1)—This signal transmits data from
the SCI 1 transmit data register.

GPIOE3 Input/Output Port E GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.

116 STD0 Output ESSI Transmit Data (STD0)—This output pin transmits serial data
from the ESSI Transmitter Shift Register.

GPIOC0 Input/Output Port C GPIO (0)—This pin is a General Purpose I/O (GPIO) pin
when the ESSI is not in use.

117 SRD0 Input ESSI Receive Data (SRD0)—This input pin receives serial data
and transfers the data to the ESSI Receive Shift Register.

GPIOC1 Input/Output Port C GPIO (1)—This pin is a General Purpose I/O (GPIO) pin
when the ESSI is not in use.

118 SCK0 Input/Output ESSI Serial Clock (SCK0)—This bidirectional pin provides the
serial bit rate clock for the transmit section of the ESSI. The clock
signal can be continuous or gated and can be used by both the
transmitter and receiver in synchronous mode.

GPIOC2 Input/Output Port C GPIO (2)—This pin is a General Purpose I/O (GPIO) pin
when the ESSI is not in use.

119 SC00 Input/Output ESSI Serial Control Pin 0 (SC00)—The function of this pin is
determined by the selection of either synchronous or asynchronous
mode. For asynchronous mode, this pin will be used for the receive
clock I/O. For synchronous mode, this pin is used either for
transmitter1 output or for serial I/O flag 0.

GPIOC3 Input/Output Port C GPIO (3)—This pin is a General Purpose I/O (GPIO) pin
when the ESSI is not in use.

120 SC01 Input/Output ESSI Serial Control Pin 1 (SC01)—The function of this pin is
determined by the selection of either synchronous or asynchronous
mode. For asynchronous mode, this pin is the receiver frame sync
I/O. For synchronous mode, this pin is used either for transmitter2
output or for serial I/O flag 1.

GPIOC4 Input/Output Port C GPIO (4)—This pin is a General Purpose I/O (GPIO) pin
when the ESSI is not in use.

56854 Technical Data, Rev. 6

Freescale Semiconductor 19
 Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)

Pin No. Signal Name Type Description

121 SC02 Input/Output ESSI Serial Control Pin 2 (SC02)—This pin is used for frame sync
I/O. SC02 is the frame sync for both the transmitter and receiver in
synchronous mode and for the transmitter only in asynchronous
mode. When configured as an output, this pin is the internally
generated frame sync signal. When configured as an input, this pin
receives an external frame sync signal for the transmitter (and the
receiver in synchronous operation).

GPIOC5 Input /Output Port C GPIO (5)—This pin is a General Purpose I/O (GPIO) pin
when the ESSI is not in use.

1 MISO Input/Output SPI Master In/Slave Out (MISO)—This serial data pin is an input to
a master device and an output from a slave device. The MISO line
of a slave device is placed in the high-impedance state if the slave
device is not selected. The driver on this pin can be configured as
an open-drain driver by the SPI’s Wired-OR mode (WOM) bit when
this pin is configured for SPI operation.

GPIOF0 Input/Output Port F GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that
can be individually programmed as input or output pin.

2 MOSI Input/Output (Z) SPI Master Out/Slave In (MOSI)—This serial data pin is an output
from a master device and an input to a slave device. The master
device places data on the MOSI line a half-cycle before the clock
edge that the slave device uses to latch the data. The driver on this
pin can be configured as an open-drain driver by the SPI’s WOM bit
when this pin is configured for SPI operation.

GPIOF1 Input/Output Port F GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.

3 SCK Input/Output SPI Serial Clock (SCK)—This bidirectional pin provides a serial bit
rate clock for the SPI. This gated clock signal is an input to a slave
device and is generated as an output by a master device. Slave
devices ignore the SCK signal unless the SS pin is active low. In
both master and slave SPI devices, data is shifted on one edge of
the SCK signal and is sampled on the opposite edge, where data is
stable. The driver on this pin can be configured as an open-drain
driver by the SPI’s WOM bit when this pin is configured for SPI
operation. When using Wired-OR mode, the user must provide an
external pull-up device.

GPIOF2 Input/Output Port F GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that
can be individually programmed as input or output pin.

56854 Technical Data, Rev. 6

20 Freescale Semiconductor
 Introduction

Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)

Pin No. Signal Name Type Description

4 SS Input SPI Slave Select (SS)—This input pin selects a slave device before
a master device can exchange data with the slave device. SS must
be low before data transactions and must stay low for the duration
of the transaction. The SS line of the master must be held high.

GPIOF3 Input/Output Port F GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.

24 XTAL Input/Output Crystal Oscillator Output (XTAL)—This output connects the

internal crystal oscillator output to an external crystal. If an external
clock source other than a crystal oscillator is used, XTAL must be
used as the input.

25 EXTAL Input External Crystal Oscillator Input (EXTAL)—This input should be

connected to an external crystal. If an external clock source other
than a crystal oscillator is used, EXTAL must be tied off. See
Section 4.5.2

33 CLKO Output Clock Output (CLKO)—This pin outputs a buffered clock signal.
When enabled, this signal is the system clock divided by four.

54 TCK Input Test Clock Input (TCK)—This input pin provides a gated clock to
synchronize the test logic and to shift serial data to the
JTAG/Enhanced OnCE port. The pin is connected internally to a
pull-down resistor.

52 TDI Input Test Data Input (TDI)—This input pin provides a serial input data
stream to the JTAG/Enhanced OnCE port. It is sampled on the
rising edge of TCK and has an on-chip pull-up resistor.

51 TDO Output (Z) Test Data Output (TDO)—This tri-statable output pin provides a
serial output data stream from the JTAG/Enhanced OnCE port. It is
driven in the Shift-IR and Shift-DR controller states, and changes on
the falling edge of TCK.

53 TMS Input Test Mode Select Input (TMS)—This input pin is used to sequence
the JTAG TAP controller’s state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.

Note: Always tie the TMS pin to VDD through a 2.2K resistor.

56854 Technical Data, Rev. 6

Freescale Semiconductor 21
 Table 3-1. 56854 Signal and Package Information for the 128-pin LQFP (Continued)

Pin No. Signal Name Type Description

50 TRST Input Test Reset (TRST)—As an input, a low signal on this pin provides a
reset signal to the JTAG TAP controller. To ensure complete
hardware reset, TRST should be asserted whenever RESET is
asserted. The only exception occurs in a debugging environment,
since the Enhanced OnCE/JTAG module is under the control of the
debugger. In this case it is not necessary to assert TRST when
asserting RESET . Outside of a debugging environment RESET
should be permanently asserted by grounding the signal, thus
disabling the Enhanced OnCE/JTAG module on the device.

Note: For normal operation, connect TRST directly to VSS. If the

design is to be used in a debugging environment, TRST may be tied to VSS
through a 1K resistor.

49 DE Input/Output Debug Event (DE)—This is an open-drain, bidirectional, active low

signal. As an input, it is a means of entering debug mode of
operation from an external command controller. As an output, it is a
means of acknowledging that the chip has entered debug mode.

This pin is connected internally to a weak pull-up resistor.

56854 Technical Data, Rev. 6

22 Freescale Semiconductor
 General Characteristics

Part 4 Specifications
4.1 General Characteristics
The 56854 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The
term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a
mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V
and 5V- compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of
3.3V ± 10% during normal operation without causing damage). This 5V tolerant capability therefore
offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.

Absolute maximum ratings given in Table 4-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.

The 56854 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.

CAUTION

This device contains protective circuitry to guard

against damage due to high static voltage or
electrical fields. However, normal precautions are
advised to avoid application of any voltages higher
than maximum rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate voltage level.

56854 Technical Data, Rev. 6

Freescale Semiconductor 23
 Table 4-1 Absolute Maximum Ratings
Characteristic Symbol Min Max Unit

Supply voltage, core VDD1 VSS – 0.3 VSS + 2.0 V

Supply voltage, IO VDDIO2 VSSIO – 0.3 VSSIO + 4.0 V

Supply voltage, analog VDDIO2 VSSA – 0.3 VDDA + 4.0

Digital input voltages VIN VSSIO – 0.3 VSSIO + 5.5 V

Analog input voltages (XTAL, EXTAL) VINA VSSA – 0.3 VDDA + 0.3

Current drain per pin excluding VDD, GND I — 8 mA

Junction temperature TJ -40 120 °C

Storage temperature range TSTG -55 150 °C

1. VDD must not exceed VDDIO
2. VDDIO and VDDA must not differ by more that 0.5V

Table 4-2 Recommended Operating Conditions

Characteristic Symbol Min Max Unit

Supply voltage for Logic Power VDD 1.62 1.98 V

Supply voltage for I/O Power VDDIO 3.0 3.6 V

Supply voltage for Analog Power VDDA 3.0 3.6 V

Ambient operating temperature TA -40 85 °C

PLL clock frequency1 fpll — 240 MHz

Operating Frequency2 fop — 120 MHz

Frequency of peripheral bus fipb — 60 MHz

Frequency of external clock fclk — 240 MHz

Frequency of oscillator fosc 2 4 MHz

Frequency of clock via XTAL fxtal — 240 MHz

Frequency of clock via EXTAL fextal 2 4 MHz

1. Assumes clock source is direct clock to EXTAL or crystal oscillator running 2-4MHz. PLL must be enabled, locked, and
selected. The actual frequency depends on the source clock frequency and programming of the CGM module.
2. Master clock is derived from on of the following four sources:
fclk = fxtal when the source clock is the direct clock to EXTAL
fclk = fpll when PLL is selected
fclk = fosc when the source clock is the crystal oscillator and PLL is not selected
fclk = fextal when the source clock is the direct clock to EXTAL and PLL is not selected

56854 Technical Data, Rev. 6

24 Freescale Semiconductor
 DC Electrical Characteristics

Table 4-3 Thermal Characteristics1

128-pin LQFP
Characteristic
Symbol Value Unit

Thermal resistance junction-to-ambient θJA 43.1 °C/W

(estimated)

I/O pin power dissipation PI/O User Determined W

Power dissipation PD PD = (IDD × VDD) + PI/O W

Maximum allowed PD PDMAX (TJ – TA) / RθJA 2 W

1. See Section 6.1 for more detail.

2. TJ = Junction Temperature
TA = Ambient Temperature

4.2 DC Electrical Characteristics

Table 4-4 DC Electrical Characteristics

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic Symbol Min Typ Max Unit

Input high voltage (XTAL/EXTAL) VIHC VDDA – 0.8 VDDA VDDA + 0.3 V
Input low voltage (XTAL/EXTAL) VILC -0.3 — 0.5 V
Input high voltage VIH 2.0 — 5.5 V
Input low voltage VIL -0.3 — 0.8 V
Input current low (pullups disabled) IIL -1 — 1 μA
Input current high (pullups disabled) IIH -1 — 1 μA
Output tri-state current low IOZL -10 — 10 μA
Output tri-state current high IOZH -10 — 10 μA
Output High Voltage VOH VDDIO – 0.7 — — V
Output Low Voltage VOL — — 0.4 V
Output High Current IOH 8 — 16 mA
Output Low Current IOL 8 — 16 mA
Input capacitance CIN — 8 — pF
Output capacitance COUT — 12 — pF

56854 Technical Data, Rev. 6

Freescale Semiconductor 25
 Table 4-4 DC Electrical Characteristics (Continued)
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic Symbol Min Typ Max Unit

VDD supply current (Core logic, memories, peripherals) IDD4
1 — 70 110 mA
Run
Deep Stop2 — 0.05 10 mA
— 5 14 mA
Light Stop3
VDDIO supply current (I/O circuity) IDDIO
5 — 40 50 mA
Run
Deep Stop2 0 1.5 mA

VDDA supply current (analog circuity) IDDA

2 — 60 120 μA
Deep Stop
Low Voltage Interrupt6 VEI — 2.5 2.85 V
Low Voltage Interrupt Recovery Hysteresis VEIH — 50 — mV

Power on Reset7 POR — 1.5 2.0 V

Note: Run (operating) IDD measured using external square wave clock source (fosc = 4MHz) into XTAL. All inputs 0.2V from rail;
no DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz out.
1. Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz.
2. Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator and time of day module operating.
3. Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator and time of day module operating.
4. IDD includes current for core logic, internal memories, and all internal peripheral logic circuitry.
5. Running core and performing external memory access. Clock at 120 MHz.
6. When VDD drops below VEI max value, an interrupt is generated.
7. Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains active
for as long as the internal 2.5V is below 1.8V no matter how long the ramp up rate is. The internally regulated voltage is typically
100 mV less than VDD during ramp up until 2.5V is reached, at which time it self-regulates.

56854 Technical Data, Rev. 6

26 Freescale Semiconductor
 DC Electrical Characteristics

150

EMI Mode5 MAC Mode1

120

90
IDD (mA)

60

30

0 20 40 60 80 100 120

Figure 4-1 Maximum Run IDDTOTAL vs. Frequency (see Notes 1. and 5. in Table 4-4)

56854 Technical Data, Rev. 6

Freescale Semiconductor 27
4.3 Supply Voltage Sequencing and Separation Cautions
Figure 4-2 shows two situations to avoid in sequencing the VDD and VDDIO, VDDA supplies.

3.3V VDDIO, VDDA

DC Power Supply Voltage

2 Supplies Stable

1.8V VDD
1

0 Time
Notes: 1. VDD rising before VDDIO, VDDA
2. VDDIO, VDDA rising much faster than VDD

Figure 4-2 Supply Voltage Sequencing and Separation Cautions

VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDD
supply (1.8V) from the voltage generated by the 3.3V VDDIO supply, see Figure 4-3. This keeps VDD from
rising faster than VDDIO.
VDD should not rise so late that a large voltage difference is allowed between the two supplies (2).
Typically this situation is avoided by using external discrete diodes in series between supplies, as shown
in Figure 4-3. The series diodes forward bias when the difference between VDDIO and VDD reaches
approximately 2.1, causing VDD to rise as VDDIO ramps up. When the VDD regulator begins proper
operation, the difference between supplies will typically be 0.8V and conduction through the diode chain
reduces to essentially leakage current. During supply sequencing, the following general relationship
should be adhered to:
VDDIO > VDD > (VDDIO - 2.1V)
In practice, VDDA is typically connected directly to VDDIO with some filtering.

56854 Technical Data, Rev. 6

28 Freescale Semiconductor
 AC Electrical Characteristics

3.3V VDDIO, VDDA

Supply Regulator

VDD
1.8V
Regulator

Figure 4-3 Example Circuit to Control Supply Sequencing

4.4 AC Electrical Characteristics

Timing waveforms in Section 4.2 are tested with a VIL maximum of 0.8 V and a VIH minimum of 2.0 V
for all pins except XTAL, which is tested using the input levels in Section 4.2. In Figure 4-4 the levels of
VIH and VIL for an input signal are shown.

VIH Low High

90%
Input Signal Midpoint1 50%
10%
Fall Time VIL Rise Time

Note: The midpoint is VIL + (VIH – VIL)/2.

Figure 4-4 Input Signal Measurement References

Figure 4-5 shows the definitions of the following signal states:

• Active state, when a bus or signal is driven, and enters a low impedance state.
• Tri-stated, when a bus or signal is placed in a high impedance state.
• Data Valid state, when a signal level has reached VOL or VOH.
• Data Invalid state, when a signal level is in transition between VOL and VOH.

Data1 Valid Data2 Valid Data3 Valid

Data1 Data2 Data3

Data
Data Invalid State
Tri-stated
Data Active Data Active

Figure 4-5 Signal States

56854 Technical Data, Rev. 6

Freescale Semiconductor 29
4.5 External Clock Operation
The 56854 system clock can be derived from a crystal or an external system clock signal. To generate a
reference frequency using the internal oscillator, a reference crystal must be connected between the
EXTAL and XTAL pins.

4.5.1 Crystal Oscillator

The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency
range specified for the external crystal in Table 4-6. In Figure 4-6 a typical crystal oscillator circuit is
shown. Follow the crystal supplier’s recommendations when selecting a crystal, because crystal
parameters determine the component values required to provide maximum stability and reliable start-up.
The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL
pins to minimize output distortion and start-up stabilization time.

Crystal Frequency = 2–4 MHz (optimized for 4MHz)

EXTAL XTAL Sample External Crystal Parameters:

Rz Rz = 10MΩ
TOD_SEL bit in CGM must be set to 0

Figure 4-6 Crystal Oscillator

4.5.2 High Speed External Clock Source (> 4MHz)

The recommended method of connecting an external clock is given in Figure 4-7. The external clock
source is connected to XTAL and the EXTAL pin is held at ground, VDDA, or VDDA/2. The TOD_SEL
bit in CGM must be set to 0.

56854
XTAL EXTAL

External GND,VDDA,
Clock or VDDA/2
(up to 240MHz)

Figure 4-7 Connecting a High Speed External Clock Signal using XTAL

56854 Technical Data, Rev. 6

30 Freescale Semiconductor
 External Clock Operation

4.5.3 Low Speed External Clock Source (2-4MHz)

The recommended method of connecting an external clock is given in Figure 4-8. The external clock
source is connected to XTAL and the EXTAL pin is held at VDDA/2. The TOD_SEL bit in CGM must be
set to 0.

56854
XTAL EXTAL

External VDDA/2
Clock
(2-4MHz)

Figure 4-8 Connecting a Low Speed External Clock Signal using XTAL

Table 4-5 External Clock Operation Timing Requirements4

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic Symbol Min Typ Max Unit

Frequency of operation (external clock driver)1 fosc 0 — 240 MHz

Clock Pulse Width4 tPW 6.25 — — ns

External clock input rise time2, 4 trise — — TBD ns

External clock input fall time3, 4 tfall — — TBD ns

1. See Figure 4-7 for details on using the recommended connection of an external clock driver.
2. External clock input rise time is measured from 10% to 90%.
3. External clock input fall time is measured from 90% to 10%.
4. Parameters listed are guaranteed by design.

VIH
External 90% 90%
50% 50%
Clock 10% 10%
tPW tPW
VIL
tfall trise

Note: The midpoint is VIL + (VIH – VIL)/2.

Figure 4-9 External Clock Timing

56854 Technical Data, Rev. 6

Freescale Semiconductor 31
 Table 4-6 PLL Timing
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic Symbol Min Typ Max Unit

External reference crystal frequency for the PLL1 fosc 2 4 4 MHz

PLL output frequency fclk 40 — 240 MHz

PLL stabilization time 2 tplls — 1 10 ms

1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is optimized for 4MHz input crystal.
2. This is the minimum time required after the PLL setup is changed to ensure reliable operation.

4.6 External Memory Interface Timing

The External Memory Interface is designed to access static memory and peripheral devices. Figure 4-10 shows
sample timing and parameters that are detailed in Table 4-11.

The timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as user
controlled wait states. The equation:

t = D + P * (M + W)
should be used to determine the actual time of each parameter. The terms in the above equation are defined as:
t parameter delay time
D fixed portion of the delay, due to on-chip path delays.
P the period of the system clock, which determines the execution rate of the part (i.e. when the device is
operating at 120 MHz, P = 8.33 ns).
M Fixed portion of a clock period inherent in the design. This number is adjusted to account for possible
clock duty cycle derating.
W the sum of the applicable wait state controls. See the “Wait State Controls” column of Table 4-11 for
the applicable controls for each parameter. See the EMI chapter of the 83x Peripheral Manual for
details of what each wait state field controls.
Some of the parameters contain two sets of numbers. These parameters have two different paths and clock edges
that must be considered. Check both sets of numbers and use the smaller result. The appropriate entry may change
if the operating frequency of the part changes.

The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters contain
two sets of numbers to account for this difference. The “Wait States Configuration” column of Table 4-11 should
be used to make the appropriate selection.

56854 Technical Data, Rev. 6

32 Freescale Semiconductor
 External Memory Interface Timing

A0-Axx,CS

tRD tRDA
tARDD
tARDA tRDRD

RD
tAWR tWAC
tWRWR tWR tWRRD tRDWR

WR

tDWR tDOH tRDD

tDOS tAD tDRD

D0-D15 Data Out Data In

Note: During read-modify-write instructions and internal instructions, the address lines do not change state.

Figure 4-10 External Memory Interface Timing

Figure 4-11 External Memory Interface Timing

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98 V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL < 50pF, P = 8.333ns

Wait States Wait States

Characteristic Symbol D M Unit
Configuration Controls

Address Valid to WR Asserted WWS=0 -0.79 0.50

tAWR WWSS ns
WWS>0 -1.98 0.69

WR Width Asserted to WR WWS=0 -0.86 0.19

tWR WWS ns
Deasserted WWS>0 -0.01 0.00

Data Out Valid to WR Asserted WWS=0 -1.52 0.00

WWS=0 - 5.69 0.25
tDWR WWSS ns
WWS>0 -2.10 0.19
WWS>0 -4.66 0.50

Valid Data Out Hold Time after WR tDOH -1.47 0.25 WWSH ns
Deasserted

Valid Data Out Set Up Time to WR -2.36 0.19 ns

tDOS WWS,WWSS
Deasserted -4.67 0.50

Valid Address after WR tWAC

-1.60 0.25 WWSH
Deasserted

56854 Technical Data, Rev. 6

Freescale Semiconductor 33
 Figure 4-11 External Memory Interface Timing (Continued)
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98 V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL < 50pF, P = 8.333ns

Wait States Wait States

Characteristic Symbol D M Unit
Configuration Controls

RD Deasserted to Address Invalid tRDA - 0.44 0.00 RWSH ns

Address Valid to RD Deasserted tARDD -2.07 1.00 RWSS,RWS ns

Valid Input Data Hold after RD tDRD 0.00 N/A1 — ns

Deasserted

RD Assertion Width tRD -1.34 1.00 RWS ns

Address Valid to Input Data Valid -10.27 1.00

tAD RWSS,RWS ns
-13.5 1.19

Address Valid to RD Asserted tARDA - 0.94 0.00 RWSS ns

RD Asserted to Input Data Valid -9.53 1.00

tRDD RWSS,RWS ns
-12.64 1.19

WR Deasserted to RD Asserted tWRRD -0.75 0.25 WWSH,RWSS ns

RD Deasserted to RD Asserted tRDRD -0.162 0.00 RWSS,RWSH ns

WR Deasserted to WR Asserted WWS=0 -0.44 0.75

tWRWR WWSS, WWSH ns
WWS>0 -0.11 1.00

RD Deasserted to WR Asserted 0.14 0.50 MDAR, BMDAR,

tRDWR ns
-0.57 0.69 RWSH, WWSS
1. N/A since device captures data before it deasserts RD
2. If RWSS = RWSH = 0, RD does not deassert during back-to-back reads and D=0.00 should be used.

4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 4-7 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic Symbol Min Max Unit See Figure

RESET Assertion to Address, Data and Control

tRAZ — 11 ns 4-12
Signals High Impedance

Minimum RESET Assertion Duration3 tRA 30 — ns 4-12

RESET Deassertion to First External Address Output tRDA — 120T ns 4-12

Edge-sensitive Interrupt Request Width tIRW 1T + 3 — ns 4-13

56854 Technical Data, Rev. 6

34 Freescale Semiconductor
 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 4-7 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic Symbol Min Max Unit See Figure

IRQA, IRQB Assertion to External Data Memory tIDM 18T — ns 4-14

Access Out Valid, caused by first instruction execution
in the interrupt service routine tIDM -FAST 14T —

IRQA, IRQB Assertion to General Purpose Output tIG 18T — ns 4-14

Valid, caused by first instruction execution in the
interrupt service routine tIG -FAST 14T —

IRQA Low to First Valid Interrupt Vector Address Out tIRI 22T — ns 4-15
recovery from Wait State4
tIRI -FAST 18T —

Delay from IRQA Assertion (exiting Stop) to External tIW 4-16

1.5T — ns
Data Memory5

Delay from IRQA Assertion (exiting Wait) to External tIF 4-16

Data Memory
Fast6 18T ns
—
22ET ns
Normal7 —

RSTO pulse width8 tRSTO 4-17

normal operation 128ET — —
internal reset mode 8ET — —
1. In the formulas, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.
2. Parameters listed are guaranteed by design.
3. At reset, the PLL is disabled and bypassed. The part is then put into Run mode and tclk assumes the period of the source
clock, txtal, textal or tosc.
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
not the minimum required so that the IRQA interrupt is accepted.
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
6. Fast stop mode:
Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is
requested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes
one less cycle and tclk will continue same value it had before stop mode was entered.
7. Normal stop mode:
As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master
clock, recovery will take an extra cycle (to restart the clock), and tclk will resume at the input clock source rate.
8. ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns.

56854 Technical Data, Rev. 6

Freescale Semiconductor 35
 RESET
tRA
tRAZ tRDA

A0–A20, First Fetch

D0–D15

CS, First Fetch

RD, WR

Figure 4-12 Asynchronous Reset Timing

IRQA
IRQB t
IRW

Figure 4-13 External Interrupt Timing (Negative-Edge-Sensitive)

56854 Technical Data, Rev. 6

36 Freescale Semiconductor
 Reset, Stop, Wait, Mode Select, and Interrupt Timing

A0–A20,
CS, First Interrupt Instruction Execution
RD, WR
tIDM

IRQA,
IRQB

a) First Interrupt Instruction Execution

General
Purpose
I/O Pin
tIG

IRQA,
IRQB

b) General Purpose I/O

Figure 4-14 External Level-Sensitive Interrupt Timing

IRQA,
IRQB
tIRI

A0–A20, First Interrupt Vector

CS, Instruction Fetch
RD, WR

Figure 4-15 Interrupt from Wait State Timing

tIW

IRQA

tIF

A0–A20,
CS, First Instruction Fetch
Not IRQA Interrupt Vector
RD, WR

Figure 4-16 Recovery from Stop State Using Asynchronous Interrupt Timing

56854 Technical Data, Rev. 6

Freescale Semiconductor 37
 RESET
tRSTO

Figure 4-17 Reset Output Timing

4.8 Host Interface Port

Table 4-8 Host Interface Port Timing1

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic Symbol Min Max Unit See Figure

Access time TACKDV — 13 ns 4-18

Disable time TACKDZ 3 — ns 4-18

4-18
Time to disassert TACKREQH 3.5 9 ns
4-21

4-18
Lead time TREQACKL 0 — ns
4-21

ns 4-19
Access time TRADV — 13
4-20

ns 4-19
Disable time TRADX 5 —
4-20

ns 4-19
Disable time TRADZ 3 —
4-20

Setup time TDACKS 3 — ns 4-21

Hold time TACKDH 1 — ns 4-21

4-22
Setup time TADSS 3 — ns
4-23

4-22
Hold time TDSAH 1 — ns
4-23

4-22
Pulse width TWDS 5 — ns
4-23

Time to re-assert
1. After second write in 16-bit mode TACKREQL 4T + 5 ns 4-18
5T + 9
2. After first write in 16-bit mode 5 13 ns 4-21
or after write in 8-bit mode
1. The formulas: T = clock cycle. f ipb = 60MHz, T = 16.7ns.

56854 Technical Data, Rev. 6

38 Freescale Semiconductor
 Host Interface Port

HACK
TACKDZ
TACKDV

HD

TREQACKL TACKREQH TACKREQL

HREQ

Figure 4-18 Controller-to-Host DMA Read Mode

HA

TRADX

HCS

HDS

HRW
TRADV
TRADZ

HD

Figure 4-19 Single Strobe Read Mode

HA

TRADX

HCS

HWR

HRD
TRADZ
TRADV
HD

Figure 4-20 Dual Strobe Read Mode

56854 Technical Data, Rev. 6

Freescale Semiconductor 39
 HACK

TDACKS TACKDH

HD

TREQACKL TACKREQL
TACKREQH

HREQ

Figure 4-21 Host-to-Controller DMA Write Mode

HA
TDSAH

HCS
TWDS

HDS
TDSAH

HRW
TADSS
TADSS TDSAH

HD

Figure 4-22 Single Strobe Write Mode

HA

HCS
TWDS

HWR

TDSAH
TADSS
HRD

TADSS

HD

Figure 4-23 Dual Strobe Write Mode

56854 Technical Data, Rev. 6

40 Freescale Semiconductor
 Serial Peripheral Interface (SPI) Timing

4.9 Serial Peripheral Interface (SPI) Timing

Table 4-9 SPI Timing 1
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic Symbol Min Max Unit See Figure

Cycle time tC 4-24, 4-25, 4-26,

Master 25 — ns 4-27
Slave 25 — ns

Enable lead time tELD 4-27

Master — — ns
Slave 12.5 — ns

Enable lag time tELG 4-27

Master — — ns
Slave 12.5 — ns

Clock (SCLK) high time tCH ns 4-24, 4-25, 4-26,

Master 9 — ns 4-27
Slave 12.5 —

Clock (SCLK) low time tCL 4-27

Master 12 — ns
Slave 12.5 — ns

Data set-up time required for inputs tDS 4-24, 4-25, 4-26,
Master 10 — ns 4-27
Slave 2 — ns

Data hold time required for inputs tDH 4-24, 4-25, 4-26,
Master 0 — ns 4-27
Slave 2 — ns

Access time (time to data active from high-impedance state) tA ns 4-27

Slave 5 15 ns

Disable time (hold time to high-impedance state) tD ns 4-27

Slave 2 9 ns

Data valid for outputs tDV 4-24, 4-25, 4-26,

Master — 2 ns 4-27
Slave (after enable edge) — 14 ns

Data invalid tDI 4-24, 4-25, 4-26,

Master 0 — ns 4-27
Slave 0 — ns

Rise time tR 4-24, 4-25, 4-26,

Master — 11.5 ns 4-27
Slave — 10.0 ns

Fall time tF 4-24, 4-25, 4-26,

Master — 9.7 ns 4-27
Slave — 9.0 ns
1. Parameters listed are guaranteed by design.

56854 Technical Data, Rev. 6

Freescale Semiconductor 41
 SS SS is held High on master
(Input)
tC
tR
tF
SCLK (CPOL = 0) tCL
(Output) tCH
tF
tR
tCL
SCLK (CPOL = 1)
(Output)
tDH
tCH
tDS tCH

MISO
(Input) MSB in Bits 14–1 LSB in

tDI tDV tDI(ref)

MOSI Master MSB out Bits 14–1 Master LSB out

(Output)
tF tR

Figure 4-24 SPI Master Timing (CPHA = 0)

SS SS is held High on master

(Input) tC
tF
tR
tCL
SCLK (CPOL = 0)
(Output) tCH
tF

tCL
SCLK (CPOL = 1)
(Output)
tDS
tCH
tR tDH

MISO
(Input) MSB in Bits 14–1 LSB in

tDV(ref) tDI tDV

MOSI Master MSB out Bits 14– 1 Master LSB out

(Output)
tF tR

Figure 4-25 SPI Master Timing (CPHA = 1)

56854 Technical Data, Rev. 6

42 Freescale Semiconductor
 Serial Peripheral Interface (SPI) Timing

SS
(Input)
tC tF tELG

tR
tCL
SCLK (CPOL = 0)
(Input)
tCH
tELD

tCL
SCLK (CPOL = 1)
(Input)
tA tF
tR tD
tCH
MISO
(Output) Slave MSB out Bits 14–1 Slave LSB out
tDS tDV tDI
tDI
tDH

MOSI MSB in Bits 14–1 LSB in

(Input)

Figure 4-26 SPI Slave Timing (CPHA = 0)

SS
(Input)
tF
tC
tR
SCLK (CPOL = 0) tCL
(Input) tCH
tELG
tELD

tCL
SCLK (CPOL = 1)
(Input) tDV
tR
tF
tA tCH tD

MISO
(Output) Slave MSB out Bits 14–1 Slave LSB out

tDS tDV
tDI
tDH
MOSI MSB in Bits 14–1 LSB in
(Input)

Figure 4-27 SPI Slave Timing (CPHA = 1)

56854 Technical Data, Rev. 6

Freescale Semiconductor 43
4.10 Quad Timer Timing

Table 4-10 Quad Timer Timing1, 2

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic Symbol Min Max Unit

Timer input period PIN 2T + 3 — ns

Timer input high/low period PINHL 1T + 3 — ns

Timer output period POUT 2T - 3 — ns

Timer output high/low period POUTHL 1T - 3 — ns

1. In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.
2. Parameters listed are guaranteed by design.

Timer Inputs
PIN PINHL PINHL

Timer Outputs
POUT POUTHL POUTHL

Figure 4-28 Timer Timing

4.11 Enhanced Synchronous Serial Interface (ESSI) Timing

Table 4-11 ESSI Master Mode1 Switching Characteristics

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Parameter Symbol Min Typ Max Units

SCK frequency fs — — 152 MHz

SCK period3 tSCKW 66.7 — — ns

SCK high time tSCKH 33.44 — — ns

SCK low time tSCKL 33.44 — — ns

Output clock rise/fall time — — 4 — ns

Delay from SCK high to SC2 (bl) high - Master5 tTFSBHM -1.0 — 1.0 ns

56854 Technical Data, Rev. 6

44 Freescale Semiconductor
 Enhanced Synchronous Serial Interface (ESSI) Timing

Table 4-11 ESSI Master Mode1 Switching Characteristics (Continued)

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Parameter Symbol Min Typ Max Units

Delay from SCK high to SC2 (wl) high - Master5 tTFSWHM -1.0 — 1.0 ns

Delay from SC0 high to SC1 (bl) high - Master5 tRFSBHM -1.0 — 1.0 ns

Delay from SC0 high to SC1 (wl) high - Master5 tRFSWHM -1.0 — 1.0 ns

Delay from SCK high to SC2 (bl) low - Master5 tTFSBLM -1.0 — 1.0 ns

Delay from SCK high to SC2 (wl) low - Master5 tTFSWLM -1.0 — 1.0 ns

Delay from SC0 high to SC1 (bl) low - Master5 tRFSBLM -1.0 — 1.0 ns

Delay from SC0 high to SC1 (wl) low - Master5 tRFSWLM -1.0 — 1.0 ns

SCK high to STD enable from high impedance - Master tTXEM -0.1 — 2 ns

SCK high to STD valid - Master tTXVM -0.1 — 2 ns

SCK high to STD not valid - Master tTXNVM -0.1 — — ns

SCK high to STD high impedance - Master tTXHIM -4 — 0 ns

SRD Setup time before SC0 low - Master tSM 4 — — ns

SRD Hold time after SC0 low - Master tHM 4 — — ns

Synchronous Operation (in addition to standard internal clock parameters)

SRD Setup time before SCK low - Master tTSM 4 — — ns

SRD Hold time after SCK low - Master tTHM 4 — — ns

1. Master mode is internally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for an 120MHz part.
3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync
have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in
the tables and in the figures.
4. 50 percent duty cycle
5. bl = bit length; wl = word length

56854 Technical Data, Rev. 6

Freescale Semiconductor 45
 tSCKW
tSCKH
tSCKL
SCK output

tTFSBHM tTFSBLM
SC2 (bl) output

tTFSWHM tTFSWLM
SC2 (wl) output

tTXVM
tTXEM tTXNVM tTXHIM
STD First Bit Last Bit

SC0 output

tRFSBHM tRFBLM
SC1 (bl) output

tRFSWHM tRFSWLM
SC1 (wl) output

tTSM
tSM tHM tTHM
SRD

Figure 4-29 Master Mode Timing Diagram

Table 4-12 ESSI Slave Mode1 Switching Characteristics

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Parameter Symbol Min Typ Max Units

SCK frequency fs — — 152 MHz

SCK period3 tSCKW 66.7 — — ns

SCK high time tSCKH 33.44 — — ns

SCK low time tSCKL 33.44 — — ns

Output clock rise/fall time — — 4 — ns

Delay from SCK high to SC2 (bl) high - Slave5 tTFSBHS -1 — 29 ns

56854 Technical Data, Rev. 6

46 Freescale Semiconductor
 Enhanced Synchronous Serial Interface (ESSI) Timing

Table 4-12 ESSI Slave Mode1 Switching Characteristics (Continued)

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Parameter Symbol Min Typ Max Units

Delay from SCK high to SC2 (wl) high - Slave5 tTFSWHS -1 — 29 ns

Delay from SC0 high to SC1 (bl) high - Slave5 tRFSBHS -1 — 29 ns

Delay from SC0 high to SC1 (wl) high - Slave5 tRFSWHS -1 — 29 ns

Delay from SCK high to SC2 (bl) low - Slave5 tTFSBLS -29 — 29 ns

Delay from SCK high to SC2 (wl) low - Slave5 tTFSWLS -29 — 29 ns

Delay from SC0 high to SC1 (bl) low - Slave5 tRFSBLS -29 — 29 ns

Delay from SC0 high to SC1 (wl) low - Slave5 tRFSWLS -29 — 29 ns

SCK high to STD enable from high impedance - Slave tTXES — — 15 ns

SCK high to STD valid - Slave tTXVS 4 — 15 ns

SC2 high to STD enable from high impedance (first bit) - Slave tFTXES 4 — 15 ns

SC2 high to STD valid (first bit) - Slave tFTXVS 4 — 15 ns

SCK high to STD not valid - Slave tTXNVS 4 — 15 ns

SCK high to STD high impedance - Slave tTXHIS 4 — 15 ns

SRD Setup time before SC0 low - Slave tSS 4 — — ns

SRD Hold time after SC0 low - Slave tHS 4 — — ns

Synchronous Operation (in addition to standard external clock parameters)

SRD Setup time before SCK low - Slave tTSS 4 — — ns

SRD Hold time after SCK low - Slave tTHS 4 — — ns

1. Slave mode is externally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part.
3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync
have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in
the tables and in the figures.
4. 50 percent duty cycle
5. bl = bit length; wl = word length

56854 Technical Data, Rev. 6

Freescale Semiconductor 47
 tSCKW

tSCKH tSCKL
SCK input
tTFSBLS
tTFSBHS
SC2 (bl) input

tTFSWHS tTFSWLS
SC2 (wl) input

tFTXVS
tFTXES
tTXVS tTXNVS
tTXES tTXHIS
STD First Bit Last Bit

SC0 input
tRFSBHS tRFBLS

SC1 (bl) input

tRFSWHS
tRFSWLS
SC1 (wl) input

tTSS
tSS tHS tTHS
SRD

Figure 4-30 Slave Mode Clock Timing

4.12 Serial Communication Interface (SCI) Timing

Table 4-13 SCI Timing4

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic Symbol Min Max Unit

Baud Rate1 BR — (fMAX)/(32) Mbps

RXD2 Pulse Width RXDPW 0.965/BR 1.04/BR ns

TXD3 Pulse Width TXDPW 0.965/BR 1.04/BR ns

1. fMAX is the frequency of operation of the system clock in MHz.

2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4. Parameters listed are guaranteed by design.

56854 Technical Data, Rev. 6

48 Freescale Semiconductor
 JTAG Timing

RXD
SCI receive
data pin
(Input) RXDPW

Figure 4-31 RXD Pulse Width

TXD
SCI receive
data pin
(Input) TXDPW

Figure 4-32 TXD Pulse Width

4.13 JTAG Timing

Table 4-14 JTAG Timing1, 3

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic Symbol Min Max Unit

TCK frequency of operation2 fOP DC 30 MHz

TCK cycle time tCY 33.3 — ns

TCK clock pulse width tPW 16.6 — ns

TMS, TDI data setup time tDS 3 — ns

TMS, TDI data hold time tDH 3 — ns

TCK low to TDO data valid tDV — 12 ns

TCK low to TDO tri-state tTS — 10 ns

TRST assertion time tTRST 35 — ns

DE assertion time tDE 4T — ns

1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 120MHz
operation, T = 8.33ns.
2. TCK frequency of operation must be less than 1/4 the processor rate.
3. Parameters listed are guaranteed by design.

56854 Technical Data, Rev. 6

Freescale Semiconductor 49
 tCY

tPW tPW
VIH
VM VM
TCK
(Input)
VIL
VM = VIL + (VIH – VIL)/2

Figure 4-33 Test Clock Input Timing Diagram

TCK
(Input)
tDS tDH

TDI
TMS Input Data Valid
(Input) tDV

TDO
(Output) Output Data Valid
tTS

TDO
(Output)

Figure 4-34 Test Access Port Timing Diagram

TRST
(Input)
tTRST

Figure 4-35 TRST Timing Diagram

DE
tDE

Figure 4-36 Enhanced OnCE—Debug Event

56854 Technical Data, Rev. 6

50 Freescale Semiconductor
 GPIO Timing

4.14 GPIO Timing

Table 4-15 GPIO Timing1, 2

Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz

Characteristic Symbol Min Max Unit

GPIO input period PIN 2T + 3 — ns

GPIO input high/low period PINHL 1T + 3 — ns

GPIO output period POUT 2T - 3 — ns

GPIO output high/low period POUTHL 1T - 3 — ns

1. In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns
2. Parameters listed are guaranteed by design.

GPIO Inputs
PIN PINHL PINHL

GPIO Outputs
POUT POUTHL POUTHL

Figure 4-37 GPIO Timing

56854 Technical Data, Rev. 6

Freescale Semiconductor 51
Part 5 Packaging
5.1 Package and Pin-Out Information 56854
This section contains package and pin-out information for the 128-pin LQFP configuration of the 56854.

HRWB
RXD1

RXD0
VDDIO

VDDIO
VDDIO

VDDIO
VSSIO

VSSIO

VSSIO
TXD1

TXD0
TIO0

TIO1
TIO2
TIO3

HA2
HA1
HA0

CS3
CS2
CS1
CS0
VDD
VDD

A20
A19
A18
A17
A16
VSS

VSS
D5
D4
D3
D2
D1

D0
HDS
PIN 65 VDD
HCS PIN 103 VSS
HREQ VSSIO
HACK VDDIO
D6 A15
D7 A14
D8 A13
D9 A12
D10 VSSIO
VDD VDDIO
VSS TCK
VDDIO TMS
VSSIO TDI
STD0 TDO
SRD0 TRST
SCK0 DE
SC00 VSS
SC01 VDD
SC02 A11
D11 A10
D12 A9
VDDIO A8
VSSIO VSSIO
ORIENTATION VDDIO
D13
D14 MARK HD7
PIN 39 HD6
D15 PIN 1
MISO

CLKO
RSTO
RD
WR
MOSI

XTAL
EXTAL

RESET
A0
A1
A2
A3

MODC
SCK
SS

IRQA
IRQB

A4
A5
A6
A7
HD0
HD1
HD2

HD3
HD4
HD5
VDDIO
VSSIO

VDD
VSS
MODA
MODB

VDDA
VSSA
VDDIO
VSSIO

Figure 5-1 Top View, 56854 128-pin LQFP Package

56854 Technical Data, Rev. 6

52 Freescale Semiconductor
 Package and Pin-Out Information 56854

Table 5-1 56854 Pin Identification by Pin Number

Pin Pin Pin Pin
Signal Name Signal Name Signal Name Signal Name
No. No. No. No.

1 MISO 33 CLKO 65 RXD0 97 TIO3

2 MOSI 34 RSTO 66 TXDO 98 TIO2

3 SCK 35 RESET 67 A16 99 TIO1

4 SS 36 HD3 68 A17 100 VDDIO

5 VDDIO 37 HD4 69 A18 101 TIO0

6 VSSIO 38 HD5 70 A19 102 VSSIO

7 RD 39 HD6 71 A20 103 HDS

8 WR 40 HD7 72 VDDIO 104 HCS

9 A0 41 VDDIO 73 D0 105 HREQ

10 A1 42 VSSIO 74 VSSIO 106 HACK

11 A2 43 A8 75 CS0 107 D6

12 A3 44 A9 76 CS1 108 D7

13 VDD 45 A10 77 CS2 109 D8

14 VSS 46 A11 78 CS3 110 D9

15 MODA 47 VDD 79 VDD 111 D10

16 MODB 48 VSS 80 VDD 112 VDD

17 MODC 49 DE 81 VSS 113 VSS

18 VDDIO 50 TRST 82 HA0 114 VDDIO

19 VSSIO 51 TDO 83 HA1 115 VSSIO

20 IRQA 52 TDI 84 HA2 116 STD0

21 IRQB 53 TMS 85 HRWB 117 SRD0

22 VDDA 54 TCK 86 D1 118 SCK0

23 VSSA 55 VDDIO 87 D2 119 SC00

24 XTAL 56 VSSIO 88 D3 120 SC01

25 EXTAL 57 A12 89 D4 121 SC02

26 A4 58 A13 90 D5 122 D11

56854 Technical Data, Rev. 6

Freescale Semiconductor 53
 Table 5-1 56854 Pin Identification by Pin Number (Continued)
Pin Pin Pin Pin
Signal Name Signal Name Signal Name Signal Name
No. No. No. No.

27 A5 59 A14 91 VDDIO 123 D12

28 A6 60 A15 92 VDDIO 124 VDDIO

29 A7 61 VDDIO 93 VSSIO 125 VSSIO

30 HD0 62 VSSIO 94 RXD1 126 D13

31 HD1 63 VSS 95 TXD1 127 D14

32 HD2 64 VDD 96 VSS 128 D15

56854 Technical Data, Rev. 6

54 Freescale Semiconductor
 Package and Pin-Out Information 56854

102 65

103 64

128 39

38

MILLIMETERS
DIM
MIN MAX
A --- 1.60
A1 0.05 0.15
A2 1.35 1.45
NOTES:
b 0.17 0.27
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994. b1 0.17 0.23
2. CONTROLLING DIMENSION: MILLIMETER. c 0.09 0.20
3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD c1 0.09 0.16
AND IS COINCIDENT WITH THE LEAD WHERE THE D 22.00 BSC
LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF D1 20.00BSC
THE PARTING LINE. e 0.50 BSC
4. DATUMS A, B, AND D TO BE DETERMINED AT DATUM E 16.00 BSC
PLANE H. E1 14.00 BSC
5. DIMENSIONS D AND E TO BE DETERMINED AT
L 0.45 0.75
SEATING PLANE C.
L1 1.00 REF
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER L2 0.50 REF
SIDE. DIMENSIONS D1 AND E1 DO INCLUDE MOLD S 0.20 ---
MISMATCH AND ARE DETERMINED AT DATUM R1 0.08 ---
PLANE H. R2 0.08 0.20
7. DIMENSION b DOES NOT INCLUDE DAMBAR 0 0o 7o
PROTRUSION. DAMBAR PROTRUSION SHALL NOT 01 0 o ---
CAUSE THE b DIMENSION TO EXCEED 0.35.
02 11o 13o
Case Outline - 1129-01
Figure 5-2 128-pin LQFP Mechanical Information
Please see www.freescale.com for the most current case outline.

56854 Technical Data, Rev. 6

Freescale Semiconductor 55
Part 6 Design Considerations
6.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
Equation 1: TJ = TA + (PD x RθJA)
Where:
TA = ambient temperature °C
RθJA = package junction-to-ambient thermal resistance °C/W
PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:
Equation 2: RθJA = RθJC + RθCA
Where:
RθJA = package junction-to-ambient thermal resistance °C/W
RθJC = package junction-to-case thermal resistance °C/W
RθCA = package case-to-ambient thermal resistance °C/W
RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where
the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the
device thermal performance may need the additional modeling capability of a system level thermal
simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether
the thermal performance is adequate, a system level model may be appropriate.
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
• Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the
chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation
across the surface.
• Measure the thermal resistance from the junction to where the leads are attached to the case. This definition
is approximately equal to a junction to board thermal resistance.
• Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case
determined by a thermocouple.

56854 Technical Data, Rev. 6

56 Freescale Semiconductor
 Electrical Design Considerations

As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the
first definition. From a practical standpoint, that value is also suitable for determining the junction
temperature from a case thermocouple reading in forced convection environments. In natural convection,
using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple
reading on the case of the package will estimate a junction temperature slightly hotter than actual. Hence,
the new thermal metric, Thermal Characterization Parameter, or ΨJT, has been defined to be (TJ – TT)/PD.
This value gives a better estimate of the junction temperature in natural convection when using the surface
temperature of the package. Remember that surface temperature readings of packages are subject to
significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat
loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the
top center of the package with thermally conductive epoxy.

6.2 Electrical Design Considerations

CAUTION

This device contains protective circuitry to guard against

damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.

Use the following list of considerations to assure correct operation:

• Provide a low-impedance path from the board power supply to each VDD pin on the controller, and from the
board ground to each VSS (GND) pin.
• The minimum bypass requirement is to place six 0.01–0.1 μF capacitors positioned as close as possible to
the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each
of the ten VDD/VSS pairs, including VDDA/VSSA.
• Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND)
pins are less than 0.5 inch per capacitor lead.
• Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and GND.
• Bypass the VDD and GND layers of the PCB with approximately 100 μF, preferably with a high-grade
capacitor such as a tantalum capacitor.
• Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal.

56854 Technical Data, Rev. 6

Freescale Semiconductor 57
 • Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and GND circuits.
• All inputs must be terminated (i.e., not allowed to float) using CMOS levels.
• Take special care to minimize noise levels on the VDDA and VSSA pins.
• When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device.
• Designs that utilize the TRST pin for JTAG port or Enhance OnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as
well as a means to assert TRST independently of RESET. Designs that do not require debugging
functionality, such as consumer products, should tie these pins together.
• The internal POR (Power on Reset) will reset the part at power on with reset asserted or pulled high but
requires that TRST be asserted at power on.

56854 Technical Data, Rev. 6

58 Freescale Semiconductor
 Electrical Design Considerations

Part 7 Ordering Information

Table 7-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor
sales office or authorized distributor to determine availability and to order parts.

Table 7-1 56854 Ordering Information

Supply Pin Frequency
Part Package Type Order Number
Voltage Count (MHz)

DSP56854 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) 128 120 DSP56854FG120

DSP56854 1.8V, 3.3V Low-Profile Quad Flat Pack (LQFP) 128 120 DSP56854FGE *

*This package is RoHS compliant.

56854 Technical Data, Rev. 6

Freescale Semiconductor 59
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This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2005. All rights reserved.

DSP56854
Rev. 6
01/2007