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LAB. 06 Alu Design 01: Circuit Diagram

This document describes the design of an ALU circuit using Verilog code. It defines modules for a half adder, full adder, 4-bit adder, 2-to-1 mux, and ALU. The ALU module instantiates 4 muxes, an adder, and combines inputs x and y based on selection lines s0, s1, s2. A test bench is provided to simulate the ALU with different input combinations over time.

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Babar Rasheed
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47 views3 pages

LAB. 06 Alu Design 01: Circuit Diagram

This document describes the design of an ALU circuit using Verilog code. It defines modules for a half adder, full adder, 4-bit adder, 2-to-1 mux, and ALU. The ALU module instantiates 4 muxes, an adder, and combines inputs x and y based on selection lines s0, s1, s2. A test bench is provided to simulate the ALU with different input combinations over time.

Uploaded by

Babar Rasheed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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LAB.

06
ALU DESIGN 01
// Muhammad Babar Rasheed
// 11-EE-185
//Section: B-2

CIRCUIT DIAGRAM:

CODE:
module ha(sum,carry,a,b);
output sum,carry;
input a,b;
xor g1(sum,a,b);

//halfadder module
//declaring outputs
//operation for sum

and g2(carry,a,b);
endmodule
module fa(sum,carry,a,b,c);
output sum,carry;
input a,b,c;
wire w1,w2,w3;

//it declares end of code


//fulladder module
// it declares wires

ha z1(w1,w2,a,b);
ha z2(sum,w3,w1,c);
or g3(carry,w2,w3);
endmodule

// calling half adder 2 times

module adder4bit(sum,carry,a,b,c);
//4 bit adder
output [3:0]sum;
// it declares 4-bit output
output carry;
input [3:0]a,b;
input c;
wire w1,w2,w3;
fa y1(sum[0],w1,a[0],b[0],c);
fa y2(sum[1],w2,a[1],b[1],w1);
fa y3(sum[2],w3,a[2],b[2],w2);
fa y4(sum[3],carry,a[3],b[3],w3);
endmodule
module mux(out,y,s1,s2);
input y,s1,s2;
output out;
not g1(w1,y);
and g2(w2,s1,y);
and g3(w3,s2,w1);
or g4(out,w2,w3);
endmodule
module ALU(G,cout,x,y,s0,s1,s2);
input [3:0]x,y;
input s0,s1,s2;
output [3:0]G;
output cout;
wire [3:0]w;
mux ins1(w[3],y[3],s1,s2);
mux ins2(w[2],y[2],s1,s2);
mux ins3(w[1],y[1],s1,s2);
mux ins4(w[0],y[0],s1,s2);
adder4bit ins5(G,cout,x,w,s0);
endmodule
module test06();
reg [3:0]x,y;
reg s0,s1,s2;

//calling full adder 4 times

//2*1 mux

//ALU module

//mux is called 4 times

//test bench module

wire [3:0]G;
wire cout;
ALU zz(G,cout,x,y,s0,s1,s2);
//instantiation of main module
initial
begin
s0=0;s1=0;s2=0;x=0011;y=1101;
#10 s0=0;s1=0;s2=1;x=0011;y=1101;
#10 s0=0;s1=1;s2=0;x=0011;y=1101;
#10 s0=0;s1=1;s2=1;x=0011;y=1101;
#10 s0=1;s1=0;s2=0;x=0011;y=1101;
#10 s0=1;s1=0;s2=1;x=0011;y=1101;
#10 s0=1;s1=1;s2=0;x=0011;y=1101;
#10 s0=1;s1=1;s2=1;x=0011;y=1101;
end
endmodule

WAVEFORM:

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