DLD LABORATORY (20A04303P) II B.

Tech(ECE/EEE)

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

II B.Tech. II-Sem (ECE)
(20A04303P) DIGITAL LOGIC DESIGN LABORATORY
COURSE OUTCOMES(COS)

CO1 Understand the pin configuration of various digital ICs used in the lab 01
CO2 Conduct the experiment and verify the properties of various logic circuits. 02
CO3 Analyze the sequential and combinational circuits. 04
CO4 Design of any sequential/combinational circuit using Hardware/ HDL. 03

PART A:
LIST OF EXPERIMENTS:
1. Verification of truth tables of the following Logic gates
Two input (i) OR (ii) AND (iii) NOR (iv) NAND (v) Exclusive-OR (vi) Exclusive-NOR
2. Design a simple combinational circuit with four variables and obtain minimal expression
and verify the truth table using Digital Trainer Kit.
3. Verification of functional table of 3 to 8-line Decoder /De-multiplexer.
4. 4variable logic function verification using 8 to1 multiplexer.
5. Design full adder circuit and verify its functional table.
6. Verification of functional tables of (i) JK Edge triggered Flip–Flop (ii) JK Master Slav
Flip–Flop (iii) D Flip-Flop
7. Design a four-bit ring counter using D Flip–Flops/JK Flip Flop and verify output
8. Design a four bit Johnson’s counter using D Flip-Flops/JK Flip Flops and verify output
9. Verify the operation of 4-bit Universal Shift Register for different Modes of operation.
10. Draw the circuit diagram of MOD-8 ripple counter and construct a circuit using T-Flip-
Flops and Test It with a low frequency clock and sketch the output waveforms.
11. Design MOD–8 synchronous counter using T Flip-Flop and verify the result and sketch
the output waveforms.
12. (a) Draw the circuit diagram of a single bit comparator and test the output
(b) Construct 7 Segment Display Circuit Using Decoder and7 Segment LED and test it.
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LOGIC DIAGRAMS:

NOT GATE

OR GATE

AND GATE

NAND GATE

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EXP.NO:01 DATE:

LOGIC GATES

AIM: Verification of Truth Table for AND, OR, NOT, NAND, NOR and EX-OR gates.

APPARATUS REQUIRED:

S.NO APPARATUS RANGE QUANTITY

74LS08,74LS32,74LS04, 1
1 IC
74LS00,74LS02,74LS86
1
2 Digital IC Trainer Kit
Required
3 Patch cards
1
4 Fixed Power Supply (0-5v)

THEORY:
The basic logic gates are the building blocks of more complex logic circuits. These
logic gates perform the basic Boolean functions, such as AND, OR, NAND, NOR,
Inversion, Exclusive-OR, Exclusive-NOR. Fig. below shows the circuit symbol, Boolean
function, and truth. It is seen from the Fig that each gate has one or two binary inputs, A
and B, and one binary output, C. The small circle on the output of the circuit symbols
designates the logic complement. The AND, OR, NAND, and NOR gates can be extended
to have more than two inputs. A gate can be extended to have multiple inputs if the binary
operation it represents is commutative and associative.
PROCEDURE:

1. Do the Connections as per symbol and indent marked on PCB.

2. Give the logic input to the gate under test as per symbol from INPUT
3. SWITCHES section.
4. Connect output of gate under test to any of the led from OUTPUT LED section
5. Observe the output on LEDS from OUTPUT SECTION and verify the truth table.

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NOR GATE

EX-OR GATE

EX-NOR GATE

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RESULT:

CONCLUSION:

VIVA QUESTIONS:

1. Why NAND & NOR gates are called universal gates?

2. Realize the EX – OR gates using minimum number of NAND gates?

3. Give the truth table for EX-NOR and realize using NAND gates?

4. What is the principle of logic gates?

5. Which is the most commonly used logic family?

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REALIZATION USING BASIC GATES:

REALIZATION USING NAND GATES:

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EXP NO: 02 DATE:

COMBINATIONAL CIRCUIT
AIM:-To implement and verification of four variables logic functional truth table using
basic gates and universal gates.
APPARATUS REQUIRED:

S.NO APPARATUS RANGE QUANTITY

IC 74LS08,74LS32,74LS04, 1
1
74LS00,74LS02
Digital IC Trainer Kit 1
2
REQUIRED
3 Patch cards
1
4 Fixed Power Supply (0-5v)

THEORY:
Canonical Forms (Normal Forms): Any Boolean function can be written in
Disjunctive normal form (sum of min-terms) or conjunctive normal form (product of maxterms).
A Boolean function can be represented by a Karnaugh map in which each cell corresponds
to a minterm. The cells are arranged in such a way that any two immediately adjacent cells
correspond to two minterms of distance 1. There is more than one way to construct a map
with this property.
PROCEDURE:

1. Do the connection as per block diagram shown below and switch ON the power supply
2. Provide the input data via the input switches and observe the output on output
LEDs Verify the Truth Table

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REALIZATION USING NOR GATES:

For the given Truth, Table,realize a logical circuit using basic gates and NAND gates

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RESULT:

CONCLUSION:

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VIVA QUESTIONS:

1. What are the different methods to obtain minimal expression?

2. What is a Min term and Max term?

3. State the difference between SOP and POS?

4. How do you realize a given function using multiplexer?

5. What is a multiplexer?

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BLOCK DIAGRAM:

TRUTH TABLE FOR DECODER:

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EXP. NO: 03 DATE:

3:8 DECODER /DE-MULTIPLEXER

AIM:-Verification of functional table of 3:8 Decoder /De-multiplexer.

APPARATUS REQUIRED:

S.NO APPARATUS RANGE QUANTITY

1
1 IC 74LS138
1
2 Digital IC Trainer Kit
Required
3 Patch cards
1
4 Fixed Power Supply (0-5v)

THEORY DECODER:

A decoder is a device which does the reverse operation of an encoder, undoing

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the encoding so that the original information can be retrieved. The same method used to
encode is usually just reversed in order to decode. It is a combinational circuit that
converts binary information from n input lines to a maximum of 2n unique output lines. In
digital electronics, a decoder can take the form of a multiple-input, multiple-output logic
circuit that converts coded inputs into coded outputs, where the input and output codes are
different. e.g. n-to-2n, binary-coded decimal decoders. Enable inputs must be on for the
decoder to function, otherwise its outputs assume a single "disabled" output code word. In
case of decoding all combinations of three bits eight (2 3=8) decoding gates are required.
This type of decoder is called 3-8 decoder because 3 inputs and 8 outputs. For any input
combination decoder outputs are 1.

Procedure:
1. The truth table and a design of 3:8 decoder are given.
2. Realize this circuit on your board by using logic circuit.
3. Connect threeinputs x,y,z to the switches & eight outputs vice-versa.
4. Connect the functions outputs to LEDs.
5. Verify input/output relation (Truth table) of this converter.

Pin Description IC74138 Circuit connection

BLOCK DIAGRAM 3:8 DEMUX:

Y0
A
Y1
B

C Y2
I/P
SWITCHES G2A
Y3
O/P

Y4 LEDS
G2B
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G1
Y6

Y7
74138
DLD LABORATORY (20A04303P) II B.Tech(ECE/EEE)

TRUTH TABLE FOR DEMUX:

NOTE1: G2=G2A and G2B

DEMULTIPLEXER:

The function of Demultiplexer is in contrast to multiplexer function. It takes information

from one line and distributes it to a given number of output lines. For this reason, the
demultiplexer is also known as a data distributor. Decoder can also be used as
demultiplexer.
In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND +9gates. The
data select lines enable only one gate at a time and the data on the data input line will pass
through the selected gate to the associated data output line.

PROCEDURE:

1. Do the connection as per block diagram shown below and switch ON the power supply.
2. Apply proper logic inputs o the Demultiplexer and observe the output on LEDs.

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3. Verify the function table of Demultiplexer.

PRECAUTIONS:

1) Make the connections according to the IC pin diagram.

2) The connections should be tight.
3) The Vcc and ground should be applied carefully at the specified pin only.

RESULT:

CONCLUSION:

VIVA QUESTIONS:

1. What do you understand by decoder?

2. What is demultiplexer?

3. What do you understand by encoder?

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4. What is the main difference between decoder and demultiplexer?

5. Why Binary is different from Gray code?

BLOCK DIAGRAM OF 8:1 MUX :

I/P SWITCHES

2G1G
1C0

1C1

1C2
I/P
1Y O/P
SWITCHES 1C3
2C0 LEDS
2Y
2C1

2C2

2C3
BA

I/P SWITCHES

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FUNCTION TABLE

Select I/p STROBE DATA INPUTS OUTPIT

B A 2G 1G 1C3 1C2 1C1 1C0 2Y 1Y
X X H H X X X X L L
CASE 1
L L H L L L L H L H
L H H L L L L H L L
H L H L L H L L L H
H H H L H L L L L H
CASE 2
B A 2G 1G 2C3 2C2 2C1 2C0 2Y 1Y
L L L H H H H L L L
L H L H H H H L H L
H L L H L H L L H L
H H L H L L L L L L

X = don’t care condition.

EXP NO: 04 DATE:

8:1 MULTIPLEXER
AIM: To verify the Functional Table using 8:1Multiplexer.

APPARATUS REQUIRED:

S.NO APPARATUS RANGE QUANTITY

1
1 IC IC 74153
1
2 Digital IC Trainer Kit
Required
3 Patch cards
1
4 Fixed Power Supply (0-5v)

THEORY:
The Multiplexers or data selector is a logic circuit that selects one out of several

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inputs to a single output. The input selected is controlled by a set of select lines. For selecting
one output line from n-input lines, a set of m-select lines is required. The relationship
between the number of input lines and the select lines is given by 2 m = n.

PROCEDURE:

1. Do the connection as per block diagram shown below and switch ON the power
supply.
2. Apply proper logic inputs o the Multiplexer and observe the output on LEDs.

3. Verify the function table of multiplexer in both the cases.

Internal Block Diagram OF 74153:

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RESULT :

CONCLUSION:

VIVA QUESTIONS:

1. What is a multiplexer?

2. What are the applications of multiplexer and de-multiplexer?

3. What is a de-multiplexer?

4. In 2n to 1 multiplexer how many selection lines are there?

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5. Implement an 8:1 mux using 4:1 muxes?

BLOCK DIAGRAM OF FULLADDER:

TRUTH TABLE

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X Y Z Sum Carry
(S) (C)
0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Exp No: 05 Date:

FULL ADDER

AIM: To verify the truth tables of Full Adder.

APPARATUS REQUIRED:

S.NO APPARATUS RANGE QUANTITY

IC’s 74LS08, 74LS32, 74LS04,

1 1
74LS00, 74LS02, 74LS86
2 Patch Chords REQUIRED
3 Fixed Power Supply (0-5v) 1
4 Digital IC Trainer Kit 1

THEORY:

Full adder
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A Full adder is a combinational circuit that performs addition of three input bits. Half adder
has inputs X, Y, Z and outputs sum (S) and carry(C).

The simplified Boolean expressions are

The logic circuit to implement is as shown below

FULL ADDER USING TWO HALF ADDERS AND OR GATE

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A full adder can also be implemented using two half adders and one OR gate as shown in
fig.The sum output from second half adder is

S=x EXOR y EXOR z S=x’y’z’+x’yz’+xy’z’+xyz

C=xy+yz+xz
PROCEDURE:

1. Connect A, B and C I/P of Full adder to switches from input switches section.
2. Connect SUM & CARRY O/P of Full Adder to LEDs from O/P LED section.
3. Switch ON the power supply of the Kit.
4. Provide proper inputs to Full adder using switches as per truth table of Full adder shown above.
5. Observe the O/P of Full Adder on LEDs.
6. Verify the functionality of Full Adder as per truth table & Note it down.

RESULT:

CONCLUSION

VIVA QUESTIONS:

1. What is use of Full adder?

2. What is difference between the half and full adder?

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3. How many half adders required to make a full adder?

4. In full adder how many types of gates are required?

5. Draw full adder circuit?

BLOCK DIAGRAM OF JK FLIP -FLOP:

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Where

Q Present State

Qt+1 Next State

Characteristic eqn Q t + 1 = J Q + K Q
i) Implementation of JK Flip-Flop Design:

IC – 74LS76: Dual –ve edge triggered JK Flip-Flop

Inputs Outputs
Q J K Qt + 1
0 0 0 0
0 0 1 0

0 1 0 1
0 1 1 1

1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

Truth Table of JK Flip – Flop

Fig: Pin diagram of 7476

Exp No: 06 Date:

JK & D FLIP-FLOP
AIM: Verification of functional tables of (i) JK Edge triggered Flip–Flop (ii) JK Master Slav Flip–
Flop (iii) D Flip-Flop

APPARATUS REQUIRED:

S.NO APPARATUS RANGE QUANTITY

IC 1
1 IC 7476,74107,7474
Digital IC Trainer Kit 1
2
REQUIRED
3 Patch cards
1
4 Fixed Power Supply (0-5v)

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THEORY:

Basically Flip-Flops are the bistable multivibrators that stores logic 1 and logic 0.Shift
registers, memory, and counters are built by using Flip – Flops. Any complex sequential
machines are build using Flip – Flops. Sequential circuit (machine) output depends on the
present state and input applied at that instant.
Mealy Machine is one whose output depends on both the present state and the input.
Moore machines one whose output depends only on the present state of the sequential circuit.
Note that the truth table of J – K Flip – Flop is same as the Master – Slave.
J – K Flip Flop and they must be remain same because IC – 7476is –ve edge trigged flip
– flop and we know that race around condition is eliminated by edge triggered flip – flop.
Another way of eliminating race around condition is by using Master – Slave J –K Flip – Flop.
When J = K = 1 (logic HIGH), J – K Flip – Flop changes output many times for single clock
pulse, it is Smaller than width of the clock pulse.

ii) Master Slave JK Flip – Flop:

IC – 74107: Dual – Master – Slave JK Flip-Flop

FIG: PIN DIAGRAM

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BLOCK IMPLEMENTATION:

Truth Table of Master – Slave – JK Flip – Flop:

Where
Q Present State
Qt+1 Next State

Input Outputs
s
Q J K Qt + 1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0 Characteristic eqn Q t + 1 =J Q+ K Q

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PROCEDURE:
JK FLIP_FLOP:
1. Connect PR to PRESET, CR to CLEAR and J and K terminals to the logic input
switches.
2. Connect CLK of JK flip-flop to Clock terminal.
3. Connect Q and /Q terminals to LED indicators in O/P section.
4. Set the PR, CR, CLK, J and K Signals by means of the switches as per the truth table of JK
flip-flop given above and verify the Q and /Q outputs by changing possible input condition.

MASTER SLAVE J-K FLIP-FLOP:

1. Do the connection for MS JK Flip-Flop as shown in Fig.7(c) above.

2. Connect PR to PRESET, CR to CLEAR of both the flip-flops and J and K terminals of
master flip-flop to the logic input switches.
3. Connect CLK of master JK flip-flop to Clock terminal.
4. Connect Q and /Q terminals of slave flip-flop to LED indicators in O/P LED section. Also
connect Q & /Q terminals of master flip-flop to the LEDs in O/P LED section.
5. Set the PR, CR, clk, J and K Signals by means of the switches as per the truth table of MS JK
flip-flop given above and verify the Q and /Q outputs.

D FLIP-FLOP:

1. Connect PR to PRESET, CR to CLEAR and D terminals to the logic input switch.

2. Connect the CLK of D Flip-Flop to CLOCK terminal.
3. Connect Q and /Q terminals to LED indicators in O/P LED section.
4. Set the PR, CR, CLK and D Signals by means of the switches as per the truth table of D flip-
flop given above and verify the Q and /Q outputs.

iii) D Flip – Flop:

IC – 7474: Dual + ve edge triggered D Flip-Flop:

FIG: PIN DIAGRAM

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BLOCK IMPLEMENTATION:

Truth Table of D Flip – Flop:

Inputs Outputs
Q J Qt + 1
0 0 0
0 1 1
1 0 0
1 1 1

Where
Q Present State
D Data Input
Qt + 1 Next State
Characteristic eqn Qt + 1 = D

RESULT:

CONCLUSION:

VIVA QUESTIONS:

1. What is flip-flop?

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2. How many types of flip-flop are used?

3. What are the characteristic equation for T flip-flop?

4. What is full form of T flip-flop?

5. Which Gates are used in SR flip flops to a JK flip-flop?

BLOCK DIAGRAM OF RING COUNTERS Using D Flip-Flop:

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Exp No: 07 Date:

RING COUNTER

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AIM: Design a four-bit ring counter using D Flip–Flop.

APPARATUS REQUIRED:

S.NO APPARATUS RANGE QUANTITY

IC 1
1 IC 7474
Digital IC Trainer Kit 1
2
REQUIRED
3 Patch cards
1
4 Fixed Power Supply (0-5v)

THEORY:

Ring counter and Johnson counters are basically shift registers.

Ring counter:

It is made by connecting Q&Q‟ output of one JK FF to J&K input of next FF respectively.

The output of final FF is connected to the input of first FF. To start the counter the first
FF is set by using preset facility and the remaining FF are reset input. When the clock arrives
the set condition continues to shift around the ring ,

As it can be seen from the truth table there are four unique output stages for this counter. The
modulus value of a ring counter is n, where n is the number of flip flops. Ring
counter is called divided by N counter where N is the number of FF

PROCEDURE:

1. Set up the ring counter and set clear Q outputs using PRESET and apply mono
pulse.
2. Note down the state of the ring counter on the truth table for successive clock 0.

RESULT:

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COCLUSION:

VIVA QUESTIONS:

1. What do you mean by Counter?

2. What is the ring counter?

3. What are the types of Counters? Explain each

4. Why asynchronous counters are called as ripple counters?

5. What are the applications of asynchronous counters?

BLOCK DIAGRAM OF JOHNSON COUNTER Using Flip-Flop:

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MODEL WAVEFORM:

Exp No: 08 Date:

JOHNSON’S COUNTER
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AIM: Design a four bit Johnson’s counter using JK Flip-Flops

APPARATUS REQUIRED:

S.NO APPARATUS RANGE QUANTITY

IC 1
1 IC 7476
Digital IC Trainer Kit 1
2
REQUIRED
3 Patch cards
1
4 Fixed Power Supply (0-5v)

THEORY:

Ring counter and Johnson counters are basically shift registers

Johnson counter (Twisted ring counter)

The modulus value of a ring counter can be doubled by making a small change in the ring counter
circuit. The Q‟ and Q of the last FFS are connected to the J and K input of the first FF respectively. This
is the Johnson counter.

Initially the FFs are reset. After first clock pulse FF0 is set and the remaining FFs are reset.
After the eight clock pulse all the FFS are reset. There are eight different conditions creating a
mode 8 Johnson counter. Johnson counter is called a twisted ring counter or divide by 2N
counter.

PROCEDURE:

1. Set up the Johnson counter and set clear Q outputs using PRESET and apply mono
pulse.
2. Note down the state of the Johnson counter on the truth table for successive clock 0.

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RESULT:

COCLUSION:

VIVA QUESTIONS:

1. What is the Johnson counter?

2. What is the difference between the counting sequence of an up counter and a down
counter?

3. What down you mean by down counter?

4. What is the advantage of Ripple counter over Synchronous Counter?

5. What are the applications of the counters?

BLOCK DIAGRAM OF USR:

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A) PIPO mode:

Expt No: 09 Date:

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UNIVERSAL SHIFT REGISTER

AIM: To study the following applications of the Universal shift register using IC 74194.
a.Left Shift Register
b.PIPO mode
c.Right Shift Register

APPARATUS REQUIRED:

S.NO APPARATUS RANGE QUANTITY

1 IC IC74LS194 1
2 Digital IC Trainer Kit
3 Patch card Required
4 Fixed Power Supply (0-5v) 1

THEORY:

Shift registers are the sequential logic circuits that can store the data temporarily and provides
the data transfer towards its output device for every clock pulse. These are capable of
transferring/shifting the data either towards the right or left in serial and parallel modes. Based
on the mode of input/output operations, shift registers can be used as a serial-in-parallel-out shift
register, serial-in-serial-out shift register, parallel-in-parallel-out shift register, parallel-in-
parallel-out shift register. Based on shifting the data, there are universal shift registers and
bidirectional shift registers. Here is a complete description of the universal shift register.
What is a Universal Shift Register?
Definition: A register that can store the data and /shifts the data towards the right and left along
with the parallel load capability is known as a universal shift register. It can be used to perform
input/output operations in both serial and parallel modes. Unidirectional shift registers and
bidirectional shift registers are combined together to get the design of the universal shift register.
It is also known as a parallel-in-parallel-out shift register or shift register with the parallel load.
Universal shift registers are capable of performing 3 operations as listed below.
 Parallel load operation – stores the data in parallel as well as the data in parallel
 Shift left operation – stores the data and transfers the data shifting towards left in the
serial path
 Shift right operation – stores the data and transfers the data by shifting towards right in
the serial path.

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PIN DIAGRAM OF RIGHT SHIFT REGISTER

TRUTH TABLE RIGHT SHIFT REGISTER

SR CLOCK QA QB QC QD O/P
1 0 0 0 0 0 0
2 1 1 0 0 0 8
3 2 1 1 0 0 12
4 3 1 1 1 0 14
5 4 1 1 1 1 15

LEFT SHIFT REGISTER

SR CLOCK O/P in
QA(MSB) QB QC QD
DEC
1 0 0 0 0 0 0
2 1 1 0 0 1 1
3 2 1 0 1 1 3
4 3 1 1 1 1 7
5 4 1 1 1 1 15

PROCEDURE:

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DLD LABORATORY (20A04303P) II B.Tech(ECE/EEE)

PIPO
 Set ABCD = 1010 using logic switches. Set S1 = S0 = ‘1’ or Logic HIGH, connect Clear of
Shift reg. to CLEAR terminal.
 Connect outputs QA to QD of reg. to LED indicators.
 Switch on the power supply. All Led indicators are in OFF positions.
 Now give clock signal to Shift register by CLOCK terminal, as soon as clock is reached to
Reg. led indicators will show 1010, which is the input we have set for register.
 Now change the data at input side using I/P switches & press clock switch, LED indication
now displays the new data. It means this shift register works as parallel in parallel out under
clock signal control.

RIGHT SHIT REGISTER

 Do the connection as per block diagram shown below,

 Set S1 = ‘0’, S0 = ‘1’, SL = X, SR = ‘1’. Connect Clear of Shift Reg. to CLEAR

terminal.
 Connect outputs QA to QD of reg. to LED indicators.
 Switch on the power supply. All Led indicators are in OFF positions.
 Now give clock signal to Shift register by CLOCK terminal and observe the LED
 From the above function table we can conclude that this register work as right shift register
as it shifts ‘1’ towards right by one position at every clock pulse.
 To start the counting again or to reset the register press CLEAR.

LEFT SHIT REGISTER

 Do the connection as per Right Shift register.

 Set S1 = ‘1’, S0 = ‘0’, SL = ‘1’ and SR = X. Connect Clear of Shift Register to CLEAR
terminal.
 Connect outputs QA to QD of reg. to LED indicators.
 Switch on the power supply. All Led indicators are in OFF positions.
 Now give clock signal to Shift register by CLOCK terminal and observe the LED indication.
 From the above function table we can conclude that this register work as Left shift register as
it shifts ‘1’ towards left by one position at every clock pulse.
 To start the counting again or to reset the register press CLEAR.
RESULT:

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DLD LABORATORY (20A04303P) II B.Tech(ECE/EEE)

CONCLUSION:

VIVA QUESTIONS:

1. What do you mean by shift register?

2. Explain the operation of a left shift register & a right shift register?

3. What is the difference between a register and shift register?

4. What is meant by universal shift register?

5. Explain the various modes in which the data can be entered or taken out from a register?

BLOCK DIAGRAM:

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DLD LABORATORY (20A04303P) II B.Tech(ECE/EEE)

FIG: 3- BIT ASYNCHRONOUS UP COUNTER

FIG: 4- BIT ASYNCHRONOUS DOWN COUNTER

Truth Table:

Up Counter Down Counter

Counter States F/F Output
Counter States F/F Output QA QB QC
QA QB QC 7 1 1 1
0 0 0 0 6 1 1 0
1 0 0 1 5 1 0 1
2 0 1 0 4 1 0 1
3 0 1 1 3 0 1 1
4 1 0 0 2 0 1 0
5 1 0 1 1 0 0 1
6 1 1 0 0 0 0 0
7 1 1 1

Exp No: 10 Date:

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DLD LABORATORY (20A04303P) II B.Tech(ECE/EEE)

MOD-8 RIPPLE COUNTER

AIM: Draw the circuit diagram of MOD-8 ripple counter and construct a circuit using T-Flip-Flops
and Test It with a low frequency clock and sketch the output waveforms.
APPARATUS REQUIRED:

S.NO APPARATUS RANGE QUANTITY

1
1 IC IC 7474
1
2 Digital IC Trainer Kit
Required
3 Patch cards
1
4 Fixed Power Supply (0-5v)

THEORY:

Asynchronous counter:

A digital counter is a set of flip flop. An Asynchronous counter uses T flip flop to perform a
counting function. The actual hardware used is usually J-K flip-flop connected to logic 1.
In ripple counter, the first flip-flop is clocked by the external clock pulse & then each successive
flip-flop is clocked by the Q or /Q‘ output the previous flip-flop. Therefore in an asynchronous
counter the flip-flop are not clocked simultaneously.
1. Up Counter:

Fig 3 shows 3 bit Asynchronous Up Counter. Here Flip-flop A act as a MSB Flip-flop and
Flip-flop C can act as a LSB Flip-flop. Clock pulse is connected to the Clock of flip-flop C.
Output of Flip-flop C (Qc) is connected to clock of next flip-flop(i.e. Flip-flop B) and so on. As
soon as clock pulse changes output is going to -change(at the negative edge of clock pulse) as a
Up count sequence. For 3 bit Up counter Truth table is as shown below.
2. Down Counter:

Fig 4 shows 3 bit Asynchronous Down Counter. Here Flip-flop a act as a MSB Flip-
flop and Flip-flop C can act as a LSB Flip-flop. Clock pulse is connected to the Clock of flip-
flop C. Output of Flip-flop C (Qc‘) is connected to clock of next flip- flop (i.e. Flip-flop B) and
so on. As soon as clock pulse changes output is going to change(at the negative edge of clock
pulse) as a down count sequence. For 3 bit down counter Truth table is as shown below.

TIMING DIAGRAM:

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DLD LABORATORY (20A04303P) II B.Tech(ECE/EEE)

1. 3 Bit Asynchronous Up Counter

CLK

Qa
0 0 0 0
3 1 1 1

Qb
0 0 1 1 0 0 1 1

Qc
0 0 0 0 1 1 1 1

2. 3 Bit Asynchronous Down Counter:

CLK

Qc 0 0
0 1 0 1 1 1

Qb 0 1 1 0 0 1 1 0

Qa 0 0 0 0
1 1 1 1

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DLD LABORATORY (20A04303P) II B.Tech(ECE/EEE)

PROCEDURE:
1. Assemble the different counters as shown in above diagrams using JK flip-flop and
verify its functionality by referring its function table.

PRECAUTIONS:
1. Make the connections according to the IC pin diagram.
2. The connections should be tight.
3. The Vcc and ground should be applied carefully at the specified pin only.

RESULT:

CONCLUSION:

VIVA QUESTIONS:

1. What do you understand by counter?

2. What is asynchronous counter?

3. What is synchronous counter?

4. Which flip flop is used in asynchronous counter?

5. Which flip flop is used in synchronous counter?

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DLD LABORATORY (20A04303P) II B.Tech(ECE/EEE)

BLOCK DIAGRAM OF MOD-8 COUNTER:

FIG: 3 BIT SYNCHRONOUS COUNTER

TRUTH TABLE:

QC QB QA
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0

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DLD LABORATORY (20A04303P) II B.Tech(ECE/EEE)

Exp No: 11 Date:

MOD–8 SYNCHRONOUS COUNTER
AIM: To Design MOD–8 synchronous counter using T Flip-Flop.

APPARATUS REQUIRED:

S.NO APPARATUS RANGE QUANTITY

1
1 IC IC 7476
1
2 Digital IC Trainer Kit
Required
3 Patch cards
1
4 Fixed Power Supply (0-5v)
.

THEORY:

A counter in which each flip-flop is triggered by the output goes to previous flip-flop. As all
the flip-flops do not change states simultaneously in asynchronous counter, spike occur at the
output. To avoid this, strobe pulse is required. Because of the propagation delay the operating
speed of asynchronous counter is low. This problem can be solved by triggering all the flip-flops
in synchronous with the clock signal and such counters are called synchronous counters.

PROCEDURE:
 Check all the components for their working.
 Insert the appropriate IC into the IC base.
 Make connections as shown in the circuit diagram.
 Verify the Truth Table and observe the outputs.

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RESULT:

CONCLUSION:

VIVA QUESTIONS:

1. What are synchronous counters?

2. What are the advantages of synchronous counters?

3. What is an excitation table?

4. Write the excitation table for D, T FF?

5. Design mod-5 synchronous counter using T FF?

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DLD LABORATORY (20A04303P) II B.Tech(ECE/EEE)

BLOCK DIAGRAM OF 1-BIT COMPARATOR:

7485
A0
_

A1 A >B

O/P LEDS
I/P A3 A=B
A2
SWITCHES
B0 A<B

B1
B2 B0

LT BI/RBO RBI

I/P SWITCHES

TRUTH TABLE:

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DLD LABORATORY (20A04303P) II B.Tech(ECE/EEE)

Exp No: 12(a) Date:

COMPARATOR

AIM: Draw the circuit diagram of a single bit comparator and test the output.

APPARATUS REQUIRED:

S.NO APPARATUS RANGE QUANTITY

1
1 IC 7485
1
2 Digital IC Trainer Kit
Required
3 Patch cards
1
4 Fixed Power Supply (0-5v)

THEORY:
Magnitude Comparator is a logical circuit, which compares two signals A and B and
generates three logical outputs, whether A > B, A = B, or A < B. IC 7485 is a high
speed 4-bit Magnitude comparator , which compares two 4-bit words . The A = B Input must
be held high for proper compare operation.

PROCEDURE:

1. Do the connection as per block diagram shown below and switch ON the power supply.
2. Give step by step inputs to A & B of comparator starting from MSB (A3 and B3).
3. Initially just observe the comparison between inputs A & B inputs and ignore the cascading
inputs.
4. Once all possible combinations for A & B inputs are over then apply cascading inputs as per
function table. Observe the outputs of comparator and verify it with function table.
5. Cascading inputs are used to increase the input line capacity of comparator.

Pin Diagram of 7485:

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RESULT:

CONCLUSION:

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VIVA QUESTIONS:

1. What is a comparator?

2. What are the applications of comparator?

3. Derive the Boolean expressions of one bit comparator and two bit comparators.

4. How do you realize a higher magnitude comparator using lower bit comparator

5. Design a 2 bit comparator using a single Logic gates?

\
BLOCK DIAGRAM OF SEVEN SEGMENT DIAGRAM:

7447
a

A
b
c B
I/P
d
C SWITCHES
e D
f

LT BI/RBO RBI

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I/P SWITCHES
DLD LABORATORY (20A04303P) II B.Tech(ECE/EEE)

TRUTH TABLE:

PIN FIAGRAM:

Exp No: 12(b) Date:

7 SEGMENT DISPLAY
AIM: Construct 7 Segment Display Circuit Using Decoder and7 Segment LED and test it.

APPARATUS REQUIRED:

S.NO APPARATUS RANGE QUANTITY

IC 1
1 7447
Digital IC Trainer Kit 1
2
REQUIRED
3 Patch cards
1
4 Fixed Power Supply (0-5v)

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DLD LABORATORY (20A04303P) II B.Tech(ECE/EEE)

THEORY:

The functions of LT, RBI, RBO and BI are given below. LT This is called the LAMP TEST
terminal and is used for segment testing. If it is connected to logic ‘0’ level, all the segements of
the display connected to the decoder will be ON. For normal decoding operation, this terminal is
to be connected to logic ‘1’ level. RBI For normal decoding operation, this is connected to logic
‘1’ level. If it is connected to logic ‘0’, the segment outputs will generate the data for normal 7-
segment decoding, for all BCD inputs except Zero. Whenever the BCD inputs correspond to
Zero, the 7-segment display switches off. This is used for zero blanking in multi-digit displays.
BI If it is connected to logic ‘0’ level, the display is switched-off irrespective of the BCD inputs.
This is used for conserving the power in multiplexed displays. RBO This output is used for
cascading purposes and is connected to the RBI terminal of the succeeding stage.

PROCEDURE:
1. Do the connection as per block diagram shown below and switch on the power supply.
2. For normal operation set LT = ‘1’ RBI = ‘1’ and BI/RBO = ‘1’. Apply input to the IC from I/P
switches as per the function table and observe the output on seven segment display
3. You can give output of onboard Decade counter (7490) as input to seven segment decoder.
Observe the output on Display. It displays from 0 to 9 digits.
4. You can also give output of onboard Binary counter (74191) as input to seven segment decoder.
Observe the output on Display. It displays digits as shown in the function table for 0 to 15.

RESULT:

CONCLUSION:

VIVA QUESTIONS:

1. What are the applications of seven segment display?

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DLD LABORATORY (20A04303P) II B.Tech(ECE/EEE)

2. Can you use the segments outputs of 7448 decoder directly to drive a 7-Segment LED? If
not suggest a suitable interface?

3. Describe the operation performed by the decoder?

4. What is the function of RBI input?

5. What is the difference between common anode & common cathode display?

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DLD LABORATORY (20A04303P) II B.Tech(ECE/EEE)

ADVANCED EXPERIMENTS

BLOCK DIAGRAM OF BCD ADDEER

INPUT OUTPUT

1st Operand 2nd Operand MSD LSD

A3 A2 A1 A0 B3 B2 B1 B0 Cout S3 S2 S1 S0
(MSB) (LSB) (MSB) (LSB) (MSB) (LSB)

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DLD LABORATORY (20A04303P) II B.Tech(ECE/EEE)

TABLE OF BCD ADDER:

EXP. NO: 13 Date:

BCD ADDER
AIM: Design BCD Adder Circuit and Test the Same using Relevant IC.

APPARATUS REQUIRED:

S.NO APPARATUS RANGE QUANTITY

1
1 IC 7483,7432,7408
1
2 Digital IC Trainer Kit
REQUIRED
3 Patch cards
4 Fixed Power Supply (0-5v) 1

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THEORY:

Carry Save Adder:

A carry save adder is just a set of one bit full adder, without any carry chaining. Therefore n-bit
CSA receivers three n-bit operands, namely A(n-1),A(0) and CIN(n-1)CIN(0) and generate two
n-bit result values, sum(n-1)-----------sum(0) and count(n-1)count(0).
Carry Propagation Adder:
The parallel adder is ripple carry type in which the carry output of each full adder stage is
connected to the carry input of the next highest order stage.
Therefore, the sum and carry outputs of any stage cannot be produced until the carry occurs. This
leads to a time delay in addition process.
This is known as Carry Propagation Delay.
BCD Adder:

It is a circuit that adds two BCD digits & produces a sum of digits also in BCD.

Rules for BCD addition:

1.Add two numbers using rules of Binary addition.
2.If the 4 bit sum is greater than 9 or if carry is generated then the sum is invalid. To correct the
sum add 0110 i.e. (6)10 to sum. If carry is generated from this addition add it to next higher
order BCD digit.
3.If the 4 bit sum is less than 9 or equal to 9 then sum is in proper form.

TruthTable:-
For design of combinational circuit for BCD adder to check invalid BCD

INPUT OUTPUT
S3 S2 S1 S0 Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0

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0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
K-map:-

For reduced Boolean expressions of output

Y= S3S2+S3S1

 CASE I: Sum <= 9 & carry = 0.

Add BCD digits 3 & 4

1. 0011

+ 0100

0111
Answer is valid BCD number = (7) BCD & so 0110 is not added.
CASE II: Sum > 9 & carry = 0.
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Add BCD digits 6 & 5

1. 0110

+ 0101

1011

Invalid BCD (since sum > 9) so 0110 is to be added

2. 1011

+ 0110

1 0001

(1 1)BCD

Valid BCD result = (11) BCD

CASE III: Sum < = 9 & carry = 1.

Add BCD digits 9 & 9

1. 1001

+1001

10010

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Invalid BCD (since Carry = 1) so 0110 is to be added

2.

1 00
10
+0110

11000

(1 8)BCD

Valid BCD result = (18) BCD

Design of BCD adder:

1.. 4 bit binary adder is used for initial addition. i.e. binary addition of two 4 bit numbers.(
. with Cin = 0 ),
2. Logic circuit to sense if sum exceeds 9 or carry = 1, this digital circuit will produce
high output otherwise its output will be zero.
3. One more 4-bit adder to add (0110)2 in the sum is greater than 9 or carry is 1.

RESULT:

CONCLUSION:

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VIVA QUESTIONS:
1. What is the need of code converters?

2. What is BCD Adder?

3. What is invalid BCD?

4. What are weighted codes and non-weighted codes?

5. What are applications of Gray code?

BLOCK DIAGRAM OF 4:1DE-MULTIPLEXER:

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TRUTH TABLE

CIRCUIT DIAGRAM:

Exp No:14 Date:

4:1DE-MULTIPLEXER

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DLD LABORATORY (20A04303P) II B.Tech(ECE/EEE)

AIM: - Verification of the truth table of the 4:1De-Multiplexer.

APPARATUS REQUIRED: -

S.NO APPARATUS RANGE QUANTITY

1
1 IC 7404,7411
1
2 Digital IC Trainer Kit
Required
3 Patch cards
1
4 Fixed Power Supply (0-5v)

THEORY:

A Demultiplexer performs the reverse operation of a Multiplexer. It accepts a single input

and distributes it over several outputs. The SELECT input code determines to which output the
data input will be transmitted. The Demultiplexer becomes enabled when the strobe signal is
active LOW.
This circuit can also be used as binary-to-decimal decoder with binary inputs applied at the select
input lines and the output will be obtained on the corresponding line. These devices are available
as 2-line-to-4-line decoder, 3-line-to- 8-line decoder, 4-line-to-16-line decoder. The output of
these devices is active LOW. Also there is an active low enable/data input terminal available.
Figure below shows the block diagram of a Demultiplexer.
In this diagram the inputs and outputs are indicated by means of broad arrows to indicate that
there may be one or more lines. Depending upon the digital code applied at the SELECT inputs,
one data is transmitted to the single output channel out of many. The pin out of a 16:1
Demultiplexer IC 74154 is shown above. The output of this circuit is active low. This is a 24-pin
DIP.
PROCEDURE: -

1) Assemble the circuit on bread board, as per above Pin diagram.

2) Give the logical inputs and check for the proper output, as per the truth table.

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PRECAUTIONS:

 All connections should be made neat and tight.

 Digital lab kits and ICs should be handled with utmost care.
 While making connections main voltage should be kept switched off.
 Never touch live and naked wires

RESULT:

CONCLUSION:

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VIVAQUESTIONS:

1. Why a De-multiplexer is called data distributor?

2. How does a De-multiplexer works?

3. Which IC is used for De-multiplexer?

4. What is difference between Multiplexer and De-multiplexer?

5. Can decoder be used as De-multiplexer?

SREE RAMA ENGINEERING COLLEGE, Dept of ECE. Page 66