Data Sheet

ADRF5141
Silicon, Transmit and Receive Switch with Limiter, 6 GHz to 12 GHz

FEATURES FUNCTIONAL BLOCK DIAGRAM

► High-power transmit and receive switch with an integrated power
limiter on receive path
► Frequency range: 6 GHz to 12 GHz
► Reflective 50 Ω design
► Low insertion loss
► TX to ANT: 0.9 dB at 8 GHz to 11 GHz
► ANT to RX: 1.4 dB at 8 GHz to 11 GHz
► High isolation: 55 dB typical for TX to RX when TX selected
► High-power handling (TCASE = 50°C)
► Input at TX: pulsed 40 dBm, >100 ns pulse width at 15% duty
cycle
► Input at ANT: pulsed 40 dBm, >100 ns pulse width at 15%
duty cycle Figure 1. Functional Block Diagram
► RX flat leakage: 17 dBm
► High linearity GENERAL DESCRIPTION
► Input P0.1dB at TX arm: 41 dBm
The ADRF5141 is a reflective, SPDT switch manufactured in the
► Fast switching time: 50 ns silicon process. The ADRF5141 is used in transmit and receive
► Fast response and recovery time: <10 ns applications with an integrated power limiter on the receive path.
► Dual-supply, with no low-frequency spurious
The ADRF5141 operates from 6 GHz to 12 GHz. The RX arm with
► Positive control interface: CMOS-/LVTTL-compatible the integrated power limiter has a flat leakage of 17 dBm with a low
► 20-lead, 3 mm × 3 mm LGA package insertion loss of 1.4 dB at 8 GHz to 11 GHz. The TX arm has an
► Pin compatible with the ADRF5144 insertion loss of 0.9 dB at 8 GHz to 11 GHz.
APPLICATIONS The ADRF5141 draws a low current of 13 μA on the positive supply
of +3.3 V and 360 μA on the negative supply of −3.3 V. The device
► X-band communications and radars employs complementary metal-oxide semiconductor (CMOS)-/low
► Electronic warfare voltage transistor to transistor logic (LVTTL)-compatible controls.
► Satellite communications The ADRF5141 requires no additional driver circuitry, making it
► GaN and PIN diode replacement
an ideal alternative to gallium nitride (GaN) and PIN diode-based
switches.
The ADRF5141 comes in a 20-lead, 3.0 mm × 3.0 mm, RoHS-com-
pliant, land grid array (LGA) package and can operate from −40°C
to +105°C.

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
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Data Sheet ADRF5141
TABLE OF CONTENTS

Features................................................................ 1 Typical Performance Characteristics..................... 7

Applications .......................................................... 1 Insertion Loss, Isolation, and Return Loss......... 7
Functional Block Diagram......................................1 Input Power Compression, POUT vs. PIN,
General Description...............................................1 and Input IP3.................................................... 8
Specifications........................................................ 3 Theory of Operation.............................................10
Absolute Maximum Ratings...................................5 Power Supply................................................... 10
Thermal Resistance........................................... 5 RF Input and Output.........................................10
Power Derating Curve........................................ 5 Applications Information...................................... 11
Electrostatic Discharge (ESD) Ratings...............5 Recommendations for PCB Design..................11
ESD Caution.......................................................5 Outline Dimensions............................................. 13
Pin Configuration and Function Descriptions........ 6 Ordering Guide.................................................13
Interface Schematics..........................................6 Evaluation Boards............................................ 13

REVISION HISTORY

10/2022—Revision 0: Initial Version

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Data Sheet ADRF5141
SPECIFICATIONS

Positive supply voltage (VDD) = 3.3 V, negative supply voltage (VSS) = −3.3 V, CTRL voltage (VCTRL) = 0 V or 3.3 V, and TCASE = 25°C, with a 50
Ω system, unless otherwise noted.

Table 1. Specifications
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE f 6 12 GHz
INSERTION LOSS 8 GHz to 11 GHz
TX to ANT 0.9 dB
ANT to RX 1.4 dB
6 GHz to 12 GHz
TX to ANT 1.1 dB
ANT to RX 1.7 dB
RETURN LOSS 8 GHz to 11 GHz
ANT 13 dB
TX (On) 16 dB
RX (On) 18 dB
6 GHz to 12 GHz
ANT 11 dB
TX (On) 13 dB
RX (On) 12 dB
ISOLATION 8 GHz to 11 GHz
TX to ANT RX selected 28 dB
ANT to RX TX selected 58 dB
TX to RX TX selected 55 dB
6 GHz to 12 GHz
TX to ANT RX selected 26 dB
ANT to RX TX selected 55 dB
TX to RX TX selected 55 dB
SWITCHING CHARACTERISTICS
Rise and Fall Time tRISE, tFALL 10% to 90% of RF output 15 ns
On and Off Time tON, tOFF 50% VCTRL to 90% of RF output 50 ns
RF Settling Time
0.1 dB 50% VCTRL to 0.1 dB of final RF output 65 ns
LIMITER Pulsed 40 dBm, 5% duty cycle, >100 ns pulse width
Response Time <10 ns
Recovery Time <10 ns
RX Flat Leakage 17 dBm
INPUT LINEARITY 8 GHz to 11 GHz
TX Arm
0.1dB Compression P0.1dB 41 dBm
1dB Compression P1dB 43 dBm
Third-Order Intercept IP3 2-tone input power = 20 dBm each tone, Δf = 1 MHz 58 dBm
RX Arm
0.1dB Compression P0.1dB 14 dBm
1dB Compression P1dB 17 dBm
Third-Order Intercept IP3 2-tone input power = 2 dBm each tone, Δf = 1 MHz 43 dBm
DIGITAL CONTROL INPUTS CTRL pin
Voltage
Low VINL 0 0.8 V
High VINH 1.2 3.3 V
Current

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Data Sheet ADRF5141
SPECIFICATIONS

Table 1. Specifications
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Low and High IINL, IINH <1 µA
SUPPLY CURRENT VDD and VSS pins
Positive Supply Current IDD 13 µA
Negative Supply Current ISS 360 µA
RECOMMENDED OPERATING CONDITONS
Supply Voltage
Positive VDD 3.15 3.45 V
Negative VSS −3.45 −3.15 V
Digital Control Voltage VCTRL 0 VDD V
RF Power PIN
Input at TX1 f = 8 GHz to 11 GHz, TCASE = 85°C2
Continuous Wave 36 dBm
Pulsed3 5% duty cycle, >100 ns pulse width, TCASE = 85°C 40 dBm
15% duty cycle, >100 ns pulse width, TCASE = 50°C 40 dBm
Peak 5% duty cycle, ≤100 ns peak duration 43 dBm
Input at ANT f = 6 GHz to 12 GHz, TCASE = 85°C2
Continuous Wave 33 dBm
Pulsed3 5% duty cycle, >100 ns pulse width, TCASE = 85°C 40 dBm
15% duty cycle, >100 ns pulse width, TCASE = 50°C 40 dBm
Peak 5% duty cycle, ≤100 ns peak duration 40 dBm
Case Temperature TCASE −40 +105 °C
1 For power derating vs. frequency for input at TX, see Figure 2.
2 For 105°C operation, the power handling degrades from the TCASE = 85°C specifications by 3 dB.
3 For different pulsed conditions, please contact applications support.

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Data Sheet ADRF5141
ABSOLUTE MAXIMUM RATINGS

For recommended operating conditions, see Table 1. Table 3. Thermal Resistance

Package Type θJC1 Unit
Table 2. Absolute Maximum Ratings
Parameter Rating TX Path 45 °C/W
RX Path 28.6 °C/W
VDD −0.3 V to +3.6 V
1 θJC was determined by simulation under the following conditions: the heat
VSS −3.6 V to +0.3 V
Digital Control Input transfer is due solely to the thermal conduction from the channel through the
Voltage −0.3 V to VDD + 0.3 V ground pad to the PCB, and the ground pad is held constant at the operating
Current 3 mA temperature of 85°C.
RF Power POWER DERATING CURVE
Input at TX1 (f = 8 GHz to 11 GHz, TCASE = 85°C2)
Continuous Wave 36.5 dBm
Pulsed (5% duty cycle, >100 ns pulse width, 40.5 dBm
TCASE = 85°C)
Pulsed (15% duty cycle, >100 ns pulse width, 40.5 dBm
TCASE = 50°C)
Peak 43.5 dBm
Input at ANT (f = 6 GHz to 12 GHz, TCASE = 85°C2)
Continuous Wave 33.5 dBm
Pulsed (5% duty cycle, >100 ns pulse width, 40.5 dBm
TCASE = 85°C)
Pulsed (15% duty cycle, >100 ns pulse width, 40.5 dBm
TCASE = 50°C)
Peak 40.5 dBm
RF Power Under Unbiased Condition (VDD and VSS =
0 V) Figure 2. Power Derating vs. Frequency for Input at TX, TCASE = 85°C
Input at ANT 33 dBm
ELECTROSTATIC DISCHARGE (ESD) RATINGS
Temperature
Junction, TJ 135°C The following ESD information is provided for handling of ESD-sen-
Storage −65°C to +150°C sitive devices in an ESD protected area only.
Reflow 260°C
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
1 For power derating vs. frequency for the input at TX, see Figure 2.
2
Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002.
For 105°C operation, the power handling degrades from the TCASE = 85°C
specifications by 3 dB.
ESD Ratings for ADRF5141
Stresses at or above those listed under Absolute Maximum Ratings Table 4. ADRF5141, 20-Terminal LGA
may cause permanent damage to the product. This is a stress ESD Model Withstand Threshold (V) Class
rating only; functional operation of the product at these or any other
HBM ±2000 for All Pins 2
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operat- CDM ±1250 for All Pins C3
ing conditions for extended periods may affect product reliability. ESD CAUTION
THERMAL RESISTANCE ESD (electrostatic discharge) sensitive device. Charged devi-
ces and circuit boards can discharge without detection. Although
Thermal performance is directly linked to printed circuit board
this product features patented or proprietary protection circuitry,
(PCB) design and operating environment. Careful attention to PCB
damage may occur on devices subjected to high energy ESD.
thermal design is required.
Therefore, proper ESD precautions should be taken to avoid
θJC is the junction to case bottom (channel to package bottom) performance degradation or loss of functionality.
thermal resistance.
Table 3. Thermal Resistance
Package Type θJC1 Unit
CC-20-9

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Data Sheet ADRF5141
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration (Top View)

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description
1, 2, 4 to 8, 10, 11, 15, 16, 18 to 20 GND Ground. The GND pins must be connected to the RF and DC ground of the
PCB.
3 ANT Antenna Port. Th ANT pin is DC-coupled to 0 V and AC matched to 50 Ω. No
DC blocking capacitor is necessary when the RF line potential is equal to 0 V
DC. See Figure 4 for the interface schematic.
9 RX Receive Port. Th RX pin is DC-coupled to 0 V and AC matched to 50 Ω. No
DC blocking capacitor is necessary when the RF line potential is equal to 0 V
DC. See Figure 4 for the interface schematic.
12 CTRL Control Input. See Figure 5 for the interface schematic.
13 VDD Positive Supply Voltage Pin. See Figure 6 for the interface schematic.
14 VSS Negative Supply Voltage Pin. See Figure 7 for the interface schematic.
17 TX Transmit Port. The TX pin is DC-coupled to 0 V and AC matched to 50 Ω. No
DC blocking capacitor is necessary when the RF line potential is equal to 0 V
DC. See Figure 4 for the interface schematic.
EPAD Exposed Pad. The exposed pad must be connected to the RF and DC
ground of the PCB.

INTERFACE SCHEMATICS

Figure 4. ANT, TX, and RX Pins Interface Schematic

Figure 6. VDD Pin Interface Schematic

Figure 5. CTRL Interface Schematic

Figure 7. VSS Pin Interface Schematic

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Data Sheet ADRF5141
TYPICAL PERFORMANCE CHARACTERISTICS

INSERTION LOSS, ISOLATION, AND RETURN LOSS

VDD = 3.3 V, VSS = −3.3 V, VCTRL = 0 V or VDD, and TCASE = 25°C, with a 50 Ω system, unless otherwise noted. Measured on the
ADRF5141-EVALZ.

Figure 8. Insertion Loss vs. Frequency at Room Temperature for TX and RX Figure 11. Insertion Loss vs. Frequency over Temperature for TX

Figure 9. Insertion Loss vs. Frequency over Temperature for RX Figure 12. Return Loss vs. Frequency

Figure 10. Isolation vs. Frequency

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Data Sheet ADRF5141
TYPICAL PERFORMANCE CHARACTERISTICS

INPUT POWER COMPRESSION, POUT VS. PIN, AND INPUT IP3

VDD = 3.3 V, VSS = -3.3 V, VCTRL = 0 V or VDD V, and TCASE = 25°C in a 50 Ω system, unless otherwise noted. All of the large-signal
performance parameters are measured on the ADRF5141-EVALZ.

Figure 13. Input 0.1dB Power Compression vs. Frequency over Temperature Figure 15. Input 1dB Power Compression vs. Frequency over Temperature
for TX for TX

Figure 14. Input 0.1dB Power Compression vs. Frequency over Temperature Figure 16. Input 1dB Power Compression vs. Frequency over Temperature
for RX for RX

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Data Sheet ADRF5141
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 17. Output Power (POUT) vs. PIN over Temperature at 10 GHz for RX Figure 20. Input IP3 vs. Frequency for RX

Figure 18. POUT vs. PIN over Frequency at Room Temperature for RX

Figure 19. Input IP3 vs. Frequency for TX

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Data Sheet ADRF5141
THEORY OF OPERATION

The ADRF5141 integrates a driver to perform logic function inter- RF INPUT AND OUTPUT
nally and to provide the advantage of a simplified control interface.
The driver features a single-control input pin (CTRL) that controls All RF ports (ANT, RX, and TX) are DC-coupled to 0 V. When the
the state of the RF paths, determining which RF port is in an RF line DC potential is at 0 V, no DC blocking is required at the RF
insertion loss state and which RF port is in an isolation state (see ports.
Table 6). The RF ports are internally matched to 50 Ω; therefore, no external
POWER SUPPLY matching networks are required.
Table 6. Control Voltage Truth Table
The ADRF5141 requires a positive supply voltage applied to the
Digital Control Input RF Paths
VDD pin and a negative supply voltage applied to the VSS pin.
Bypassing capacitors are recommended on the supply lines to CTRL TX to ANT ANT to RX
minimize RF coupling. Low Insertion loss (on) Isolation (off)
High Isolation (off) Insertion loss (on)
The ideal power-up sequence is as follows:
1. Connect to ground.
2. Power up VDD and VSS. Power up VSS after VDD to avoid
current transients on VDD during ramp-up.
3. Power up the digital control input (CTRL). Power up CTRL be-
fore the VDD supply can inadvertently forward bias and damage
the internal ESD protection structures. To avoid this damage,
use a series 1 kΩ resistor to limit the current flowing into the
CTRL pin. Use pull-up or pull-down resistors if the controller
output is in a high-impedance state after VDD is powered up and
the CTRL pin is not driven to a valid logic state
4. Apply an RF input signal.
The ideal power-down sequence is the reverse order of the power-
up sequence.

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Data Sheet ADRF5141
APPLICATIONS INFORMATION

The ADRF5141 has two power-supply pins (VDD and VSS) and RECOMMENDATIONS FOR PCB DESIGN
one control pin (CTRL). Figure 21 shows the external components
and connections for the supply and control pins. The VDD pin is The RF ports are matched to 50 Ω internally and the pinout is
decoupled with 100 pF and 1000 pF multilayer ceramic capacitor, designed to mate a coplanar waveguide (CPWG) with 50 Ω charac-
while the VSS pin and the control pin are decoupled with 100 teristic impedance on the PCB. Figure 23 shows the referenced
pF multilayer ceramic capacitor. The device pinout allows the place- CPWG RF trace design for an RF substrate with 8 mil thick Rogers
ment of the decoupling capacitors close to the device. No other RO4003 dielectric material. RF trace with 14 mil width and 7 mil
external components are needed for bias and operation, except clearance is recommended for 1.5 mil finished copper thickness.
DC-blocking capacitors on the ANT, TX, and RX pins when the RF
lines are biased at a voltage different than 0 V. Refer to the Pin
Configuration and Function Descriptions section for details.

Figure 23. Example PCB Stack-Up

Figure 24 shows the routing of the RF traces, supply, and control

signals from the device. The ground planes are connected with as
many filled, through vias as allowed for optimal RF and thermal
performance. The primary thermal path for the device is the bottom
side; therefore, a heatsink is required underneath the PCB to
ensure maximum heat dissipation and to reduce thermal rise on the
Figure 21. Recommended Schematic PCB during high-power applications.

The power limiter at the RX arm engages and limits the input
power from the ANT power. See the Table 1 section for the RX
flat Leakage power level. A typical application of the ADRF5141
is to connect an antenna at the ANT pin, a power amplifier (PA)
at the TX pin, and a low-noise amplifier (LNA) at the RX pin. The
integrated power limiter at the RX arm provides protection to the
LNA input connected to the RX pin (see Figure 22).

Figure 24. PCB Routings

Figure 25 shows the recommended layout from the device RF pins

to the 50 Ω CPWG on the referenced stack-up. PCB pads are
drawn 1:1 to device pads. The ground pads are drawn soldermask
defined, and the signal pads are drawn as pad defined. The RF
trace from the PCB pad is extended with the same width till the
package edge and tapered to the RF trace with a 45° angle.
The paste mask is also designed to match the pad without any
Figure 22. Typical Application Diagram aperture reduction. The paste is divided into multiple openings for
the paddle.

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Data Sheet ADRF5141
APPLICATIONS INFORMATION

Figure 25. Recommended RF Pin Transitions

For alternate PCB stack-ups with different dielectric thickness and

CPWG design, contact Analog Devices, Inc., Technical Support
Request for further recommendations.

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Data Sheet ADRF5141
OUTLINE DIMENSIONS

Figure 26. 20-Terminal Land Grid Array [LGA]

3 mm × 3 mm Body and 0.75 mm Package Height
(CC-20-9)
Dimensions shown in millimeters

Updated: October 22, 2022

ORDERING GUIDE
Model1 Temperature Range Package Description Packing Quantity Package Option
ADRF5141BCCZN −40°C to +105°C 20-Terminal Land Grid Array [LGA] Reel, 500 CC-20-9
ADRF5141BCCZN-R7 −40°C to +105°C 20-Terminal Land Grid Array [LGA] Reel, 500 CC-20-9
1 Z = RoHS Compliant Part.

EVALUATION BOARDS

Table 7. Evaluation Boards

Model1 Description
ADRF5141-EVALZ Evaluation Board

1 Z = RoHS-Compliant Part.

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registered trademarks are the property of their respective owners.
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