International Journal of Control and Automation

Vol.10, No.8 (2017), pp.105-116

http://dx.doi.org/10.14257/ijca.2017.10.8.09

A Two-Stage Cascaded Multi-Level Inverter

Zhi Xu1, Shengnan Li1*, Risheng Qin1 and Yanhang Zhao2

1
Electric Power Research Institute, Yunnan Electric Power
Company, Kunming, China
xuzhi1123@163.com, lsn788@sina.com*, 514927517@qq.com
2
State Key Laboratory of Power Transmission Equipment & System Security and
New Technology, Chongqing University, Chongqing, China
zhaoyanhang@cqu.edu.cn

Abstract
The cascaded H-bridge multi-level inverter has been extensively applied to
middle-high voltage and high power fields, but it has disadvantages of numerous DC
voltage sources and switch tubes. Based on this reason, this paper presents a two stage
cascaded multilevel inverter. The preceding stage is composed of several basic modules
through cascading, and the backward stage is H-bridge inverter. The direct voltage use
ratio of every basic module in this inverter is increased by 2 times, and the number of DC
voltage sources and switch tubes is reduced effectively. In addition, H-bridge at the
backward stage operates under power frequency conditions only, which can further
reduce the switching loss. According to the new type of inverter, this paper proposes
carrier cascading modulation and hysteresis control method combining. The cascaded
multilevel inverter can output a variety of level. Finally, simulation model of the inverter
is built up, the input and load jump of the two working modes are simulated and analyzed.
The performance of the proposed inverter are verified by simulation.

Keywords: Multi-Level inverter; Cascade; Carrier Disposition; Voltage utilization

1. Introduction
At the high power application site, such as combination of photovoltaic power
generation, wind power generation, and new energy power generation, the multi-level
inverter is becoming a mainstream choice by providing good big voltage and large
current[1, 2]. Compared with two-level inverters, the devices of multi-level inverter
possess small stress, which has effectively increased the power level. Under the same
switching frequency, the harmonic distortion rate is reduced, and the quality of output
waveform is increased. Besides the above advantages, the cascaded multi-level inverter is
characterized by modularization and easy extension, but the high number of DC voltage
sources and switch tubes has restricted its application in industry[3-5].
The traditional cascaded H-bridge multilevel inverter outputs 2N+1 levels, requiring N
DC input sources and 4N switch tubes[6-7]. By directing at the high number of switch
tubes in cascaded H-bridge topology, related experts have proposed a new topological
structure literature, which has reduced the number of switch tubes by half[8]. Besides, the
cascaded H-bridge multilevel topology is improved in many aspects. The number of
switch tubes is reduced to a certain extent, but the number of conductive switch tubes is
not decreased. And researchers have turned the switch number almost reduced to 1/4, and
only three switch tubes are conductive at any time, but the number of DC voltage sources
remains unchanged[9]. The diode-clamped, flying capacitor and hybrid cascaded
multi-level inverter has reduced the number of DC voltage sources to a certain extent, but
will increase the number of switch tubes.

ISSN: 2005-4297 IJCA

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In order to overcome the above problems, this paper puts forward a cascaded
multi-level inverter by setting three-level module as the basic unit, which has reduced the
number of DC voltage sources by half and almost decreased the number of switch tubes
by half.

2. Topology of Multilevel Inverter

2.1. Multi-level DC/DC Convertor
The basic modules of cascaded multi-level DC/DC convertor are presented in
Figure 1(a), and it is composed of 1 input voltage source V in (V in=Vdc), 2 DC-link
capacitors (C 1 and C2), 2 diodes (D 1 and D 2), 2 capacitance charge-discharge control
switches Q 1 and Q 2 (unidirectional switches), and 3 level selection switches S 0, S 1
and S2 (bidirectional switches). According to Figure 1(a), Q 1 and Q 2 cannot be
conductive at the same time, otherwise, short-circuit fault will happen to the input
voltage source. In addition, only one switch in S 0, S 1 and S2 can be conductive at the
same time, otherwise, short-circuit fault will happen to capacitors C 1 and C 2.
S2 S2 S2

C2 C2 C2
Q2 Q2 Q2
S1 S1 S1
Vin Vin Vin
Vo
Vo Vo
Q1 C1 Q1 C1 Q1 C1

S0 S0 S0

(1) (2) (3)

S2
S2 S2 S2

C2 C2 C2
Q2 Q2 Q2
S1 S1 S1
Vin Vin Vin
Vo Vo Vo
C1 Q1 C1 Q1 C1
Q1

S0 S0 S0

(4) (5) (6)

S2 S2 S2

C2 C2 C2
Q2 Q2 Q2
S1 S1 S1
Vin Vin Vin
Vo Vo Vo
C1 Q1 C1 Q1 C1
Q1

S0 S0 S0

(7) (8) (9)

(b)

S2
S2

Vc 2
C2
Q2 S1
S1
Vin Vo
Vo
Q1 C1 Vc1
S0
S0

(a) (c)

Figure 1. Basic Module Working State

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Figure 1(b) gives 9 operating states of basic modules, and the 9 operating states of
basic modules are elaborated in the following:
Mode 1: Q1, D2 and S0 are conductive, and other switches are cut off. At this time,
capacitor C2 is in a charging state. Vc2=Vin=Vdc; Vo=0.
Mode 2: Q1, D2 and S1 are conductive, and other switches are cut off. At this time,
capacitor C2 is in a charging state. Vc2=Vin=Vdc; Vo=Vc1=Vdc.
Mode 3: Q1, D2 and S2 are conductive, and other switches are cut off. At this time,
capacitor C2 is in a charging state. Vc2=Vin=Vdc; Vo=Vc1+Vc2=2Vdc.
Mode 4: Q2, D1 and S0 are conductive, and other switches are cut off. At this time,
capacitor C1 is in a charging state. Vc1=Vin=Vdc; Vo=0.
Mode 5: Q2, D1 and S1 are conductive, and other switches are cut off. At this time,
capacitor C1 is in a charging state. Vc1=Vin=Vdc; Vo= Vc1=Vdc.
Mode 6: Q2, D1 and S2 are conductive, and other switches are cut off. At this time,
capacitor C1 is in a charging state. Vc1=Vin=Vdc; Vo= Vc1+Vc2=2Vdc.
Mode 7: S0 is conductive, and other switches are cut off. At this time, capacitors C1
and C2 are in a discharging state. Vc1=Vin=Vdc; Vo=0.
Mode 8: S1 is conductive, and other switches are cut off. At this time, capacitors C1
and C2 are in a discharging state. Vo= Vc1=Vdc.
Mode 9: S2 is conductive, and other switches are cut off. At this time, capacitors C1
and C2 are in a discharging state. Vo= Vc1+Vc2=2Vdc.
According to Figure 1(b), when the switching period T of Q1 and Q2 is small,
Vc1=Vc2=Vin=Vdc, and the equivalent circuit of basic modules is shown in Figure 1(c).
Table 1 shows the relation between the output voltage Vo of basic modules and switching
state of S0, S1 and S2 under different operating states. According to Table 1, basic modules
have three level outputs: 0, Vdc and 2Vdc.

Table 1. Switching state

S0 S1 S2 Vo
1 0 0 0
0 1 0 Vdc
0 0 1 2Vdc

For every basic module, the switch function Si is defined, as shown in formula (1):
 1, switch on
Si   (i  0,1,2) (1)
 0, switch off
The output levels of basic modules can be unified into:
Vo=i·Vdc if Si=1 for i=0,1,2 (2)
The typical output waveform of basic modules in one period can be worked out
according to formulas (1) and (2), as shown in Figure 2.

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Vin
Vdc

S0

S1

S2

Vo
2Vdc
Vdc

T T
2 2

Figure 2. Output Waveform of Basic Modules in One Period

The topological structure of cascaded multi-level DC/DC convertor can be gained

through cascading of several modules, as shown in Figure 3. It’s worth noting that the
total output voltage of multi-level DC/DC convertor is the sum of the output voltages of
all basic modules.
Vo(t)=Vo,1(t)+ Vo,2(t) +Vo,3(t)+……+ Vo,n(t) (3)
If Vin,j=Vdc(j=1,2,……，n), the following formula can be gained according to formula (2)
 in )  Vdc  Vdc   j 1i j
n
Vo (t )  (i1  i2  i3  (4)
ij represents the quantity of levels output by basic module j, and it meets the following
formula:
 2, if S2, j  1

i j   1, if S1, j  1 for j  0,1,2 n (5)
 0,
 if S 0, j  1
Therefore, the maximum output voltage of multi-level DC/DC convertor is
Vomax=2n·Vdc. The maximum quantity of levels output is 2n, and levels of any quantity in
0-2n can be output.

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Sn _ 2

Cn _ 2
Qn _ 2
Sn _1
Vin _ n Von (t)

Qn _1 Cn _1

Sn _ 0

S2 _ 2

Vo (t )
C2 _ 2
Q2 _ 2
S2 _1
Vin _ 2
Vo2 (t)
Q2 _1 C2 _1

S2 _ 0

S1_ 2

C1_ 2
Q1_ 2
S1_1
Vin _1
Vo1 (t)
Q1_1 C1_1

S1_ 0

Figure 3. Cascaded Multi-Level DC/DC Convertor

2.2. Cascaded Multi-level Inverter

Through the series connection of an H-bridge to the output end of multi-level DC/DC
convertor presented in Figure 3, we can form a cascaded multi-level inverter, as shown in
Figure 4. The switching states of 4 switch tubes at H-bridge decide the direction of load
voltage Vl. Table 2 displays the relation between Vo and Vl under 4 switching states of
H-bridge. The following conclusions can be gained easily according to Table 2. When H1
and H3 are conductive, and H2 and H4 are cut off, Vl has the same direction with Vo. When
H2 and H4 are conductive, and H1 and H3 are cut off, Vl and Vo present a reverse
direction. Figure 5 shows the common waveform of 7-level inverter composed of 3
modules. Within the period 0-0.5T, Vl=Vo; within the period 0.5T-T, Vl=-Vo.
Vl  Vo (6)
 +Vo , if H1,3 on, H 2,4 off
Vl   (7)
  Vo , if H 2,4 on, H 1,3 off

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Table 2. Switching States of the Cascaded Multi-Level Converter

H1 H2 H3 H4 Vl
1 0 0 1 +Vo
0 1 1 0 -Vo
1 0 1 0 0
0 1 0 1 0

Sn _ 2

Cn _ 2
Qn _ 2
Sn _1
Vin _ n Von (t)

Qn _1 Cn _1

Sn _ 0
Vo (t )

S2 _ 2

H1 H3
C2 _ 2
Q2 _ 2
S2 _1 
Vin _ 2 Vo2 (t) Vl

Q2 _1 C2 _1
H2 H4
S2 _ 0

S1_ 2

C1_ 2
Q1_ 2
S1_1
Vin _1
Vo1 (t)
Q1_1 C1_1

S1_ 0

Figure 4. Two-Stage Cascaded Multi-Level Inverter

3. Modulation Strategy
The two-level H-bridge carrier phase-shift modulation technique has already been quite
mature, but it cannot be directly applied to the inverter proposed in this paper. The
quantity of output levels of basic modules is 3, so the modulation method of combining
laminated carrier modulation with carrier phase-shift modulation is adopted in this paper.
1) Laminated carrier modulation is adopted in the single module;
2) The carrier phase-shift modulation is adopted between the modules.

3.1. Laminated Carrier Modulation

The control signal of a single basic module is shown in Figure 5. A comparison is made
between the values of carrier signal and reference signal Vref via the comparator.
Moreover, the comparison results are recorded as Ca and Cb. The waveform of output
voltage V0 can be drawn according to Ca and Cb. And then the drive signals of switching

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devices S0, S1 and S2 are determined via switch function (8). It’s worth noting that basic
modules only output zero or positive levels, so if the reference signal shows negative
half-cycle, the absolute value should be taken before it is compared with the carrier wave.
In this way, the quantity of carrier waves can be reduced by half.
S0  Cb
S1  Ca  Cb (8)
S2  Ca

Ⅰ Ⅱ Ⅲ Ⅳ Ⅴ
C1 C2
-2Vdc -Vdc 0 Vdc 2Vdc
Ⅴ

C4 C3 Ⅰ

S0

S1

S2

Figure 5. Laminated Carrier Modulation Strategy

3.2. Carrier Phase-Shift Modulation

Suppose that the number of modules is n. Then the carrier phase angle difference of
every module is 360°/n. The carrier wave of module j is defined as Ca,j and Cb,j. Then the
initial phase angles of Ca,1, Ca,2, Ca,3……Ca,n are 0, 360°/n, 720°/n……360°respectively;
Cb,j has the same initial phase angle as Ca,j. Therefore, the drive signal of basic module j is
as follows:
S0, j = Cb, j
S1, j = Ca, j  Cb, j (9)
S2, j = Ca, j

3.3. Q1 and Q2 Control Strategy

Under the influences of circuit parameter and load jump, voltage unbalance will happen
to the tandem split capacitors in DC-link during the operation process. As a result, the
harmonic distortion rate will increase, and the output waveform quality will deteriorate.
By adding PI control into the preceding-stage circuit, we can realize capacitor voltage
balance. By taking C1 and C2 in Figure 1 as an example, when the voltage of capacitor C1
is higher than that of C2, Q2 is cut off, Q1 is conductive, C1 discharges to reduce the
voltage, and meanwhile C2 charges to increase the voltage. When the voltage of capacitor
C1 is lower than that of C2, Q1 is cut off, Q2 is conductive, C1 charges to increase the

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voltage, and meanwhile C2 discharges to reduce the voltage. The above process is
repeated continuously, to guarantee the dynamic equilibrium of voltage between C1 and
C2. The block diagram for capacitor voltage balance control is shown in Figure 6.

Vc 2

Q1
Vc1 -+ PID PWM
Q2
Figure 6. Capacitor Voltage Balance Control Block

4. Performance Analysis
4.1. Voltage Stress
According to Figure 1, VQ1stress= VQ2stress =Vdc. The voltage stress of S0, S1 and S2 is
related to the operating modes. When S0 is conductive, and S1 and S2 are cut off,
Vs1stress=Vdc and Vs2stress=2Vdc. When S1 is conductive, and S0 and S2 are cut off,
Vs0stress=Vdc and Vs2stress=Vdc. When S2 is conductive, and S0 and S1 are cut off,
Vs0stress=2Vdc and Vs1stress=Vdc. Therefore, Vs0stress=Vs1stress=Vs2stress=2Vdc.

4.2. Direct Voltage Use Ratio

The five-level inverter of a single module is carefully compared with diode-clamped
five-level inverter. Under every operating mode, short circuit is used to replace switch
conduction, and open circuit is used to replace cutoff state. It is discovered that they
almost have the same simplified circuit. As for the sole difference, the former realizes
inversion through H-bridge, while the latter realizes inversion by setting a neutral point in
the middle of split capacitors in DC-link. Therefore, the number of capacitors of the
former is half of the number of split capacitors owned by the latter. Let the capacitor
voltage of the two be equal to each other. Then the five-level inverter proposed can be
equivalently replaced by a diode-clamped five-level inverter. When laminated carrier
modulation is adopted, the input-output relation of diode-clamped five-level inverter is
shown in formula (8):
1
V0 = MV'in (10)
2
In the formula, Vo is the peak value of output voltage after LC filter; M means the
modulation ratio; represents the DC input voltage source of the equivalent
diode-clamped multi-level inverter; the number of split capacitors in DC-link is 4; the
terminal voltage is Vc, and .
When carrier modulation is adopted for the five-level inverter proposed, the
input-output relation is shown in formula (9):
1 1
Vo = MV'in = M  4Vc = 2MVc (11)
2 2
In the formula, means the DC voltage source of the five-level inverter proposed,
and . According to formulas (10) and (11), compared with the diode-clamped
five-level inverter, direct voltage use ratio of the five-level inverter proposed is improved
from 0.5M to 2M by 3 times. When the duty ratio and output voltage peak are consistent,
input voltage of the latter is only 0.25 times the voltage of the former. When the input
voltage is the same, the maximum output voltage of the latter is 4 times the voltage of the
former. Therefore, the five-level inverter proposed has effectively improved the direct
voltage use ratio, and expanded the input and output range.

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4.3. Number of Devices

A comparison is made with H-bridge cascaded multi-level inverter, the new-type
cascaded inverters proposed in literature [8] and literature [9] in the number of DC
voltage sources and switch tubes, as shown in Table 3. According to Table 3, the number
of DC voltage sources owned by the cascaded topology proposed is half of that possessed
by the other three topological structures, and the number of switch tubes is almost half of
that possessed by H-bridge cascaded multi-level inverter.

Table 3. Comparison of Number of Switches and DC Voltage Sources

Needed for Different Output Voltage Level
Number of DC voltage sources Number of switch tubes

Quantit Cascade Literatur Literatur Topolog Cascade Literature Literatur Topolog

y of d e e9 y d 8 e9 y
output H-bridge 8 proposed H-bridge proposed
levels
5 2 2 2 1 8 8 7 9
9 4 4 4 2 16 12 9 13
13 6 6 6 3 24 16 11 17
17 8 8 8 4 32 20 13 21
21 10 10 10 5 40 24 15 25
… … … … … … … … …
4N+1 2N 2N 2N N 8N 4N+4 2N+5 4N+5

5. Simulation Analysis
A new-type cascaded 9-level inverter simulation platform is established in
MTALBA/Simulink, and it is obtained through cascading of two basic modules. Let the
input voltage of all modules be equal to each other; the remaining circuit parameters are
determined according to Section 3.2. Table 4 shows the open-loop simulation results
under different input and modulation ratios. Table 5 gives the simulation results of PI
control for voltage effective values. Figure 8 presents the waveform of closed-loop
simulation when the input voltage is 90V.
According to Table 4 and Table 5, the simulation results have a certain deviation from
the theoretical values. The voltage of diode and switch tube will drop under conduction,
so such deviation is deemed as reasonable. Besides, THD is within 1%. Therefore, the
laminated carrier modulation technique mentioned in 3.2 can meet modulation
requirements of the new-type cascaded multi-level inverter. In Figure 7 (b), the output
voltage becomes stabilized after 0.35s, and the modulation time is too long. If load
disturbance or power disturbance happens at the same time, the output waveform effect
will become poorer.

Table 4. Open-Loop Simulation Results of Different Input and Modulation

Ratio
Theoretical Simulated
M THD
/V
50 0.6 120 116.1 0.6%
75 0.65 195 189.4 0.54%
100 0.7 280 275.5 0.65%
110 0.707 311 303.1 0.54%

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Table 5. Closed-Loop Simulation Results of Different Input

Theoretical Simulated
THD
/V
50 120 118.3 0.94%
75 195 192.1 0.84%
100 280 272.3 0.61%
110 311 304.9 0.59%

Figure 7. Closed-Loop Output Voltage Before and After LC Filter when Input
90V

In order to restrain load disturbance or power disturbance, hysteresis control and

capacitor voltage PI control are used to improve the dynamic properties of cascaded
9-level inverter. Figure 8 to Figure 10 show the output voltage and inductor current
waveforms when power source jumps from 120V to 100V under constant load, load
jumps from 11Ωto 20Ωunder constant power source, and power source and load jump at
the same time. The jumping time is t=0.04s. According to Figure 8 – Figure 10, the
new-type cascaded multi-level inverter possesses very good dynamic response after
hysteresis control.

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Figure 8. Output Voltage and Inductor Current when Input Jumps

Figure 9. Output Voltage and Inductor Current when Load Jumps

Figure10. Output Voltage and Inductor Current when Input and Load Jump at
the Same Time

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6. Conclusions
Compared with the diode-clamped inverter, the five-level inverter proposed increases
its direct voltage use ratio by 3 times, and it is easy to realize capacitor voltage balance.
As for the cascaded multi-level inverter based on the five-level inverter proposed, the
number of voltage sources is reduced by half, and the number of switch tubes is also
greatly decreased. Hence, the loss is reduced, and cost is saved. Laminated carrier
modulation and hysteresis control can realize modulation and control for the cascaded
multi-level inverter proposed well.

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Authors
Zhi Xu, Male, postgraduate, research direction is power quality
and flexible transmission.

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