Presentation created by:

Assoc. Prof. Aneliya Manukova,

Department of Electronics
University of Ruse „Angel Kanchev”
The field-effect transistor (FET) is a three-terminal device used for a
variety of applications that match, to a large extent. Although there
are important differences between the two types of devices, there are
also many similarities.

Two types of FETs are there: the junction field-effect transistor (JFET)
and the metal-oxide-semiconductor field-effect transistor (MOSFET).

The MOSFET category is further broken down into depletion and

enhancement types. The MOSFET transistor has become one of the
most important devices used in the design and construction of
integrated circuits for digital computers. Its thermal stability and other
general characteristics make it extremely popular in computer circuit
design.
Similarities:
Amplifiers

Switching devices

Impedance matching circuits

Differences:
FETs are voltage-controlled devices. BJTs are current
controlled devices.
FETs have a higher input impedance. BJTs have
higher gains.
FETs are less sensitive to temperature variations and
are more easily integrated on ICs.

FET Types
JFET: Junction field-effect transistor
MOSFET: Metal–Oxide–Semiconductor FET
D-MOSFET: Depletion MOSFET
E-MOSFET: Enhancement MOSFET
There are two types of JFETs
•n-channel
•p-channel
The n-channel is more widely used.

There are three terminals:

•Drain (D) and Source (S) are connected to the n-channel
•Gate (G) is connected to the p-type material
VGS = 0 V , VDS some positive value
When VGS = 0 and VDS is increased from 0 to a more positive voltage:

• The depletion region between p-gate and n-channel increases.

• Increasing the depletion region, decreases the size of the n-
channel which increases the resistance of the n-channel.
• Even though the n-channel resistance is increasing, the current
(ID) from source to drain through the n-channel is increasing. This is

because VDS is increasing. Pinch Off

If VGS = 0 and VDS is further increased to a more positive voltage, then the

depletion zone gets so large that it pinches off the n-channel. As VDS is

increased beyond |VP|, the level of ID remains the same (ID=IDSS).

IDSS is the maximum drain current for a JFET and is
defined by the conditions VGS=0 and VDS > |VP|.
 VGS<0

• As VGS becomes more negative, the depletion

region increases.
• The more negative VGS, the resulting level for ID is
reduced.
• Eventually, when VGS = VP (-ve) [VP= VGS(off)], ID is
0 mA. (the device is “turned off”.

The level of VGS that results in ID=0 mA is

defined by VGS= VP, with VP being a negative
voltage for n-channel devices and a positive
voltage for p-channel JFETs.
 Voltage-Controlled Resistor

• The region to the left of the pinch-off point is

called the ohmic region.
•The JFET can be used as a variable resistor,
where VGS controls the drain-source resistance n-Channel JFET characteristics
with IDSS = 8 mA and VP = -4 V.
(rd). As VGS becomes more negative, the
resistance (rd) increases.

– ro is the resistance with VGS =0 and

– rd is the resistance at a particular level of VGS
 The p-channel JFET behaves the same as the n-
channel JFET, except the voltage polarities and
current directions are reversed.

As VGS increases more positively

•The depletion zone increases
•ID decreases (ID < IDSS)
•Eventually ID = 0 A

Also note that at high levels of VDS the JFET

reaches a breakdown situation: ID increases
uncontrollably if VDS > VDSmax
(a) VGS = 0 V, ID = IDSS;
(b) cutoff (ID = 0 A) VGS less than (more negative
than) the pinch-off level;
(c) ID is between 0 A and IDSS for VGS ≤ 0 V and
greater than the pinch-off level.
Shockley’s equation
Substituting VGS = 0 V in equation 1.3 gives, Shorthand Method
  ID = IDSS|VGS = 0v ID = IDSS|VGS = VP/2
Substituting VGS = VP yields,
ID = 0V| VGS = VP VGS = 0.3VP|ID = IDSS/2
For the drain characteristics of Last Figure, if we VGS versus I D
substitute VGS = -1V, ID = 4.5mA. Note the care
Using Shockley’s Equation
taken with the negative signs for VGS and VP in the VGS ID
calculations above. The loss of one sign would 0 I DSS
result in a totally erroneous result.
It should be obvious from the above that given IDSS 0.3 VP I DSS /2
and VP (as is normally provided on specification 0.5 VP I DSS /4
sheets) the level of ID can be found for any level of VP 0 mA
VGS. Conversely, an equation for the resulting
level of VGS for a given level of ID.
 ID 
VGS  VP .  1  
 I DSS 
A clear understanding of the impact of each of the equations above is sufficient background to
approach the most complex of dc configurations. Recall that VBE = 0.7 V was often the key to
initiating an analysis of a BJT configuration. Similarly, the condition IG = 0 A is often the starting
point for the analysis of a JFET configuration.
For the BJT configuration, IB is normally the first parameter to be determined. For the JFET, it
is normally VGS.
Using IDSS and Vp (VGS(off)) values found in a specification
sheet, the transfer curve can be plotted according to these
three steps:

Conversely , for a given ID, VGS can be obtained

Sketch the transfer curve defined by
IDSS=12 mA and VP=-6V.
Determine VGS when Solution
a)ID= 0 mA
b)ID= 12 mA
c)ID= 3 mA

a) IDSS= 0 mA VGS = -6
b) IDSS= 12 mA VGS = 0 V
c) IDSS= 3 mA VGS = 3 mA
MOSFETs have characteristics similar to JFETs and
additional characteristics that make them very useful.

There are two types of MOSFETs:

• Depletion-Type;
• Enhancement-Type

enhancement-type MOSFETs
 The Drain (D) and Source (S) connect to the to n-doped regions.
 These n-doped regions are connected via an n-channel.
 This n-channel is connected to the Gate (G) via a thin insulating layer of SiO2.
 The n-doped material lies on a p-doped substrate that may have an additional
terminal connection called Substrate (SS or B).
A depletion-type MOSFET can operate
in two modes:

 When VGS is reduced to VP (Pinch-off ) [i.e. Vp=-6V],

then ID=0 mA.
 For positive values of VGS, the positive gate will draw
additional electrons (free carriers) from the p-type
substrate and hence ID increases.

Note that VGS is now

a positive polarity
 For VGS=0, ID=0 (no channel).
 For VDS some positive voltage, and 0=VGS, two reverse biased p-n junctions and no
significant flow between drain and source.
 For VGS>0 and VGS>0, the positive voltage at gate pressure holes to enter deeper
regions of the p-substrate, and the electrons in p-substrate will be attracted to the
positive gate.
 The level of VGS that results in the significant increase in drain current is called
threshold voltage (VT).
 For VGS< VT, ID=0 mA.
The enhancement-type MOSFET operates only in the
enhancement mode.
VGS is always positive.

•As VGS increases, ID increases

•As VGS is kept constant and VDS is increased, then ID

saturates (IDSS) and the saturation level, VDS sat is reached

VDS sat can be calculated by:

To determine ID given VGS

Where k, a constant, can be

determined by using values at a
specific point and the formula:

VT is threshold voltage or voltage at which the MOSFET turns on

Substituting ID(on) =10 mA when VGS(on)=8V from the characteristics.

Solution
The p-channel enhancement-type MOSFET is similar to the n-channel,
except that the voltage polarities and current directions are reversed
 Transconductance
Transconductance (for transfer conductance), also infrequently called mutual conductance, is the
electrical characteristic relating the current through the output of a device to the voltage across the input of
a device
Amplifiers and current sources operate in the “saturation” region of a FET (don’t confuse with the
saturation region of a BJT, which is where you don’t want to operate a BJT amplifier).

The FET transconductance improves only as the square root of current, while the BJT goes linear with
current. In general, the BJT will make a higher gain amplifier (voltage or current amp), but
JFET Amplifiers
• Typically, the place you want to use a JFET amplifier is where you need very high input impedance, for
example because your signal source has a very high impedance (cannot deliver much current).
– Probably best used in differential amps or source-followers, not common-source amps.
• Another example is where the base current of a bipolar transistor will cause a significant error.
– The LF411 Op-amp that you will soon use in several circuits uses JFETs at its inputs. This is very nice, because
the current flowing into the inputs is negligible in all cases.
• Otherwise, bipolar transistors will usually give much better performance in terms of gain, predictability, etc.
• You need to keep in mind:
– The gate-source junction must be reverse biased at all times (or at worst, zero volts).
– The gate does need some bias current, although it can be very small.
– The drain-to-source voltage cannot be too small, especially if the drain current is substantial. For a bipolar
transistor the collector emitter voltage can be a fraction of a volt, but for a JFET count on a
few volts.
– Unlike the case of a bipolar transistor, there is no simple formula for the transconductance. You must consult the
data sheet, and it will be small compared with the bipolar transistor transconductance.
• Or equivalently, the effective dynamic resistance of the source will be a few hundred ohms, not the bipolar
transistor value of 25 divided by the current in mA.
 VGO  VSO

VGO  VSO  VGSO

VGSO
RS 
I DO


2
VGS   ID  R S  120...240
ID  I DSS  1    VGS  VP .  1  
 VP   I DSS 

I D 2.I DSS  VGSO  2.I DSS I DO For larger S t 

S  gm  1  
U GS UP  VP  VP I DSS R S increases 
R1  R 2
Analysis at medium frequencies

Gain

vo V
Av 
vi

 o  g m . R o R D R L
Vi
 gm  S R D R o

Usually R o  R D R L  R o 
R D R L  R D R L  R DL и A v   g m .R DL

g m .R DL
AU 
1  g m .R S
 Input impedance
R 2  1...2M for low frequencies
Vi
R iA   Ri R2 R 2  100...120k for high frequencies
Ii
VGS
Ri 
I GSS
 Analysis at medium frequencies 1
f 
2
M dB  M dB
 M dB
 M dB
li lo lS
f l  max  f li , f lo , f lS 
M,dB
M dB
Mj  и M  10 20
3

Input circuit Output circuit Source circuit

C1 C2
T
Rs Roa
Ria RL
Es Rs Cs
Eoa

l i  C1.(R Sig  R iA ) l o  C 2 .(R oA  R L ) l S  CS .R S

1 1 gm
C1  C2  CS 
R Sig  R iA  . 2f l . M l2i  1  R oA  R L  . 2f l . M l2b  1 2fl . 2
M lS 1
 Models at high frequencies
JFET
Cgd
G gm.Ugs D
Ro
Cgs

MOSFET
When MOSFET capacity can not be distinguished
Cgd externally to amend.
G gm.Ugs D CiSS  C gs  C gd
R1 C rSS  C gd
Cgs Cds
CoSS  Cds  C gd

S
 Input-output capacities at high frequencies travel with transition JFET

Schematic representation of the three diagrams

Common Source Common Gate Common Drain

Cgd Cgs

T
T
T
Cgs Cgd
Cgs Cgd

Cid  C gs  Cgd . 1  A v  Cid  C gs Cid  Cgd  Cgd . 1- A v 

 1   1 
Cod  C gd .  1   Cod  C gd Cod  C gs .  1  
 Av   A v 
Analysis at medium frequencies

Gain

Vo R D R o
AV 
Vi

 gm . R o R D R L  gm  S

Usually R o  R D R L  R o 
R D R L  R D R L  R DL и A U  g m .R DL

 Input impedance
Vi 1
R iA  
Ii gm

 Current gain
io I
AI   o 1
ii Ii
Analysis at medium frequencies

Gain

Vo S.R SL
AU   R SL  R S R L
Vi 1  S.R SL

 Input impedance
Vi R 2  1...2M for low frequencies
R iA   Ri R2
Ii R 2  100...120k for high frequencies
VGS
Ri 
I GSS
  Longer input impedance

From Miler effect:

YiA  Y2 . 1  A 

R2
R iA 
1 A

Example № 5 : А=0,7; R2=1M 

1.106
R iA   3, 3M
1  0, 7
Important relationships
and characteristics