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EC6205

Uploaded by

detej79667
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA

Name of the Examination: B.Tech. 7th/M.Tech.-M.Tech.(R)-Ph.D. 1st End-Semester (Autumn) 2023


Subject Code: EC6205 Subject Name: Integrated Circuit for Digital Signal Processing
No. of pages: 1 Maximum marks: 50 Duration: 3 Hours
ANSWER ALL QUESTIONS
ALL PARTS OF A QUESTION MUST BE ANSWERED IN SINGLE CONTIGUOUS SPACE

Q.
No. Questions Marks

1. a) Draw the design flow-graph for an 8-point FFT hardware architecture and explain 5
its working principle. +
b) What do you mean by retiming? What is its importance in VLSI implementation 5
of DSP processors? How is retiming different from the concept of pipelining?
Explain with an example.
2 What do you mean by a Parallel Prefix Adder? Design the structure of a generalized 1 + 3
Parallel Prefix Adder. Draw and explain the structure of Kogge-stone adder. In + 3 + 1
which respect it is superior and inferior to a Conditional Sum Adder?
3 a) What is un-folding technique? Draw the 3-unfolded version (J=3) of the 5
following DSP structure (D represents a delay element). What can be the maximum
unfolding possible for the given graph?
D
S1 S2
+
5D 6D
S3

b) Design a circuit to calculate average of eight 4-bit numbers (assume the numbers 3
are provided through a serial communication bus).
4 Derive expressions for hyperbolic CORDIC and design its architecture. How this 6+2
structure can be modified into pipelined CORDIC to increase its throughput?

5 a) Draw an optimized hardware for the following IIR filter like architecture with 5
the given expression (m denotes the last digit of your roll number)
𝑚𝑚+1 10−𝑚𝑚

y(𝑛𝑛) = � 𝑎𝑎𝑘𝑘 y(𝑛𝑛 − 𝑘𝑘) + � 𝑏𝑏𝑘𝑘 x(𝑛𝑛 − 𝑘𝑘)


+
𝑘𝑘=0 𝑘𝑘=0

b) Discuss various properties and relations between the two circuits below.
3

6 Design Baugh-Wooley’s and Braun’s Multiplier structures for multiplying 3-bit data
6+2
with 5-bit data. Clearly discuss their differences and uses in DSP architectures.

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