C

on ac
W
fid in
en g o
h

tia nly
lf
or

OV9623

datasheet
PRELIMINARY SPECIFICATION
1/2.7" color CMOS WXGA (1280 x 800) high dynamic range (HDR)
high definition (HD) image sensor

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

00Copyright ©2019 OmniVision Technologies, Inc. All rights reserved.

This document is provided “as is” with no warranties whatsoever, including any warranty of merchantability,
non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification,
or sample.

OmniVision Technologies, Inc. and all its affiliates disclaim all liability, including liability for infringement of any proprietary
rights, relating to the use of information in this document. No license, expressed or implied, by estoppel or otherwise, to
any intellectual property rights is granted herein.

The information contained in this document is considered proprietary to OmniVision Technologies, Inc. and all its
affiliates. This information may be distributed to individuals or organizations authorized by OmniVision Technologies, Inc.
to receive said information. Individuals and/or organizations are not allowed to re-distribute said information.
C
on ac

Trademark Information

OmniVision and the OmniVision logo are registered trademarks of OmniVision Technologies, Inc. OmniPixel3-HS is a
trademark of OmniVision Technologies, Inc.
W
fid in

All other trademarks used herein are the property of their respective owners.
en g o
h

tia nly
lf
or

color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

datasheet (CSP)
PRELIMINARY SPECIFICATION

version 1.23
december 2019

To learn more about OmniVision Technologies, visit www.ovt.com.

Powered by TCPDF (www.tcpdf.org)

 i

00applications ordering information

security and surveillance cameras OV09623-N29A (color, lead-free)
129-pin CSP packed in tray

00features
C

support for image sizes: WXGA (1280x800), auto white balance control
HD 720p (1280x720), WVGA (752x480),
aperture/gamma correction
VGA (640x480), 600x400, CIF (352x288),
on ac

QVGA (320x240) serial camera control bus (SCCB) for register

support for output formats: YUV and separated and
programming note To reduce
combined RAW low power consumption image artifacts from
Infrared light, and
W
fid in

parallel DVP interface external frame sync capability provide the best image
high sensitivity 50/60 Hz flicker cancellation quality, OmniVision
recommends an IR cut
automatic exposure/gain defective pixel correction filter
en g o

horizontal and vertical windowing capability

h

tia nly

00key specifications (typical)

active array size: 1280 x 800 output formats: up to 18-bit combined raw,
lf

separated 10-bit raw, 8-/10-bit YUV422

power supply:
analog: 3.14~3.47V lens chief ray angle: 9° (see figure 10-2)
note OmniVision
or

core: 1.425~1.575V input clock frequency: 6 ~ 27 MHz

I/O: 1.7~3.47V recommends CSP
scan mode: progressive packages use underfill
power requirements: shutter: rolling shutter as part of camera
active: 507 mW typical @ 3.3V AVDD, 1.5V assembly process.
DVDD, and 1.8V DOVDD maximum exposure interval: 838 tROW
standby: 440 µW typical @ 3.3V AVDD, 1.5V maximum image transfer rate: 30 fps full resolution
DVDD, and 1.8V DOVDD
sensitivity: 3650 mV/Lux-sec
temperature range: (see table 8-2)
operating: -30°C to +85°C junction temperature
max S/N ratio: 39 dB note Register
dynamic range: 115 dB initialization sequence
stable image: 0°C to +50°C junction temperature settings must be
pixel size: 4.2 µm x 4.2 µm provided by OmniVision
output interfaces: 10-bit parallel DVP
image area: 5510.4 μm x 3418.8 μm (see section 7).
lens size: 1/2.7"
package dimensions:7795 μm x 7145 μm

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

C
on ac
W
fid in
en g o
h

tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 iii

00table of contents

1 signal descriptions 1-1

2 system level description 2-1
2.1 overview 2-1
2.2 architecture 2-1
2.3 format and frame rate 2-4
2.4 I/O control 2-4
2.5 system clock control 2-6
2.6 serial camera control bus (SCCB) interface 2-7
C

2.6.1 data transfer protocol 2-7

2.6.2 message format 2-7
on ac

2.6.3 read / write operation 2-7

2.6.4 SCCB timing 2-10
W
fid in

2.7 standby 2-11

2.8 power on timing 2-11
2.9 system control 2-12
en g o

3 pixel array structure 3-1

4 image sensor core digital functions 4-1
h

4.1 mirror and flip 4-1

tia nly

4.2 test pattern 4-2

4.2.1 color bar 4-2
lf

4.2.2 square 4-3

4.2.3 random data 4-3
or

4.2.4 transparent effect 4-3

4.2.5 rolling bar effect 4-3
4.3 image cropping and windowing 4-5
4.4 AEC/AGC algorithms 4-7
4.4.1 position weight 4-7
4.4.2 exposure/gain control 4-14
4.5 black level calibration (BLC) 4-33
4.5.1 coarse and fine BLC 4-33
4.5.2 trigger methods 4-33

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

5 image sensor processor digital functions 5-1

5.1 DSP top level control 5-1
5.2 LENC 5-3
5.3 auto white balance (AWB) 5-7
5.3.1 simple AWB 5-8
5.3.2 CT AWB 5-8
5.3.3 AWB control 5-14
5.3.4 AWB stable range and gain range 5-15
5.4 de-noise (DNS) 5-16
5.5 color interpolation (CIP) 5-20
5.6 color matrix (CMX) 5-26
C

5.7 auto color saturation 5-32

on ac

5.8 combine 5-34

5.9 normalize 5-39
5.10 tone_mapping 5-40
W
fid in

5.11 windowing cropping and subsampling 5-44

5.12 defect pixel correction (DPC) 5-45
5.13 group control 5-45
en g o

6 image sensor output interface digital functions 6-1

h

6.1 embedded line 6-1

tia nly

6.2 DVP timing 6-2

6.2.1 DVP setup/hold time 6-5
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 v

7 register tables 7-1

7.1 system control [0x0100, 0x0103, 0x3000 ~ 0x3049] 7-1
7.2 analog control [0x3600 ~ 0x3603, 0x3610 ~ 0x3618, 0x3620 ~ 0x3636] 7-6
7.3 sensor control [0x3700 ~ 0x3710, 0x3712 ~ 0x374F] 7-7
7.4 timing control [0x3800 ~ 0x382B, 0x3832 ~ 0x3835, 0x3844, 0x3848 ~ 0x3849] 7-8
7.5 OTP control [0x3D00 ~ 0x3D11, 0x3D1F, 0x3D30 ~ 0x3D5F] 7-11
7.6 BLC function [0x4000 ~ 0x405B, 0xC4B7 ~ 0xC50F, 0x5B1C ~ 0x5D30] 7-14
7.7 AEC [0x3503, 0x3504, 0x5600 ~ 0x56EB, 0xC2ED ~ 0xC51B, 0x5A00 ~ 0x5C17] 7-25
7.8 ISP control [0x5000 ~ 0x500E, 0x503B ~ 0x503E, 0x5040 ~ 0x5044] 7-50
7.9 LENC control [0x5080 ~ 0x5098, 0x509C ~ 0x50B8] 7-53
7.10 AWB [0x5100 ~ 0x5718, 0xC4B8 ~ 0xC4DF, 0x5AB0 ~ 0x5D1B] 7-56
C

7.11 DNS control [0x5210 ~ 0x522F, 0x5238 ~ 0x5256] 7-70

on ac

7.12 CIP control [0x5280 ~ 0x52A1, 0x52C0 ~ 0x52E1] 7-73

7.13 CMX control [0xC318 ~ 0xC347] 7-79
7.14 low level filter (LLF) control [0x5380 ~ 0x538A] 7-85
W
fid in

7.15 combine [0x5400 ~ 0x542D, 0xC30C ~ 0xC4CB, 0x5A08 ~ 0x5A97, 0x5C18 ~ 0x5C6F] 7-86
7.16 normalize (NMLZ) control [0x5480 ~ 0x5A98, 0x5C71 ~ 0x5C78] 7-95
en g o

7.17 tone mapping (TMAP) [0x5500 ~ 0x5511, 0xC4E4 ~ 0xC4F9, 0x5A9C ~ 0x5CFB] 7-96
7.18 frame counter (FC) control [0x4200 ~ 0x4203] 7-105
h

7.19 format control [0x4300, 0x4302 ~ 0x4309] 7-106

tia nly

7.20 VFIFO control [0x4600 ~ 0x4603, 0x4605 ~ 0x4613, 0x4620 ~ 0x4639] 7-107
7.21 digital video port (DVP) control [0x4700 ~ 0x470D] 7-109
lf

7.22 embedded line control [0x6800 ~ 0x6807] 7-112

7.23 group writer [0x6F00, 0x6F04 ~ 0x6F1F] 7-113
or

7.24 macro-code [0xD000 ~ 0xDFFF] 7-114

8 operating specifications 8-1
8.1 absolute maximum ratings 8-1
8.2 functional temperature 8-1
8.3 DC characteristics 8-2
8.4 AC characteristics 8-3
9 mechanical specifications 9-1
9.1 physical specifications 9-1
9.2 IR reflow specifications 9-3

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

10 optical specifications 10-1

10.1 sensor array center 10-1
10.2 lens chief ray angle (CRA) 10-2
10.3 spectrum response curve 10-4
C
on ac
W
fid in
en g o
h

tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 vii

00list of figures

figure 1-1 pin diagram 1-1

figure 2-1 OV9623 block diagram 2-2
figure 2-2 OV9623 reference schematic 2-3
figure 2-3 PLL control diagram 2-6
figure 2-4 message type 2-7
figure 2-5 SCCB single read from random location 2-8
figure 2-6 SCCB single read from current location 2-8
figure 2-7 SCCB sequential read from random location 2-8
C

figure 2-8 SCCB sequential read from current location 2-9

figure 2-9 SCCB single write to random location 2-9
on ac

figure 2-10 SCCB sequential write to random location 2-9

figure 2-11 SCCB interface timing 2-10
W
fid in

figure 2-12 power on timing diagram 2-11

figure 3-1 sensor array region color filter layout 3-1
figure 4-1 mirror and flip samples 4-1
en g o

figure 4-2 color bar types 4-2

h

figure 4-3 color, black and white square bars 4-3

tia nly

figure 4-4 transparent effect 4-3

figure 4-5 rolling bar effect 4-3
figure 4-6 frame structure diagram 4-5
lf

figure 4-7 position window diagram 4-8

figure 4-8 position weight diagram 4-12
or

figure 4-9 AEC/AGC target/range diagram 4-15

figure 5-1 LENC coefficient versus sensor gain 5-3
figure 5-2 RAW domain DNS - long 5-16
figure 5-3 RAW domain DNS - short 5-17
figure 5-4 CIP sharpen curve 5-20
figure 5-5 auto color saturation graph 5-32
figure 6-1 DVP timing diagram 6-2
figure 6-2 DVP setup/hold time diagram 6-5
figure 9-1 package specifications 9-1
figure 9-2 IR reflow ramp rate requirements 9-3

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

figure 10-1 sensor array center 10-1

figure 10-2 chief ray angle (CRA) 10-2
figure 10-3 spectrum response curve diagram 10-4

C
on ac
W
fid in
en g o
h

tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 ix

00list of tables

table 1-1 signal descriptions 1-1

table 1-2 configuration under various conditions 1-6
table 2-1 DVP supported formats and frame rates 2-4
table 2-2 driving capability and direction control for I/O pads 2-4
table 2-3 SCCB interface timing specifications 2-10
table 2-4 power on timing 2-11
table 2-5 system control registers 2-12
table 4-1 mirror and flip function control 4-1
C

table 4-2 test pattern registers 4-4

table 4-3 format related registers 4-6
on ac

table 4-4 position window control registers 4-8

table 4-5 AEC position weight registers 4-13
W
fid in

table 4-6 AEC target/range control registers 4-15

table 4-7 BLC control functions 4-33
table 5-1 DSP top registers 5-1
en g o

table 5-2 LENC control registers 5-4

h

table 5-3 AWB registers 5-7

tia nly

table 5-4 AWB long calibration registers 5-9

table 5-5 AWB short calibration registers 5-11
table 5-6 AWB control registers 5-14
lf

table 5-7 AWB range registers 5-15

table 5-8 DNS control registers 5-17
or

table 5-9 CIP control registers 5-20

table 5-10 CMX control registers 5-26
table 5-11 auto color saturation control registers 5-32
table 5-12 combine control registers 5-34
table 5-13 normalize control registers 5-39
table 5-14 tone_mapping registers 5-40
table 5-15 WINC control registers 5-44
table 5-16 group control registers 5-45
table 6-1 embedded line control 6-1
table 6-2 DVP timing specifications 6-2

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 6-3 DVP setup/hold time 6-5

table 7-1 system control registers 7-1
table 7-2 analog control registers 7-6
table 7-3 sensor control registers 7-7
table 7-4 timing control registers 7-8
table 7-5 OTP control registers 7-11
table 7-6 BLC function registers 7-14
table 7-7 AEC control registers 7-25
table 7-8 ISP control registers 7-50
table 7-9 LENC control registers 7-53
table 7-10 AWB control registers 7-56
C

table 7-11 DNS control registers 7-70

on ac

table 7-12 CIP control registers 7-73

table 7-13 CMX control registers 7-79
table 7-14 LLF control registers 7-85
W
fid in

table 7-15 combine control registers 7-86

table 7-16 NMLZ control registers 7-95
en g o

table 7-17 TMAP control registers 7-96

table 7-18 FC control registers 7-105
h

table 7-19 format control registers 7-106

tia nly

table 7-20 VFIFO control registers 7-107

table 7-21 DVP control registers 7-109
lf

table 7-22 embedded line control (EMB) registers 7-112

table 7-23 group writer registers 7-113
or

table 7-24 macro-code registers 7-114

table 8-1 absolute maximum ratings 8-1
table 8-2 functional temperature 8-1
table 8-3 DC characteristics (-30°C < TJ < +85°C) 8-2
table 8-4 AC characteristics (TA = 25°C, VDD-A = 3.3V, VDD-IO = 1.8V) 8-3
table 8-5 timing characteristics 8-3
table 9-1 package dimensions 9-1
table 9-2 reflow conditions 9-3
table 10-1 CRA versus image height plot 10-2

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 1-1

1 signal descriptions
table 1-1 lists the signal descriptions and their corresponding pin numbers for the OV9623 image sensor. The package
information is shown in section 9.

figure 1-1 pin diagram

A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13

AVDD AGND SVDD DOGND DOGND SVDD SGND DOVDD DOGND DEVDD SVDD VF4

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14

AVDD AGND AVDD SGND DOGND DOGND DOGND DOGND DOGND DOGND DOGND SGND AGND AVDD
C

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14

AGND AVDD AGND DOGND DOGND DOGND DOGND DOGND DOGND DOGND DOGND VF VH AGND
on ac

D1 D2 D3 D4 D12 D13 D14

DOGND DOGND DOGND DOGND DOGND DOGND AVDD

E1 E2 E3 E4 E12 E13 E14

DOGND DOGND DOGND DOGND DOGND EVDD PVDD
W
fid in

F1 F2 F3 F4 F12 F13 F14

TM DOGND DOGND DOGND DOGND XVCLK EGND

G1 G2 G3 G4 OV9623 G12 G13 G14

en g o

AGND PWDN DOGND DOGND DOGND DGND DOVDD

H1 H2 H3 H4 H12 H13 H14

AVDD DOGND DOGND DOGND DOGND DOGND DVDD
h

tia nly

J1 J2 J3 J4 J12 J13 J14

TMB RESETB DOGND DOGND DOGND GPIO2/ GPIO3
SID2
K1 K2 K3 K4 K12 K13 K14
DVDD DGND FSIN DOGND DOGND DVDD DGND
lf

L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14

DOVDD SIOC DGND DOGND DOGND DOGND DOGND DOGND DOGND DOGND DOGND GPIO0/ DOGND DOVDD
SID0
or

M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14

SIOD DOGND D9 D7 D6 D4 DGND D3 D1 DOVDD PCLK VSYNC DGND GPIO1/
SID1
N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13
DVDD D8 DOGND DOVDD D5 DVDD DOVDD D2 D0 DOGND HREF DVDD

top view

table 1-1 signal descriptions (sheet 1 of 6)

pin pin
number signal name type description
A2 AVDD power 3.3V power

A3 AGND ground analog ground

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 1-1 signal descriptions (sheet 2 of 6)

pin pin
number signal name type description
A4 SVDD power 3.3V power

A5 DOGND ground I/O ground

A6 DOGND ground I/O ground

A7 SVDD power 3.3V power

A8 SGND ground sensor array ground

A9 DOVDD power 1.7 ~ 3.6V power

A10 DOGND ground I/O ground

C

A11 DEVDD power analog power

on ac

A12 SVDD power 3.3V power

A13 VF4a reference internal analog reference

B1 AVDD power 3.3V power

W
fid in

B2 AGND ground analog ground

B3 AVDD power 3.3V power

en g o

B4 SGND ground sensor array ground

B5 DOGND ground I/O ground

h

B6 DOGND ground I/O ground

tia nly

B7 DOGND ground I/O ground

B8 DOGND ground I/O ground

lf

B9 DOGND ground I/O ground

B10 DOGND ground I/O ground

or

B11 DOGND ground I/O ground

B12 SGND ground sensor array ground

B13 AGND ground analog ground

B14 AVDD power 3.3V power

C1 AGND ground analog ground

C2 AVDD power 3.3V power

C3 AGND ground analog ground

C4 DOGND ground I/O ground

C5 DOGND ground I/O ground

C6 DOGND ground I/O ground

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 1-3

table 1-1 signal descriptions (sheet 3 of 6)

pin pin
number signal name type description
C7 DOGND ground I/O ground

C8 DOGND ground I/O ground

C9 DOGND ground I/O ground

C10 DOGND ground I/O ground

C11 DOGND ground I/O ground

C12 VFa reference internal analog reference

a
C13 VH reference internal analog reference
C

C14 AGND ground analog ground

on ac

D1 DOGND ground I/O ground

D2 DOGND ground I/O ground

D3 DOGND ground I/O ground

W
fid in

D4 DOGND ground I/O ground

D12 DOGND ground I/O ground

en g o

D13 DOGND ground I/O ground

D14 AVDD power 3.3V power

h

E1 DOGND ground I/O ground

tia nly

E2 DOGND ground I/O ground

E3 DOGND ground I/O ground

lf

E4 DOGND ground I/O ground

E12 DOGND ground I/O ground

or

E13 EVDD power PLL digital power (connect to DVDD)

E14 PVDD power PLL analog power

F1 TM input test mode, active high

F2 DOGND ground I/O ground

F3 DOGND ground I/O ground

F4 DOGND ground I/O ground

F12 DOGND ground I/O ground

F13 XVCLK input system clock input

F14 EGND ground PLL ground

G1 AGND ground analog ground

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 1-1 signal descriptions (sheet 4 of 6)

pin pin
number signal name type description
G2 PWDN input input (active high with pull down resistor)

G3 DOGND ground I/O ground

G4 DOGND ground I/O ground

G12 DOGND ground I/O ground

G13 DGND ground ground for digital circuit

G14 DOVDD power 1.7 ~ 3.6V power

H1 AVDD power 3.3V power

C

H2 DOGND ground I/O ground

on ac

H3 DOGND ground I/O ground

H4 DOGND ground I/O ground

H12 DOGND ground I/O ground

W
fid in

H13 DOGND ground I/O ground

H14 DVDD power 1.5V power

en g o

J1 TMB input test mode (active low)

J2 RESETB input reset input (active low with internal pull up resistor)
h

J3 DOGND ground I/O ground

tia nly

J4 DOGND ground I/O ground

J12 DOGND ground I/O ground

lf

J13 GPIO2/SID2 I/O general purpose IO2 / SCCB address select 2

J14 GPIO3 I/O general purpose IO3

or

K1 DVDD power 1.5V power

K2 DGND ground ground for digital circuit

K3 FSIN I/O frame sync input

K4 DOGND ground I/O ground

K12 DOGND ground I/O ground

K13 DVDD power 1.5V power

K14 DGND ground ground for digital circuit

L1 DOVDD power 1.7 ~ 3.6V power

L2 SIOC input SCCB interface input clock

L3 DGND ground ground for digital circuit

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 1-5

table 1-1 signal descriptions (sheet 5 of 6)

pin pin
number signal name type description
L4 DOGND ground I/O ground

L5 DOGND ground I/O ground

L6 DOGND ground I/O ground

L7 DOGND ground I/O ground

L8 DOGND ground I/O ground

L9 DOGND ground I/O ground

L10 DOGND ground I/O ground

C

L11 DOGND ground I/O ground

on ac

L12 GPIO0/SID0 I/O general purpose IO0/ SCCB address select 0

L13 DOGND ground I/O ground

L14 DOVDD power 1.7 ~ 3.6V power

W
fid in

M1 SIOD I/O SCCB interface data

M2 DOGND ground I/O ground

en g o

M3 D9 I/O video data output[9]

M4 D7 I/O video data output[7]

h

M5 D6 I/O video data output[6]

tia nly

M6 D4 I/O video data output[4]

M7 DGND ground ground for digital circuit

lf

M8 D3 I/O video data output[3]

M9 D1 I/O video data output[1]

or

M10 DOVDD power 1.7 ~ 3.6V power

M11 PCLK I/O video output clock

M12 VSYNC I/O vertical signal video output

M13 DGND ground ground for digital circuit

M14 GPIO1/SID1 I/O general purpose IO1/ SCCB address select 1

N2 DVDD power 1.5V power

N3 D8 I/O video data output[8]

N4 DOGND ground I/O ground

N5 DOVDD power 1.7 ~ 3.6V power

N6 D5 I/O video data output[5]

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 1-1 signal descriptions (sheet 6 of 6)

pin pin
number signal name type description
N7 DVDD power 1.5V power

N8 DOVDD power 1.7 ~ 3.6V power

N9 D2 I/O video data output[2]

N10 D0 I/O video data output[0]

N11 DOGND ground I/O ground

N12 HREF I/O video output horizontal signal

N13 DVDD power 1.5V power

C

a. internal reference voltages require a 0.1µF capacitor to AGND

on ac

table 1-2 configuration under various conditions (sheet 1 of 2)

W
fid in

pin RESETB = 1 RESETB = 1

number signal name RESETB = 0 PWDN = 0 PWDN = 1
en g o

F1 TM input input input

F13 XVCLK input input input

h

tia nly

G2 PWDN input input input

J1 TMB input input input

J2 RESETB input input input

lf

J13 GPIO2/SID2 input input (configurable) input (configurable)

J14 GPIO3 input input (configurable) input (configurable)

or

K3 FSIN input input high-z

L2 SIOC input input high-z

L12 GPIO0/SID0 input input (configurable) input (configurable)

M1 SIOD open-drain open-drain open-drain

M3 D9 output output (configurable) output (configurable)

M4 D7 output output (configurable) output (configurable)

M5 D6 output output (configurable) output (configurable)

M6 D4 output output (configurable) output (configurable)

M8 D3 output output (configurable) output (configurable)

M9 D1 output output (configurable) output (configurable)

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 1-7

table 1-2 configuration under various conditions (sheet 2 of 2)

pin RESETB = 1 RESETB = 1

number signal name RESETB = 0 PWDN = 0 PWDN = 1
M11 PCLK output output (configurable) output (configurable)

M12 VSYNC output output (configurable) output (configurable)

M14 GPIO1/SID1 input input (configurable) input (configurable)

N3 D8 output output (configurable) output (configurable)

N6 D5 output output (configurable) output (configurable)

N9 D2 output output (configurable) output (configurable)

N10 D0 output output (configurable) output (configurable)

C

N12 HREF output output (configurable) output (configurable)

on ac
W
fid in
en g o
h

tia nly
lf
or

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

C
on ac
W
fid in
en g o
h

tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 2-1

2 system level description

2.1 overview

The OV9623 color image sensors are low voltage, high performance, 1/2.7-inch, CMOS image sensors that provide the
full functionality of a single chip 1 megapixel (1280x800) camera using OmniPixel3-HS™ technology in a small footprint
package. They provide full-frame, sub-sampled and windowed images in various formats via the control of the Serial
Camera Control Bus (SCCB) interface.

The OV9623 has an image array capable of operating at up to 30 frames per second (fps) in full resolution with complete
user control over image quality, formatting and output data transfer. All required image processing functions, including
exposure control, white balance, defective pixel canceling, etc., are programmable through the SCCB interface. In
addition, OmniVision image sensors use proprietary sensor technology to improve image quality by reducing or
C

eliminating common lighting/electrical sources of image contamination, such as fixed pattern noise, smearing, etc., to
produce a clean, fully stable image.
on ac

2.2 architecture
W
fid in

The OV9623 sensor core generates streaming pixel data at a constant frame rate, indicated by HREF, VSYNC, and
PCLK.

The timing generator outputs clocks to access the rows of the imaging array, precharging and sampling the rows of the
en g o

array sequentially. In the time between precharging and sampling a row, the charge in the pixels decrease with exposure
to incident light. This is the exposure time in rolling shutter architecture.
h

The exposure time is controlled by adjusting the time interval between precharging and sampling. After the data of the
tia nly

pixels in the row has been sampled, it is processed through analog circuitry to correct the offset and multiply the data
with corresponding gain. Following analog processing is the ADC.
lf
or

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

figure 2-1 OV9623 block diagram

OV9623
image sensor core image sensor image output
processor interface
column
sample/hold

digital gain
calibration
black level
row select

image

FIFO

DVP
ISP
array AMP ADC D[9:0]
C

gain
control
on ac

control register bank

W
fid in

PLL timing generator and system control logic SCCB slave interface
en g o
XVCLK

PWDN
RESETB
TMB
GPIO[3:0]
TM
VSYNC
HREF
PCLK
FSIN

SID[2:0]

SIOC

SIOD
h

tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

Powered by TCPDF (www.tcpdf.org)
C17 0.1μF-0603
D3 1 2 D2
D3 D2

AVDD
C15 0.1μF-0603
D5 3 4 D4
D5 D4
C1 0.1μF-0603
D7 5 6 D6
D7 D6

DVDD
C18 0.1μF-0603
D9 7 8 D8
D9 D8

12.17.2019
C2 0.1μF-0603
9 10 PWDN
NC PWDN

B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
C19 0.1μF-0603
11 12 SIOD

figure 2-2
NC SIOD
C3 0.1μF-0603

VF4
HREF 13 14 SIOC

AVDD
AVDD
AVDD
AVDD

SVDD
SVDD
SVDD
HREF SIOC

SGND
SGND
SGND

AGND
AGND
AGND
C20 0.1μF-0603 N13

DEVDD
DOVDD

DOGND
DOGND
DOGND
DOGND
DOGND
DOGND
DOGND
DOGND
DOGND
DOGND
VSYNC 15 16 DVDD
VSYNC GND
C1 N12 HREF
PCLK 17 18 AGND HREF
PCLK GND

T1
C2 N11
19 20 XCLK AVDD DOGND
PWR XCLK

J1CON32A
C3 N10 D0
21 22 AGND D0
PWR GND
C21 0.1μF-0603 C4 N9 D2

L3

FSIN
D1 23 24 D0 DOGND D2
D1 D0
C5 N8
25 26 DOGND DOVDD
NC NC

T2
C22 0.1μF-0603 C6 N7
27 28 DOGND DVDD
NC NC
C7 N6 D5
29 30 DOGND D5
NC NC
C8 N5

GPIO3
31 32 DOGND DOVDD
GND GND
C9 N4
DOGND DOGND

T3
C10 N3 D8
DOGND D8

10μH-L1008
C23 0.1μF-0603 C11 N2
DOGND DVDD
C12 M14 SID1
VF GPIO1/SID1
C24 0.1μF-0603 C13 M13
C9 10μF/16V VH DGND

PWR
+ C14 M12 VSYNC
AGND VSYNC
C25 0.1μF-0603 D1 M11 PCLK
DOGND PCLK
D2 M10
DOGND DOVDD
W
C26 0.1μF-0603 D3 M9 D1
DOGND D1
D4 M8 D3
DOGND D3
C36 0.1μF-0603 C30 0.1μF-0603 DVDD D12 M7
DOGND DGND
C

PWR
U1
D13 M6 D4
DOGND

CSP
D4

1
2
C27 0.1μF-0603 D14 M5 D6

OV9623
AVDD D6

3
2
1
E1 M4 D7

VIN
GND
DOGND D7
OV9623 reference schematic

IN

EN
C28 0.1μF-0603 E2 M3 D9

U2

GND
DOGND D9
E3 M2

U4
OUT
DOGND DOGND

3
C29 0.1μF-0603 E4 M1 SIOD

PRELIMINARY SPECIFICATION
FB
OUT
PWR XC62FP3302-SOT89
C31 10μF/6V-EIA-A DOGND SDA

4
5
ADP123-TSOT23-5
E12 L14
DOGND DOVDD
on ac
E13 L13
h
C32 0.1μF-0603 EVDD DOGND

R8
R7
E14 L12 SID0

AVDD
PVDD GPIO0/SID0
R6 0-0603 F1 L11
TM DOGND
F2 L10
DOGND DOGND
F3 L9
DOGND DOGND
F4 L8

10K-0603
20K-0603
DOGND DOGND
F12 L7
fid in
C33 0.1μF-0603 DOGND DOGND
C37 10μF/6V-EIA-A
XCLK F13 L6
XVCLK DOGND

DVDD
F14 L5

1
2
EGND DOGND
G1 L4
AGND DOGND

VIN
GND
PWDN G2 L3
PWDN DGND

U3
G3 L2 SIOC

SID2
SID1
SID0
DOGND SCL

OUT
L1

3
DOVDD
en g o

PWR XC62FP3302-SOT89

R3
R4
R5
C34 10μF/6V-EIA-A
C4 0.1μF-0603

DOGND
DOGND
DGND
DOVDD
AVDD
DOGND
DOGND
DOGND
DOGND
DOGND
DVDD
TMB
RESETB
DOGND
DOGND
DOGND
GPIO2/SID2
GPIO3
DVDD
DGND
FSIN
DOGND
DOGND
DVDD
DGND

C35 0.1μF-0603
J1
J2
J3
J4
K1
K2
K3
K4

G4
H1
H2
H3
H4
C5 0.1μF-0603
J12
J13
K12
K13
K14

G12
G13
G14
H12
H13
H14

DOVDD
C6 0.1μF-0603

10K-0603
10K-0603
10K-0603
SID2
J14 GPIO3
FSIN

tia nly
C7 0.1μF-0603
C10 0.1μF-0603
C16 0.1μF-0603
C8 0.1μF-0603
C11 0.1μF-0603
DOVDD

DVDD

AVDD
R2
R1

C12 0.1μF-0603
lf
C13 0.1μF-0603
0-0603
15K-0603

C14 0.1μF-0603

proprietary to OmniVision Technologies

DOVDD

or
2-3
 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

2.3 format and frame rate

The OV9623 supports 8/10-bit YUV, up to 18-bit combined RAW and separated 10-bit RAW. For further information on
the registers affecting windowing, cropping, and skipping (subsampling), see section 4.3.

table 2-1 DVP supported formats and frame rates

format resolution frame rate methodology

WXGA 1280 x 800 30 fps full progressive

HD 720p 1280 x 720 30 fps cropping

WVGA 752 x 480 30 fps cropping

C

VGA 640 x 480 30 fps cropping

640 x 400 640 x 400 60 fps skipping, cropping

on ac

CIF 352 x 288 60 fps skipping, cropping

QVGA 320 x 240 60 fps skipping, cropping

W
fid in

2.4 I/O control

en g o

The OV9623 I/O pad direction and driving capability can be easily adjusted. table 2-2 lists the driving capability and
direction control registers of the I/O pads.
h

tia nly

table 2-2 driving capability and direction control for I/O pads (sheet 1 of 2)
lf

function register R/W description

Bit[7:6]: output drive capability
00: 1x
or

output drive
0x3011 RW 01: 2x
capability control
10: 3x
11: 4x

input/output selection for the D[9:0] pins

0x3000[1:0],
D[9:0] I/O control RW 0: input
0x3001[7:0]
1: output

output selection for the D[9:0] pins

0: video data output
0x300E[1:0],
D[9:0] output select RW 1: register-controlled value, refer to
0x300F[7:0]
registers {0x3008[1:0], 0x3009[7:0]}
and {0x3008[1:0], 0x3001[7:0]}

0x3008[1:0],
D[9:0] output value RW D[9:0] output value
0x3009[7:0]

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 2-5

table 2-2 driving capability and direction control for I/O pads (sheet 2 of 2)

function register R/W description

Bit[7]: input/output selection for the VSYNC pin
VSYNC I/O control 0x3002 RW 0: input
1: output

Bit[7]: output selection for the VSYNC pin

0: vertical sync output
VSYNC output select 0x3010 RW
1: register-controlled value, refer to
register 0x300D[7] and 0x3002[7]

VSYNC output value 0x300D RW Bit[7]: VSYNC output value

Bit[6]: input/output selection for the HREF pin

HREF I/O control 0x3002 RW 0: input
C

1: output

Bit[6]: output selection for the HREF pin

on ac

0: horizontal reference output

HREF output select 0x3010 RW
1: register-controlled value, refer to
register 0x300D[6] and 0x3002[6]

HREF output value 0x300D RW Bit[6]: HREF output value

W
fid in

Bit[5]: input/output selection for the PCLK pin

PCLK I/O control 0x3002 RW 0: input
1: output
en g o

Bit[5]: output selection for the PCLK pin

0: pixel clock output
PCLK output select 0x3010 RW
h

1: register-controlled value, refer to

tia nly

register 0x300D[5] and 0x3002[5]

PCLK output value 0x300D RW Bit[5]: PCLK output value

lf
or

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

2.5 system clock control

The OV9623 has an on-chip PLL which generates the maximum 96 MHz system clock from a 6~27 MHz input clock. A
programmable clock divider is provided to generate different frequencies for the system. PLL adjustment should be
applied while the sensor is in software standby mode to prevent image corruption or unstable performance. Real-time
adjustment is not allowed.

figure 2-3 PLL control diagram

main PLL for system clock

6 ~ 27 MHz pre divider 3 ~ 27 MHz PLL multiplier 200 ~ 500 MHz SCLK divider
XVCLK system clock
/1, /1.5, /2, /3, /4, /5, /6, /7 register 0x3003[5:0] /2(1+register 0x3004[2:0])
C

0x3004[6:4] 0x3003[5:0] 0x3004[2:0]

on ac

secondary PLL for PCLK system clock 1

PCLK
6 ~ 27 MHz pre divider 3 ~ 27 MHz PLL multiplier 200 ~ 500 MHz PCLK divider
W
fid in

XVCLK 0
/1, /1.5, /2, /3, /4, /5, /6, /7 register 0x3005[5:0] /2(1+register 0x3006[2:0])

0x3006[6:4] 0x3005[5:0] 0x3006[2:0] 0x3024[0]

en g o
h

tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 2-7

2.6 serial camera control bus (SCCB) interface

The Serial Camera Control Bus (SCCB) interface controls the image sensor operation. Refer to the OmniVision
Technologies Serial Camera Control Bus (SCCB) Specification for detailed usage of the serial control port.

2.6.1 data transfer protocol

The data transfer of the OV9623 follows the SCCB protocol.

2.6.2 message format

The OV9623 supports the message format shown in figure 2-4. The 7-bit SCCB slave device default address is 0x30,
the low 3 bits can be configured from pad GPIO[2:0] /SID[2:0], which is controlled by 0x300C[0]. The repeated START
(Sr) condition is shown in figure 2-5 and figure 2-7.
C

figure 2-4 message type

on ac

message type: 16-bit sub-address, 8-bit data, and 7-bit slave address

slave sub address sub address

S R/W A A A data A/A P
W
fid in

address [15:8] [7:0]

index[15:8] index[7:0]
en g o

from slave to master S START condition A acknowledge

h

from master to slave P STOP condition A negative acknowledge

tia nly

direction depends on operation Sr repeated START condition

lf

2.6.3 read / write operation

The OV9623 supports four different read operations and two different write operations:
or

• a single read from random locations

• a sequential read from random locations
• a single read from current location
• a sequential read from current location
• single write to random locations
• sequential write starting from random location

The sub-address in the sensor automatically increases by one after each read/write operation.

In a single read from random locations, the master does a dummy write operation to desired sub-address, issues a
repeated start condition and then addresses the camera again with a read operation. After acknowledging its slave
address, the camera starts to output data onto the SIOD line as shown in figure 2-5. The master terminates the read
operation by setting a negative acknowledge and stop condition.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

figure 2-5 SCCB single read from random location

previous index value, K index M index M + 1

slave sub address sub address slave

S 0 A A A Sr 1 A data A P
address [15:8] [7:0] address

index value M

If the host addresses the camera with read operation directly without the dummy write operation, the camera responds
by setting the data from last used sub-address to the SIOD line as shown in figure 2-6. The master terminates the read
C

operation by setting a negative acknowledge and stop condition.

on ac

figure 2-6 SCCB single read from current location

previous index value, K index K + 1 index K + 2

W
fid in

slave slave
S 1 A data A P S 1 A data A P
en g o

address address
h

The sequential read from a random location is illustrated in figure 2-7. The master does a dummy write to the desired
tia nly

sub-address, issues a repeated start condition after acknowledge from slave and addresses the slave again with read
operation. If a master issues an acknowledge after receiving data, it acts as a signal to the slave that the read operation
shall continue from the next sub-address. When master has read the last data byte, it issues a negative acknowledge
lf

and stop condition.

or

figure 2-7 SCCB sequential read from random location

previous index value, K index M index index

M+L-1 M+L

slave sub address sub address slave

S 0 A A A Sr 1 A data A data A P
address [15:8] [7:0] address

index value M L bytes of data

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 2-9

The sequential read from current location is similar to a sequential read from a random location. The only exception is
that there is no dummy write operation as shown in figure 2-8. The master terminates the read operation by setting a
negative acknowledge and stop condition.

figure 2-8 SCCB sequential read from current location

previous index value, K index K + 1 index index

K+L-1 K+L

slave
S 1 A data A data A data A P
address
C

L bytes of data
on ac

The write operation to a random location is illustrated in figure 2-9. The master issues a write operation to the slave, sets
the sub-address and data correspondingly after the slave has acknowledged. The write operation is terminated with a
stop condition from the master.
W
fid in

figure 2-9 SCCB single write to random location

en g o

previous index value, K index M index M + 1

h

tia nly

slave sub address sub address

S 0 A A A data A/A P
address [15:8] [7:0]
lf

index value M
or

The sequential write is illustrated in figure 2-10. The slave automatically increments the sub-address after each data
byte. The sequential write operation is terminated with stop condition from the master.

figure 2-10 SCCB sequential write to random location

previous index value, K index M index index

M+L-1 M+L

slave sub address sub address

S 0 A A A data A data A/A P
address [15:8] [7:0]

index value M L bytes of data

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

2.6.4 SCCB timing

figure 2-11 SCCB interface timing

tF tHIGH tR

SIOC
tLOW
tSU:DAT
tHD:STA tSU:STO

SIOD (IN)

tSU:STA tHD:DAT tBUF

tAA
C

SIOD (OUT)
on ac

tDH
W
fid in

table 2-3 SCCB interface timing specificationsab

symbol parameter min typ max unit

en g o

fSIOC clock frequency 400 kHz

h

tLOW clock low period 1.3 µs

tia nly

tHIGH clock high period 0.6 µs

tAA SIOC low to data out valid 0.1 0.9 µs

tBUF bus free time before new start 1.3 µs

lf

tHD:STA start condition hold time 0.6 µs

or

tSU:STA start condition setup time 0.6 µs

tHD:DAT data in hold time 0 µs

tSU:DAT data in setup time 0.1 µs

tSU:STO stop condition setup time 0.6 µs

tR, tF SCCB rise/fall times 0.3 µs

tDH data out hold time 0.05 µs

a. SCCB timing is based on 400kHz mode

b. timing measurement shown at beginning of rising edge or end of falling edge signifies 30%,
timing measurement shown in middle of rising/falling edge signifies 50%,
timing measurement shown at end of rising edge or beginning of falling edge signifies 70%

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 2-11

2.7 standby

To initiate hardware standby mode, the PWDN pin must be tied to high. When this occurs, the OV9623 internal device
clock is halted and all internal counters are reset and registers are maintained.

2.8 power on timing

figure 2-12 power on timing diagram

TDVDD

DOVDD TAVDD
C

TPWDN
DVDD
on ac

AVDD
W
fid in

PWDN
en g o

RESETB
h

tia nly

TRST
lf

SIOC
TSCCB
...
or

SIOD
...

table 2-4 power on timing

parameter min max unit

TDVDD >0 10 ms

TAVDD >0 n/a ms

TPWDN >1 n/a ms

TRST >200 n/a µs

TSCCB >2048 n/a XVCLK cycles

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

2.9 system control

table 2-5 system control registers

default
address register name value R/W description
Bit[7:1]: Not used
Bit[0]: Turn on video stream after power
0x0100 STREAM MODE 0x00 RW up, always set to "1"
0: Not used
1: Stream on

0x0103 SOFTWARE RESET 0x00 RW Software Reset will Auto Clear by Itself to 0x00
C
on ac
W
fid in
en g o
h

tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 3-1

3 pixel array structure

The OV9623 sensor has an image array of 1312 columns by 828 rows. figure 3-1 shows a cross-section of the image
sensor array.

The color filters are arranged in a Bayer pattern. The primary color BG/GR array is arranged in line-alternating fashion.
Of the 828 rows, 814 rows are active rows and can be output. The other rows are used for black level calibration and
interpolation.

The sensor array design is based on a read-out system with line-by-line transfer and an electronic shutter with a
synchronous pixel read-out scheme.

figure 3-1 sensor array region color filter layout

C

columns
1306
1307
1308
1309
1310
1311
on ac 0
1
2
3
4
5

0 B Gb B Gb B Gb B Gb B Gb B Gb
1 Gr R Gr R Gr R Gr R Gr R Gr R
2 B Gb B Gb B Gb B Gb B Gb B Gb
W
fid in

3 Gr R Gr R Gr R Gr R Gr R Gr R
dummy
10 B Gb B Gb B Gb B Gb B Gb B Gb
11 Gr R Gr R Gr R Gr R Gr R Gr R
12 B Gb B Gb B Gb B Gb B Gb B Gb
en g o

13 Gr R Gr R Gr R Gr R Gr R Gr R
rows

14 B Gb B Gb B Gb B Gb B Gb B Gb
h

15 Gr R Gr R Gr R Gr R Gr R Gr R
16 B Gb B Gb B Gb B Gb B Gb B Gb
tia nly

17 Gr R Gr R Gr R Gr R Gr R Gr R
active
pixel
824 B Gb B Gb B Gb B Gb B Gb B Gb
825 Gr R Gr R Gr R Gr R Gr R Gr R
lf

826 B Gb B Gb B Gb B Gb B Gb B Gb
827 Gr R Gr R Gr R Gr R Gr R Gr R
or

active
pixel

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

C
on ac
W
fid in
en g o
h

tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-1

4 image sensor core digital functions

4.1 mirror and flip

The OV9623 provides mirror mode, which reverses the sensor data read-out order horizontally, and flip mode which
reverses it vertically (see figure 4-1).

figure 4-1 mirror and flip samples

F F
F F
C
on ac

original image mirrored image flipped image mirrored and flipped

image
W
fid in

table 4-1 mirror and flip function controla

en g o

function register description

h

Bit[1:0]: Mirror ON/OFF select

00: Horizontal mirror OFF
tia nly

mirror 0x381D 01: Not allowed

10: Not allowed
11: Horizontal mirror ON
lf

Bit[7:6]: Flip ON/OFF select

00: Vertical flip OFF
flip 0x381C 01: Not allowed
or

10: Not allowed

11: Vertical flip ON

a. when mirror mode is on, register 0x6900[0] needs to be set to 0x01 in order to ensure correct color output

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

4.2 test pattern

For testing purposes, the OV9623 offers one type of analog test pattern and three types of digital test patterns. The
analog test pattern is a color bar overlaid on an image, which can be enabled by register 0x370A[2]. The digital test
patterns include color bar, square and random data. The OV9623 also offers two digital effects for the test patterns:
transparent effect and rolling bar effect. The digital test pattern function is enabled by register 0x503D[7] and the pattern
is selected by register 0x503E[1:0].

The digital test pattern passes through the pipeline. To get a consistent output pattern, register 0x5000 must be set to
0x78 to turn off some of the ISP blocks and register 0x3042 must be set to 0xF9 after the software reset and before
enabling the test pattern.

4.2.1 color bar

C

There are four types of color bars shown in figure 4-2.

figure 4-2 color bar types

on ac
W
fid in
en g o
h

color bar type 1 color bar type 2

tia nly

0x503D[5:4]=2'b00 0x503D[5:4]=2'b01
lf
or

color bar type 3 color bar type 4

0x503D[5:4]=2'b10 0x503D[5:4]=2'b11

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-3

4.2.2 square
There are two types of square test patterns: color square and black-white square.

figure 4-3 color, black and white square bars

color square black-white square

C

4.2.3 random data

on ac

There are two types of random data test patterns: frame-changing and frame-fixed random data.

4.2.4 transparent effect

W
fid in

figure 4-4 is an example which shows a transparent color bar image.

figure 4-4 transparent effect

en g o
h

tia nly
lf
or

4.2.5 rolling bar effect

figure 4-5 is an example which shows a rolling bar on color bar image.

figure 4-5 rolling bar effect

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 4-2 test pattern registers

default
address register name value R/W description
Bit[2]: Analog color bar enable
0x370A SENSOR REG0A 0x00 RW 0: Disable
1: Enable

Bit[7]: Digital test pattern enable

0: Disable
1: Enable
Bit[5:4]: Color bar type (see figure 4-2)
Bit[2]: Rolling horizontal bar in color bar test
0x503D ISP CTRL3D 0x00 RW
pattern
0: Disable rolling bar
C

1: Enable rolling bar

Bit[1:0]: Debug control
Changing this value is not allowed
on ac

Bit[7:4]: Seed of random number

Initial seed for random data pattern
Bit[3]: B&W square test pattern enable
W
fid in

0: Output square is color square

1: Output square is black-white square
Bit[2]: Transparent enable mode
0x503E ISP CTRL3E 0x00 RW 0: Disable
1: Enable
en g o

Bit[1:0]: Test pattern type

00: Color bar
h

01: Random data

10: Square
tia nly

11: Not allowed

lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-5

4.3 image cropping and windowing

An image cropping area is defined by four parameters: H_crop_start, H_crop_end, V_crop_start, V_crop_end;
windowing area is defined by four parameters, horizontal start (H_win_off), horizontal width (H_output_size), vertical start
(V_win_off), and vertical height (V_output_size). By properly setting the parameters, any portion within the sensor array
can be cropped as a visible area. Windowing is achieved by simply masking off the pixels outside of the window; thus,
the original timing is not affected. Also, it will not conflict with the flip and mirror functions. The selected window size must
be equal to or smaller than the crop size.

The OV9623 can:

• support any size vertical crop

• support three size horizontal crop: 1312, 768 and 656
• support HDR mode
C

• support non-HDR mode

• support mirror and flip mode
on ac

• support any size windowing

figure 4-6 frame structure diagram

W
fid in

horizontal full size: 1312

H_crop_start H_crop_end
en g o

sensor array horizontal output size

h
V_crop_start

H_win_off
sensor array vertical output size

tia nly

H_output_size
vertical full size: 814

V_win_off
V_output_size

lf
or
V_crop_end

VTS is adjusted by registers (0x6E42[7:0], 0x6E43[7:0]). The reference initialization settings must be used for these two
registers to be valid.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 4-3 format related registers (sheet 1 of 2)

default
address value R/W description
Bit[4:3]: Horizontal crop mode select
00: Full size
01: Horizontal crop to 768
0x3621 0x03 RW
10: Horizontal crop to 656
11: Not used
Bit[2:0]: Analog delay option

0x3802 0x00 RW Vertical Crop Start Address High Byte

0x3803 0x00 RW Vertical Crop Start Address Low Byte

0x3806 0x03 RW Vertical Crop End Address High Byte

C

0x3807 0x28 RW Vertical Crop End Address Low Byte

on ac

0x3808 0x05 RW DVP Horizontal Output Size High Byte

0x3809 0x00 RW DVP Horizontal Output Size Low Byte

0x380A 0x03 RW DVP Vertical Output Size High Byte

W
fid in

0x380B 0x20 RW DVP Vertical Output Size Low Byte

0x380C 0x07 RW Line Length High Byte

en g o

0x380D 0x70 RW Line Length Low Byte

0x380E 0x03 RW Frame Length High Byte

h

0x380F 0x48 RW Frame Length Low Byte

tia nly

0x3810 0x00 RW Horizontal ISP Window Offset High Byte

0x3811 0x00 RW Horizontal ISP Window Offset Low Byte

lf

0x3812 0x00 RW Vertical ISP Window Offset High Byte

0x3813 0x00 RW Vertical ISP Window Offset Low Byte

or

0x381C 0x00 RW Bit[0]: Vertical sub-sample in array

Bit[7]: Vertical sub-sample in ISP

0x5005 0x08 RW
Bit[0]: VAP enable

Bit3:0]: DVP PCLK divider

0x3007 0x01 RW
Used when ISP horizontal subsample

Bit[2]: VFIFO 2 bytes input

0x4600 0x04 RW 0: Raw10 mode
1: Other mode

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-7

table 4-3 format related registers (sheet 2 of 2)

default
address value R/W description
Bit[7:4]: Output format select
0x3: YUV mode
0xF: RAW mode
Others: Not allowed
0x4300 0xF8 RW Bit[3:0]: pix_order_ctrl
1000: YUYV
1001: YVYU
1010: UYVY
1011: VYUY
C

4.4 AEC/AGC algorithms

on ac

In the OV9623, the exposure/gain control is designed to adjust the weighted frame average to a user defined range. The
weight of each pixel includes three parts: position weight, combination weight and luminance weight. Instead of using
the whole frame, the statistic window can be defined manually with the left-top corner {0x5601[2:0], 0x5602},
W
fid in

{0x5603[1:0], 0x5604}, width {0x5605[2:0], 0x5606} and height {0x5607[1:0], 0x5608}. The pixels outside of the window
will not be included in the weighted average.

There are three target modes: AA, AB and ABC mode. This is defined by the target mode register 0xC450[1:0].
en g o

The AEC/AGC algorithms support HDR mode and non-HDR mode. Register 0xC454[0] must be set to 1 for non-HDR
h

mode and 0 for HDR mode.

tia nly

In non-HDR mode, the sensor only uses one sub-pixel. In HDR mode, the AEC/AGC needs to determine the exposure
and the gain for the two sub-pixels. It supports auto ratio mode, fixed ratio mode and geometric proportion mode.
lf

Auto ratio mode means the long exposure/short exposure ratio changes automatically according to the scene. It supports
all modes (AA,AB and ABC). To enable auto ratio mode, the fixed ratio mode register 0xC456[0] and the geometric
proportion mode register 0xC457[0] must be set to 0.
or

Fixed ratio mode means the long exposure/short exposure ratio is fixed regardless of the scene. It supports all modes
(AA, AB and ABC). To enable fixed ratio mode, register 0xC456[0] should be set to 1. The fixed ratio can be set by
register 0xC490. In this mode, the geometric proportion mode register 0xC457[0] should be set to 0.

Geometric proportion mode works only in AB or ABC modes. This means that the relationship between the stable range
of AB or ABC frame is fixed. The fixed relationship can be adjusted by registers 0xC492 and 0xC493. In geometric
proportion mode, the register 0xC457[0] must be set to be 1.

4.4.1 position weight

The position weight is decided by the position of the pixel, which also includes two independent parts: the windowing
weight and the region of interest (ROI) weight. The windowing weight function divides the statistic window into 13
windows as shown in figure 4-7 and each window has a weight defined by one of registers 0x562E~0x5647. Also, the
size and position of the center 3×3 windows can be defined with registers 0x5609~0x5618. The ROI weight is determined

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

by whether the pixel is within the ROI region which is defined with the registers 0x5619~0x5628. The weight of pixels,
which are in ROI region is defined with register 0x562A (for long exposure channel) or 0x562C (for short exposure
channel). The weight of other pixels is defined with register 0x562B (for long exposure channel) and 0x562D (for short
exposure channel). The long ROI shift (0x5629[5:3]) and short ROI shift (0x5629[2:0]) control the precision of the long
ROI weight and the short ROI weight, separately. The weight given to a window is relative to the other windows. Thus,
a window weighted "4" has four times the weight as one weighted "1". The default is that all windows are weighted "1",
and thus, all are weighted evenly.

figure 4-7 position window diagram

image {0x5603[2:0], 0x5604} L: {0x561D[2:0], 0x561E}

S: {0x561F[2:0], 0x5620}
{0x5601[2:0], 0x5602}

{0x5605[2:0], 0x5606}
0 1
C

S: {0x560D[2:0], 0x560E} window

L: {0x560F[2:0], 0x5610}
on ac

L: {0x5611[2:0], 0x5612}
S: {0x5613[2:0], 0x5614} ROI

S: {0x5617[2:0], 0x5618}
L: {0x5615[2:0], 0x5616}
4 5 6
W
fid in L: {0x5609[2:0], 0x560A}
S: {0x560B[2:0], 0x560C}

7 8 9
L: {0x5619[2:0], 0x561A}
S: {0x561B[2:0], 0x561C}

L: {0x5621[2:0], 0x5622}
S: {0x5623[2:0], 0x5624}
en g o

10 11 12
h

tia nly

2 3
L: {0x5625[2:0], 0x5626}
{0x5607[2:0], 0x5608}
lf

S: {0x5627[2:0], 0x5628}
or

table 4-4 position window control registers (sheet 1 of 5)

default
address register name value R/W description
Bit[7:2]: Not used
Bit[1:0]: Sampling
0x5600 AEC CTRL00 0x01 RW 0x: 2
10: 4
11: 8

Bit[7:3]: Not used

Bit[2:0]: Statwinleft[10:8]
0x5601 AEC CTRL01 0x00 RW
Horizontal start point of outer 4-zone
statistic window

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-9

table 4-4 position window control registers (sheet 2 of 5)

default
address register name value R/W description
Bit[7:0]: Statwinleft[7:0]
0x5602 AEC CTRL02 0x00 RW Horizontal start point of outer 4-zone
statistic window

Bit[7:2]: Not used

Bit[1:0]: Statwintop[9:8]
0x5603 AEC CTRL03 0x00 RW
Vertical start point of outer 4-zone statistic
window

Bit[7:0]: Statwintop[7:0]
0x5604 AEC CTRL04 0x00 RW
Vertical start point for statistic image
C

Bit[7:3]: Not used

Bit[2:0]: Statwinright[10:8]
0x5605 AEC CTRL05 0x00 RW
Horizontal end point of outer 4-zone
on ac

statistic window

Bit[7:0]: Statwinright[7:0]
0x5606 AEC CTRL06 0x00 RW Horizontal end point of outer 4-zone
W
fid in

statistic window

Bit[7:2]: Not used

Bit[1:0]: Statwinbottom[9:8]
0x5607 AEC CTRL07 0x00 RW
Vertical end point of outer 4-zone statistic
en g o

window

Bit[7:0]: Statwinbottom
h

0x5608 AEC CTRL08 0x00 RW Bit[7:0]: Vertical end point of outer 4-zone statistic
tia nly

window

Bit[7:3]: Not used

Bit[2:0]: winleft_l[10:8]
0x5609 AEC CTRL09 0x00 RW
lf

Horizontal start point of inner 9-zone

window long exposure sub-pixel

Bit[7:0]: winleft_l
or

0x560A AEC CTRL0A 0x64 RW Bit[7:0]: Horizontal start point of inner 9-zone
window long exposure sub-pixel

Bit[7:3]: Not used

Bit[2:0]: winleft_s[10:8]
0x560B AEC CTRL0B 0x00 RW
Horizontal start point of inner 9-zone
window short exposure sub-pixel

Bit[7:0]: winleft_s[7:0]
0x560C AEC CTRL0C 0x64 RW Horizontal start point of inner 9-zone
window short exposure sub-pixel

Bit[7:2]: Not used

Bit[1:0]: wintop_l[9:8]
0x560D AEC CTRL0D 0x00 RW
Vertical start point of inner 9-zone window
long exposure sub-pixel

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 4-4 position window control registers (sheet 3 of 5)

default
address register name value R/W description
Bit[7:0]: wintop_l[7:0]
0x560E AEC CTRL0E 0x4B RW Vertical start point of inner 9-zone window
long exposure sub-pixel

Bit[7:2]: Not used

Bit[1:0]: wintop_s[9:8]
0x560F AEC CTRL0F 0x00 RW
Vertical start point of inner 9-zone window
short exposure sub-pixel

Bit[7:0]: wintop_s[7:0]
0x5610 AEC CTRL10 0x4B RW Vertical start point of inner 9-zone window
short exposure sub-pixel
C

Bit[7:3]: Not used

Bit[2:0]: winwidth_l[10:8]
on ac

0x5611 AEC CTRL11 0x00 RW

Horizontal width of inner 9-zone window
long exposure sub-pixel

Bit[7:0]: winwidth_l[7:0]
W
fid in

0x5612 AEC CTRL12 0xC8 RW Horizontal width of inner 9-zone window

long exposure sub-pixel

Bit[7:3]: Not used

Bit[2:0]: winwidth_s[10:8]
en g o

0x5613 AEC CTRL13 0x00 RW

Horizontal width of inner 9-zone window
short exposure sub-pixel
h

Bit[7:0]: winwidth_s[7:0]
tia nly

0x5614 AEC CTRL14 0xC8 RW Horizontal width of inner 9-zone window

short exposure sub-pixel

Bit[7:2]: Not used

lf

Bit[1:0]: winheight_l[9:8]
0x5615 AEC CTRL15 0x00 RW
Vertical width of inner 9-zone window long
exposure sub-pixel
or

Bit[7:0]: winheight_l[7:0]
0x5616 AEC CTRL16 0x96 RW Vertical width of inner 9-zone window long
exposure sub-pixel

Bit[7:2]: Not used

Bit[1:0]: winheight_s[9:8]
0x5617 AEC CTRL17 0x00 RW
Vertical width of inner 9-zone window long
exposure sub-pixel

Bit[7:0]: winheight_s[7:0]
0x5618 AEC CTRL18 0x96 RW Vertical width of inner 9-zone window long
exposure sub-pixel

Bit[7:3]: Not used

Bit[2:0]: roi_left_l[10:8]
0x5619 AEC CTRL19 0x00 RW
Horizontal start point for ROI for long
exposure sub-pixel

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-11

table 4-4 position window control registers (sheet 4 of 5)

default
address register name value R/W description
Bit[7:0]: roi_left_l[7:0]
0x561A AEC CTRL1A 0x00 RW Horizontal start point for ROI for long
exposure sub-pixel

Bit[7:3]: Not used

Bit[2:0]: roil_eft_s[10:8]
0x561B AEC CTRL1B 0x00 RW
Horizontal start point for ROI for short
exposure sub-pixel

Bit[7:0]: roi_left_s[7:0]
0x561C AEC CTRL1C 0x00 RW Horizontal start point for ROI for short
exposure sub-pixel
C

Bit[7:2]: Not used

Bit[1:0]: roi_top_l[9:8]
on ac

0x561D AEC CTRL1D 0x00 RW

Vertical start point for ROI for long exposure
sub-pixel

Bit[7:0]: roi_top_l[7:0]
W
fid in

0x561E AEC CTRL1E 0x00 RW Vertical start point for ROI for long exposure
sub-pixel

Bit[7:2]: Not used

Bit[1:0]: roi_top_s[9:8]
en g o

0x561F AEC CTRL1F 0x00 RW

Vertical start point for ROI for short
exposure sub-pixel
h

Bit[7:0]: roi_top_s[7:0]
tia nly

0x5620 AEC CTRL20 0x00 RW Vertical start point for ROI for short
exposure sub-pixel

Bit[7:3]: Not used

lf

Bit[2:0]: roi_right_l[10:8]
0x5621 AEC CTRL21 0x00 RW
Horizontal end point for ROI for long
exposure sub-pixel
or

Bit[7:0]: roi_right_l[7:0]
0x5622 AEC CTRL22 0x00 RW Horizontal end point for ROI for long
exposure sub-pixel

Bit[7:3]: Not used

Bit[2:0]: roi_right_s[10:8]
0x5623 AEC CTRL23 0x00 RW
Horizontal end point for ROI for short
exposure sub-pixel

Bit[7:0]: roi_right_s[7:0]
0x5624 AEC CTRL24 0x00 RW Horizontal end point for ROI for short
exposure sub-pixel

Bit[7:2]: Not used

Bit[1:0]: roi_bottom_l[9:8]
0x5625 AEC CTRL25 0x00 RW
Vertical end point for ROI for long exposure
sub-pixel

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 4-4 position window control registers (sheet 5 of 5)

default
address register name value R/W description
Bit[7:0]: roi_bottom_l[7:0]
0x5626 AEC CTRL26 0x00 RW Vertical end point for ROI for long exposure
sub-pixel

Bit[7:2]: Not used

Bit[1:0]: roi_bottom_s[9:8]
0x5627 AEC CTRL27 0x00 RW
Vertical end point for ROI for short
exposure sub-pixel

Bit[7:0]: roi_bottom_s[7:0]
0x5628 AEC CTRL28 0x00 RW Vertical end point for ROI for short
exposure sub-pixel
C

Bit[7:6]: Not used

0x5629 AEC CTRL29 0x00 RW Bit[5:3]: r_roishift_l
on ac

Bit[2:0]: r_roishift_s

figure 4-8 position weight diagram

W
fid in

image
en g o

0 L: 0x562F 1
L: 0x562E
S: 0x563B
window S: 0x563C
h

tia nly

ROI
S: 0x562D
S: 0x562C
L: 0x562A

L: 0x562B
out ROI:
in ROI:

4 5 6
lf

L: 0x5632 L: 0x5633 L: 0x5634

S: 0x563F S: 0x5640 S: 0x5641
7 8 9
or

L: 0x5635 L: 0x5636 L: 0x5637

S: 0x5642 S: 0x5643 S: 0x5644
10 11 12
L: 0x5638 L: 0x5639 L: 0x563A
S: 0x5645 S: 0x5646 S: 0x5647

L: 0x5630 L: 0x5631
2 S: 0x563D S: 0x563E 3

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-13

table 4-5 AEC position weight registers (sheet 1 of 2)

default
address register name value R/W description
Bit[4:3]: Horizontal crop mode select
00: Full size
01: Horizontal crop to 768
0x3621 ANA_ARRAY1 0x03 RW
10: Horizontal crop to 656
11: Not used
Bit[2:0]: Analog delay option

0x562A AEC CTRL2A 0x01 RW ROIweightl0 for Long Exposure Sub-pixel

0x562B AEC CTRL2B 0x01 RW ROIweightl1 for Long Exposure Sub-pixel

0x562C AEC CTRL2C 0x01 RW ROIweights0 for Short Exposure Sub-pixel

C

0x562D AEC CTRL2D 0x01 RW ROIweights1 for Short Exposure Sub-pixel

on ac

0x562E AEC CTRL2E 0x01 RW Weightl0 for Long Exposure Sub-pixel

0x562F AEC CTRL2F 0x01 RW Weightl1 for Long Exposure Sub-pixel

0x5630 AEC CTRL30 0x01 RW Weightl2 for Long Exposure Sub-pixel

W
fid in

0x5631 AEC CTRL31 0x01 RW Weightl3 for Long Exposure Sub-pixel

0x5632 AEC CTRL32 0x01 RW Weightl4 for Long Exposure Sub-pixel

en g o

0x5633 AEC CTRL33 0x01 RW Weightl5 for Long Exposure Sub-pixel

0x5634 AEC CTRL34 0x01 RW Weightl6 for Long Exposure Sub-pixel

h

0x5635 AEC CTRL35 0x01 RW Weightl7 for Long Exposure Sub-pixel

tia nly

0x5636 AEC CTRL36 0x01 RW Weightl8 for Long Exposure Sub-pixel

0x5637 AEC CTRL37 0x01 RW Weightl9 for Long Exposure Sub-pixel

lf

0x5638 AEC CTRL38 0x01 RW Weightla for Long Exposure Sub-pixel

0x5639 AEC CTRL39 0x01 RW Weightlb for Long Exposure Sub-pixel

or

0x563A AEC CTRL3A 0x01 RW Weightlc for Long Exposure Sub-pixel

0x563B AEC CTRL3B 0x01 RW Weights0 for Short Exposure Sub-pixel

0x563C AEC CTRL3C 0x01 RW Weights1 for Short Exposure Sub-pixel

0x563D AEC CTRL3D 0x01 RW Weights2 for Short Exposure Sub-pixel

0x563E AEC CTRL3E 0x01 RW Weights3 for Short Exposure Sub-pixel

0x563F AEC CTRL3F 0x01 RW Weights4 for Short Exposure Sub-pixel

0x5640 AEC CTRL40 0x01 RW Weights5 for Short Exposure Sub-pixel

0x5641 AEC CTRL41 0x01 RW Weights6 for Short Exposure Sub-pixel

0x5642 AEC CTRL42 0x01 RW Weights7 for Short Exposure Sub-pixel

0x5643 AEC CTRL43 0x01 RW Weights8 for Short Exposure Sub-pixel

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 4-5 AEC position weight registers (sheet 2 of 2)

default
address register name value R/W description
0x5644 AEC CTRL44 0x01 RW Weights9 for Short Exposure Sub-pixel

0x5645 AEC CTRL45 0x01 RW Weightsa for Short Exposure Sub-pixel

0x5646 AEC CTRL46 0x01 RW Weightsb for Short Exposure Sub-pixel

0x5647 AEC CTRL47 0x01 RW Weightsc for Short Exposure Sub-pixel

4.4.2 exposure/gain control

Both long and short exposure are controlled by the same algorithm, which estimates the new exposure based on the
C

weighted average of current frame. Long exposure can change freely in the whole range. Short exposure, however, is
limited by the new estimated dynamic range and long exposure.
on ac

The AEC/AGC adjustment step is calculated by the distance between current weighted average and the target. When
the current weighted average is far from the stable range, the exposure will adjust by big steps to quickly bring the image
to stable range. When the current weighted average is close to the stable range, the exposure will adjust by small steps
W
fid in

to avoid oscillating.

In the OV9623, the exposure time and gain changes every two frames. At the end of first frame, the new exposure time
en g o

and gain will be estimated and the exposure time registers will be updated afterward. The gain registers will be updated
at the end of the second frame. So, the third frame will be the result of new exposure and gain.
h

tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-15

figure 4-9 AEC/AGC target/range diagram

stable range adjustment

start after getting out of

stable_out range
slow speed range

stable_out range

stop after going into

stable_in range

stable_in range
raw target
C
on ac
W
fid in
en g o
h

tia nly

table 4-6 AEC target/range control registers (sheet 1 of 18)

default
address register name value R/W description
lf

0x5648 AEC CTRL48 0x01 RW Minwl for Long Exposure Sub-pixel

or

0x5649 AEC CTRL49 0x01 RW Minws for Short Exposure Sub-pixel

Bit[7:2]: Not used

0x564A AEC CTRL4A 0x00 RW Bit[1:0]: Maxwl[9:8] for long exposure
sub-pixel

Bit[7:0]: Maxwl[7:0] for long exposure

0x564B AEC CTRL4B 0x20 RW
sub-pixel

Bit[7:2]: Not used

0x564C AEC CTRL4C 0x01 RW Bit[1:0]: Maxws[9:8] for short exposure
sub-pixel

Bit[7:0]: Maxws[7:0] for short exposure

0x564D AEC CTRL4D 0x00 RW
sub-pixel

0x566C AEC CTRL6C 0x00 RW Bit[0]: his_en

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 4-6 AEC target/range control registers (sheet 2 of 18)

default
address register name value R/W description
0x566D AEC CTRL6D 0x00 RW Bit[7:0]: his_addr

0x566E AEC CTRL6E – R Bit[6:0]: his_data[14:8]

0x566F AEC CTRL6F – R Bit[7:0]: his_data[7:0]

0x56D0 AEC CTRLD0 0x00 RW Bit[2:0]: r_man_en

0x56D1 AEC CTRLD1 0x00 RW Bit[1:0]: cameragain_l_m[9:8]

0x56D2 AEC CTRLD2 0x10 RW Bit[7:0]: cameragain_l_m[7:0]

0x56D3 AEC CTRLD3 0x00 RW Bit[1:0]: cameragain_s_m[9:8]

C

0x56D4 AEC CTRLD4 0x10 RW Bit[7:0]: cameragain_s_m[7:0]

on ac

0x56D5 AEC CTRLD5 0x00 RW Bit[7:0]: exp_l_m[31:24]

0x56D6 AEC CTRLD6 0x00 RW Bit[7:0]: exp_l_m[23:16]

W
fid in

0x56D7 AEC CTRLD7 0x00 RW Bit[7:0]: exp_l_m[15:8]

0x56D8 AEC CTRLD8 0x00 RW Bit[7:0]: exp_l_m[7:0]

0x56D9 AEC CTRLD9 0x00 RW Bit[7:0]: exp_s_m[31:24]

en g o

0x56DA AEC CTRLDA 0x00 RW Bit[7:0]: exp_s_m[23:16]

h

0x56DB AEC CTRLDB 0x00 RW Bit[7:0]: exp_s_m[15:8]

tia nly

0x56DC AEC CTRLDC 0x00 RW Bit[7:0]: exp_s_m[7:0]

0x56DF AEC CTRLDF 0x02 RW Bit[2:0]: digigain_l_m[10:8]

lf

0x56E0 AEC CTRLE0 0x00 RW Bit[7:0]: digigain_l_m[7:0]

0x56E1 AEC CTRLE1 0x02 RW Bit[2:0]: digigain_s_m[10:8]

or

0x56E2 AEC CTRLE2 0x00 RW Bit[7:0]: digigain_s_m[7:0]

0x56E3 AEC CTRLE3 0x00 RW Bit[0]: exp_ctrl

0x56E4 AEC CTRLE4 0x00 RW Bit[3:0]: exp_l_f[11:8]

0x56E5 AEC CTRLE5 0x00 RW Bit[7:0]: exp_l_f[7:0]

Bit[7:4]: Not used

0x56E6 AEC CTRLE6 0x00 RW
Bit[3:0]: exp_s_f[11:8]

0x56E7 AEC CTRLE7 0x00 RW Bit[7:0]: exp_s_f[7:0]

Bit[7:1]: Not used

0x56E8 AEC CTRLE8 0x00 RW
Bit[0]: snrgain_l_m[8]

0x56E9 AEC CTRLE9 0x00 RW Bit[7:0]: snrgain_l_m[7:0]

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-17

table 4-6 AEC target/range control registers (sheet 3 of 18)

default
address register name value R/W description
Bit[7:1]: Not used
0x56EA AEC CTRLEA 0x00 RW
Bit[0]: snrgain_s_m[8]

0x56EB AEC CTRLEB 0x00 RW Bit[7:0]: snrgain_s_m[7:0]

Bit[7:1]: Not used

Bit[0]: Non-HDR mode at high
temperatures
NON-HDR MODE AT Set to 0 if HDR mode is on. Set to 1
0xC2ED 0x00 RW
HIGH TEMPERATURES if non-HDR mode is on.

This register value will be automatically

C

initialized by sensor after powering up.

Bit[7:0]: manual_expo11[15:8]
on ac

0xC2F0 S_MANUAL_EXP11 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.
W
fid in

Bit[7:0]: manual_expo11[7:0]

0xC2F1 S_MANUAL_EXP11 – RW This register value will be automatically

en g o

initialized by sensor after powering up. Default

value is random.
h

Bit[7:0]: manual_expo12[15:8]
tia nly

0xC2F2 S_MANUAL_EXP12 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.
lf

Bit[7:0]: manual_expo12[7:0]

0xC2F3 S_MANUAL_EXP12 – RW This register value will be automatically

or

initialized by sensor after powering up. Default

value is random.

Bit[7:0]: manual_expo21[15:8]

0xC2F4 S_MANUAL_EXP21 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

Bit[7:0]: manual_expo21[7:0]

0xC2F5 S_MANUAL_EXP21 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 4-6 AEC target/range control registers (sheet 4 of 18)

default
address register name value R/W description
Bit[7:0]: manual_expo22[15:8]

0xC2F6 S_MANUAL_EXP22 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

Bit[7:0]: manual_expo22[7:0]

0xC2F7 S_MANUAL_EXP22 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.
C

Bit[7:0]: manual_expo31[15:8]
on ac

0xC2F8 S_MANUAL_EXP31 0x34 RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

Bit[7:0]: manual_expo31[7:0]
W
fid in

0xC2F9 S_MANUAL_EXP31 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.
en g o

Bit[7:0]: manual_expo32[15:0]
h

0xC2FA S_MANUAL_EXP32 – RW This register value will be automatically

tia nly

initialized by sensor after powering up. Default

value is random.

Bit[7:0]: manual_expo32[7:0]
lf

0xC2FB S_MANUAL_EXP22 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.
or

Bit[7:0]: manual_gain11[15:8]

0xC2FC S_MANUAL_GAIN11 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

Bit[7:0]: manual_gain11[7:0]

0xC2FD S_MANUAL_GAIN11 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

Bit[7:0]: manual_gain12[15:8]

0xC2FE S_MANUAL_GAIN12 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-19

table 4-6 AEC target/range control registers (sheet 5 of 18)

default
address register name value R/W description
Bit[7:0]: manual_gain12[7:0]

0xC2FF S_MANUAL_GAIN12 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

Bit[7:0]: manual_gain21[15:8]

0xC300 S_MANUAL_GAIN21 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.
C

Bit[7:0]: manual_gain21[7:0]
on ac

0xC301 S_MANUAL_GAIN21 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

Bit[7:0]: manual_gain22[15:8]
W
fid in

0xC302 S_MANUAL_GAIN22 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.
en g o

Bit[7:0]: manual_gain22[7:0]
h

0xC303 S_MANUAL_GAIN22 – RW This register value will be automatically

tia nly

initialized by sensor after powering up. Default

value is random.

Bit[7:0]: manual_gain31[15:8]
lf

0xC304 S_MANUAL_GAIN31 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.
or

Bit[7:0]: manual_gain31[7:0]

0xC305 S_MANUAL_GAIN31 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

Bit[7:0]: manual_gain32[15:8]

0xC306 S_MANUAL_GAIN32 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

Bit[7:0]: manual_gain32[7:0]

0xC307 S_MANUAL_GAIN32 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 4-6 AEC target/range control registers (sheet 6 of 18)

default
address register name value R/W description
Bit[7:1]: Not used
Bit[0]: manual_en
0: Disable
1: Enable
0xC308 S_MANUAL_EN – RW
When register value is 0x00, it means function is
disabled; all other values mean function is
enabled. This register value must be initialized
by user and must not be removed from start up
sequence. Default value is random.

Bit[7:3]: Not used

C

Bit[2]: targetc_manual_en
0: Disable
on ac

1: Enable
Bit[1]: targetb_manual_en
0: Disable
1: Enable
0xC309 S_MANUAL_MODE – RW
W
fid in

Bit[0]: targeta_manual_en
0: Disable
1: Enable
en g o

This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
h

Bit[7:2]: Not used

tia nly

Bit[1:0]: manual_done
00: Write protected
01: Write valid once
0xC30A S_MANUAL_DONE – RW 10: Write valid always
lf

This register value must be initialized by user

and must not be removed from start up
or

sequence. Default value is random.

Bit[7:2]: Not used

Bit[1:0]: Target number
01: AA mode
10: AB mode
0xC450 TARGET_NUM – RW 11: ABC mode

This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: L/S sensitivity ratio[15:8]

0xC452 LS_SENS_RATIO_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-21

table 4-6 AEC target/range control registers (sheet 7 of 18)

default
address register name value R/W description
Bit[7:0]: L/S sensitivity ratio[7:0]

0xC453 LS_SENS_RATIO_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:1]: Not used

Bit[0]: Non-HDR mode
0: Disable
1: Enable
0xC454 NONHDR_EN – RW
When register value is 0x00, it means function is
C

disabled; all other values mean function is

enabled. This register value must be initialized
on ac

by user and must not be removed from start up

sequence. Default value is random.

Bit[7:1]: Not used

Bit[0]: Fixed ratio mode
W
fid in

0: Disable
1: Enable
0xC456 FIXED_RATIO_EN – RW
When register value is 0x00, it means function is
en g o

disabled; all other values mean function is

enabled. This register value must be initialized
h

by user and must not be removed from start up

sequence. Default value is random.
tia nly

Bit[7:1]: Not used

Bit[0]: Geometric proportion mode
0: Disable
lf

1: Enable
0xC457 GP_MODE_EN – RW
When register value is 0x00, it means function is
or

disabled; all other values mean function is

enabled. This register value must be initialized
by user and must not be removed from start up
sequence. Default value is random.

Bit[7:1]: Not used

Bit[0]: Night mode
0: Disable
1: Enable
0xC458 NIGHT_MODE_EN – RW
When register value is 0x00, it means function is
disabled; all other values mean function is
enabled. This register value must be initialized
by user and must not be removed from start up
sequence. Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 4-6 AEC target/range control registers (sheet 8 of 18)

default
address register name value R/W description
Bit[7:1]: Not used
Bit[0]: Only insert frame when in night
mode
0: Disable
1: Enable
0xC459 NIGHT_MODE_CTRL – RW
When register value is 0x00, it means function is
disabled; all other values mean function is
enabled. This register value must be initialized
by user and must not be removed from start up
sequence. Default value is random.
C

Bit[7:1]: Not used

Bit[0]: Allow fractal exposure
on ac

0: Disable
1: Enable
0xC45A FRACTAL_EXP_EN – RW
When register value is 0x00, it means function is
W
fid in

disabled; all other values mean function is

enabled. This register value will be automatically
initialized by sensor after powering up. Default
value is random.
en g o

Bit[7:1]: Not used

Bit[0]: Debug only
h

0xC45B NONLINEAR_GAIN_EN – RW
This register value must be initialized by user
tia nly

and must not be removed from start up

sequence. Default value is random.

Bit[7:1]: Not used

lf

Bit[0]: Manual gamma mode

0: Disable
1: Enable
or

0xC45C MANU_GAMMA_EN – RW
When register value is 0x00, it means function is
disabled; all other values mean function is
enabled. This register value must be initialized
by user and must not be removed from start up
sequence. Default value is random.

Bit[7:2]: Not used

Bit[1:0]: Light source type
00: Frequency is zero or very high
01: 60Hz
10: 50Hz
0xC45E BAND_FILTER_FLAG – RW
11: Not valid

This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-23

table 4-6 AEC target/range control registers (sheet 9 of 18)

default
address register name value R/W description
Bit[7:1]: Not used
Bit[0]: Banding filter
0: Disable
1: Enable
0xC45F BAND_FILTER_EN – RW
When register value is 0x00, it means function is
disabled; all other values mean function is
enabled. This register value must be initialized
by user and must not be removed from start up
sequence. Default value is random.

Bit[7:1]: Not used

C

Bit[0]: Short banding filter

0: Disable
on ac

1: Enable
0xC460 BAND_FILTER_SHORT – RW
When register value is 0x00, it means function is
disabled; all other values mean function is
W
fid in

enabled. This register value must be initialized

by user and must not be removed from start up
sequence. Default value is random.

Bit[7:1]: Not used

en g o

Bit[0]: Less than one band exposure mode

0: Disable
h

1: Enable
tia nly

0xC461 LESS_1BAND_EN – RW
When register value is 0x00, it means function is
disabled; all other values mean function is
enabled. This register value must be initialized
by user and must not be removed from start up
lf

sequence. Default value is random.

Bit[7:1]: Not used

or

Bit[0]: Less than one band exposure for

short
0: Disable
1: Enable
0xC462 LESS_1BAND_SHORT – RW
When register value is 0x00, it means function is
disabled; all other values mean function is
enabled. This register value must be initialized
by user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Log target 1[15:8]

0xC464 LOG_TARGET_11 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 4-6 AEC target/range control registers (sheet 10 of 18)

default
address register name value R/W description
Bit[7:0]: Log target 1[7:0]

0xC465 LOG_TARGET_12 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Log target 2[15:8]

0xC466 LOG_TARGET_21 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
C

Bit[7:0]: Log target 2[7:0]

on ac

0xC467 LOG_TARGET_22 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Log target 3[15:8]

W
fid in

0xC468 LOG_TARGET_31 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
en g o

Bit[7:0]: Log target 3[7:0]

h

0xC469 LOG_TARGET_32 – RW This register value must be initialized by user

tia nly

and must not be removed from start up

sequence. Default value is random.

Target of Raw Data for Long 1

lf

0xC46A TARGET_LONG_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
or

Target of Raw Data for Long 2

0xC46B TARGET_LONG_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Target of Raw Data for Long 3

0xC46C TARGET_LONG_3 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Target of Raw Data for Short 1

0xC46D TARGET_SHORT_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-25

table 4-6 AEC target/range control registers (sheet 11 of 18)

default
address register name value R/W description
Target of Raw Data for Short 2

0xC46E TARGET_SHORT _2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Target of Raw Data for Short 3

0xC46F TARGET_SHORT _3 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
C

Slow Range for Long Exposure

on ac

0xC470 SLOW_RANGE_LONG – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

Slow Range for Short Exposure

W
fid in

0xC471 SLOW_RANGE_SHORT – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.
en g o

Range Become Stable from Unstable

h

0xC472 STABLE_RANGE_IN – RW This register value will be automatically

tia nly

initialized by sensor after powering up. Default

value is random.

Range Become Unstable from Stable

lf

0xC473 STABLE_RANGE_OUT – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.
or

Fast AEC Adjustment Step for Long Exposure

0xC474 FAST_STEP_LONG – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

Fast AEC Adjustment Step for Short Exposure

0xC475 FAST_STEP_SHORT – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

Slow AEC Adjustment Step for Long Exposure

0xC476 SLOW_STEP_LONG – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 4-6 AEC target/range control registers (sheet 12 of 18)

default
address register name value R/W description
Slow AEC Adjustment Step for Short Exposure

0xC477 SLOW_STEP_SHORT – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

Max Fast Adjustment Ratio

0xC478 MAX_FAST_RATIO – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.
C

Max Slow Adjustment Ratio

on ac

0xC479 MAX_SLOW_RATIO – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

Bit[7:0]: Max short light exposure[31:24]

W
fid in

0xC47C MAX_SHORT_LE_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
en g o

Bit[7:0]: Max short light exposure[23:16]

h

0xC47D MAX_SHORT_LE_2 – RW This register value must be initialized by user

tia nly

and must not be removed from start up

sequence. Default value is random.

Bit[7:0]: Max short light exposure[15:8]

lf

0xC47E MAX_SHORT_LE_3 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
or

Bit[7:0]: Max short light exposure[7:0]

0xC47F MAX_SHORT_LE_4 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:2]: Not used

Bit[1:0]: Max gain for long[9:8]
0xC480 MAX _GAIN_LONG_1 – RW
This register value must be initialized by user
and must not be removed from start up
sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-27

table 4-6 AEC target/range control registers (sheet 13 of 18)

default
address register name value R/W description
Bit[7:0]: Max gain for long[7:0]

0xC481 MAX _GAIN_LONG_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:2]: Not used

Bit[1:0]: Max gain for short[9:8]
0xC482 MAX_GAIN_SHORT_1 – RW
This register value must be initialized by user
and must not be removed from start up
sequence. Default value is random.
C

Bit[7:0]: Max gain for short[7:0]

on ac

0xC483 MAX_GAIN_SHORT_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
W
fid in

Bit[7:2]: Not used

Bit[1:0]: Min gain for long[9:8]
0xC484 MIN_ GAIN_LONG_1 – RW
This register value must be initialized by user
en g o

and must not be removed from start up

sequence. Default value is random.
h

Bit[7:0]: Min gain for long[7:0]

tia nly

0xC485 MIN_ GAIN_LONG_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
lf

Bit[7:2]: Not used

Bit[1:0]: Min gain for short[9:8]
or

0xC486 MIN_GAIN_SHORT_1 – RW
This register value must be initialized by user
and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Min gain for short[7:0]

0xC487 MIN_GAIN_SHORT_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Max exposure for long[15:8]

0xC488 MAX_EXP_LONG_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 4-6 AEC target/range control registers (sheet 14 of 18)

default
address register name value R/W description
Bit[7:0]: Max exposure for long[7:0]

0xC489 MAX_EXP_LONG_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Max exposure for short[15:8]

0xC48A MAX_EXP_SHORT_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
C

Bit[7:0]: Max exposure for short[7:0]

on ac

0xC48B MAX_EXP_SHORT_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Min exposure for long[15:8]

W
fid in

0xC48C MIN_EXP_LONG_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
en g o

Bit[7:0]: Min exposure for long[7:0]

h

0xC48D MIN_EXP_LONG_2 – RW This register value must be initialized by user

tia nly

and must not be removed from start up

sequence. Default value is random.

Bit[7:0]: Min exposure for short[15:8]

lf

0xC48E MIN_EXP_SHORT_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
or

Bit[7:0]: Min exposure for short[7:0]

0xC48F MIN_EXP_ SHORT_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Fixed Ratio, Value+1

0xC490 FIXED_RATIO – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

B/A Ratio in Gp Mode

0xC492 GP_MODE_RATIO_B2A – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-29

table 4-6 AEC target/range control registers (sheet 15 of 18)

default
address register name value R/W description
C/A Ratio in Gp Mode

0xC493 GP_MODE_RATIO_C2A – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Min gamma list 1[15:8]

0xC498 MIN_GAMMA_LIST_11 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
C

Bit[7:0]: Min gamma list 1[7:0]

on ac

0xC499 MIN_GAMMA_LIST_12 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Min gamma list 2[15:8]

W
fid in

0xC49A MIN_GAMMA_LIST_21 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
en g o

Bit[7:0]: Min gamma list 2[7:0]

h

0xC49B MIN_GAMMA_LIST_22 – RW This register value must be initialized by user

tia nly

and must not be removed from start up

sequence. Default value is random.

Bit[7:0]: Min gamma list 3[15:8]

lf

0xC49C MIN_GAMMA_LIST_31 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
or

Bit[7:0]: Min gamma list 3[7:0]

0xC49D MIN_GAMMA_LIST_32 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Max gamma list 1[15:8]

0xC49E MAX_GAMMA_LIST_11 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Max gamma list 1[7:0]

0xC49F MAX_GAMMA_LIST_12 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 4-6 AEC target/range control registers (sheet 16 of 18)

default
address register name value R/W description
Bit[7:0]: Max gamma list 2[15:8]

0xC4A0 MAX_GAMMA_LIST_21 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Max gamma list 2[7:0]

0xC4A1 MAX_GAMMA_LIST_22 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
C

Bit[7:0]: Max gamma list 3[15:8]

on ac

0xC4A2 MAX_GAMMA_LIST_31 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Max gamma list 3[7:0]

W
fid in

0xC4A3 MAX_GAMMA_LIST_32 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
en g o

Bit[7:0]: Dynamic range list 1[15:8]

h

0xC4A4 DR_LIST_11 – RW This register value must be initialized by user

tia nly

and must not be removed from start up

sequence. Default value is random.

Bit[7:0]: Dynamic range list 1[7:0]

lf

0xC4A5 DR_LIST_12 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
or

Bit[7:0]: Dynamic range list 2[15:8]

0xC4A6 DR_LIST_21 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Dynamic range list 2[7:0]

0xC4A7 DR_LIST_22 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Dynamic range list 3[15:8]

0xC4A8 DR_LIST_31 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-31

table 4-6 AEC target/range control registers (sheet 17 of 18)

default
address register name value R/W description
Bit[7:0]: Dynamic range list 3[7:0]

0xC4A9 DR_LIST_32 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Band filter value for 60Hz[15:8]

0xC4AA BAND_VALUE_60HZ_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
C

Bit[7:0]: Band filter value for 60Hz[7:0]

on ac

0xC4AB BAND_VALUE_60HZ_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Band filter value for 50Hz[15:8]

W
fid in

0xC4AC BAND_VALUE_50HZ_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
en g o

Bit[7:0]: Band filter value for 50Hz[7:0]

h

0xC4AD BAND_VALUE_50HZ_2 – RW This register value must be initialized by user

tia nly

and must not be removed from start up

sequence. Default value is random.

Min Dynamic Ratio

lf

0xC4B1 MIN_DR_RATIO – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.
or

Bit[7:0]: Max dynamic ratio[15:8]

0xC4B2 MAX_DR_RATIO_1 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

Bit[7:0]: Max dynamic ratio[7:0]

0xC4B3 MAX_DR_RATIO_2 – RW This register value will be automatically

initialized by sensor after powering up. Default
value is random.

Bit[7:0]: Sensor clock ratio[15:8]

0xC514 SENSOR_CLK_RATIO_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 4-6 AEC target/range control registers (sheet 18 of 18)

default
address register name value R/W description
Bit[7:0]: Sensor clock ratio[7:0]

0xC515 SENSOR_CLK_RATIO_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: VTS[15:8]

0xC518 VTS_ADDR_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
C

Bit[7:0]: VTS[7:0]
on ac

0xC519 VTS_ADDR_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

0x5A00~
W
fid in

AEC_R – R Debug Information for AEC Control

0x5C17
en g o
h

tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-33

4.5 black level calibration (BLC)

In order to maximize the ADC range, and thus, the SNR, the OV9623 compensates for the black level of active pixels by
using optically shielded pixels. There are coarse and fine BLC calibrations that, when used together, can compensate
for very large offsets with a high degree of accuracy.

4.5.1 coarse and fine BLC

Dark current changes with temperature. At very high temperature, the dark current level may be out of the fine BLC
range. The coarse BLC cancels the majority of the dark current to make sure the remaining dark current is within the
range of the fine BLC compensation. The fine BLC then performs the final subtraction of the optically black pixels from
the active pixels.

4.5.2 trigger methods

C

Coarse BLC and fine BLC are initiated by any of the following conditions:

• image sensor soft or hard reset

on ac

• changes in either gain or exposure

• change in temperature
• change in data output format
W
fid in

BLC can also be manually triggered by setting the register 0x4003[7] from 0 to 1.
en g o

table 4-7 BLC control functions (sheet 1 of 3)

default
h

address register name value R/W description

tia nly

Bit[7:4]: Not used

Bit[3:1]: Chip debug
0x4000 BLC CTRL00 0x09 RW Bit[0]: BLC enable
lf

0: Disable
1: Enable
or

Bit[7:5]: Not used

Bit[4:0]: Start line
0x4001 START LINE 0x04 RW
Start line for calculating normal
offsets

Bit[7]: Trigger BLC when format changes

0: Change of format will not trigger
BLC
1: Change of format will trigger
BLC
Bit[6]: BLC manual mode enable
0x4002 BLC CTRL02 0xC5 RW
0: Use manual offsets for BLC
1: Use calculated offsets for BLC
Bit[5:0]: rest_frame_num
Number indicates how many frames
BLC will be updated continuously
when BLC is reset

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 4-7 BLC control functions (sheet 2 of 3)

default
address register name value R/W description
Bit[7]: BLC manual trigger
BLC will update manual_frame_num
frames continuously. Refer to register
BLC CTRL03[5:0] when this register
changes from 0 to 1
Bit[6]: BLC freeze
0x4003 BLC CTRL03 0x08 RW 0: BLC running
1: BLC freeze
Bit[5:0]: manual_frame_num
Number of frames BLC will be
updated continuously when BLC is
C

manually triggered by register BLC

CTRL03[7]
on ac

Bit[7:5]: Not used

Bit[4:0]: line_num
0x4004 LINE NUM 0x08 RW
Line number specifies black lines
used in offsets calculation
W
fid in

Bit[7:0]: Target black level for long exposure

0x4008 LONG BLC TARGET – R channel
BLC target for long exposure channel
en g o

Bit[7:0]: Target black level for short exposure

channel
0x4009 SHORT BLC TARGET – R
BLC target for short
h

exposure channel
tia nly

0x4050~ BLC Control

BLC CTRL5 – RW
0x4051 Changing these registers is not allowed
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 4-35

table 4-7 BLC control functions (sheet 3 of 3)

default
address register name value R/W description
Bit[7]: Debug control
Changing this value is not allowed
Bit[6]: BLC temperature trigger enable for
short exposure channel
0: Temperature change does not
trigger BLC
1: Temperature change triggers
BLC
Bit[5]: BLC exposure trigger enable for
short exposure channel
0: Exposure change does not
C

trigger BLC
1: Exposure change triggers BLC
Bit[4]: BLC gain trigger enable for short
on ac

exposure channel
0: Gain change does not trigger
BLC
1: Gain change triggers BLC
0x4055 BLC CTRL55 0xFF RW
W
fid in

Bit[3]: Debug control

Changing this value is not allowed
Bit[2]: BLC temperature trigger enable for
long exposure channel
en g o

0: Temperature change does not

trigger BLC
1: Temperature change triggers
h

BLC
tia nly

Bit[1]: BLC exposure trigger enable for long

exposure channel
0: Exposure change does not
trigger BLC
lf

1: Exposure change triggers BLC

Bit[0]: BLC gain trigger enable for long
exposure channel
or

0: Gain change does not trigger

BLC
1: Gain change triggers BLC

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

C
on ac
W
fid in
en g o
h

tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-1

5 image sensor processor digital functions

5.1 DSP top level control

The DSP top level control registers allow enabling and disabling of individual DSP blocks. However, the user must be
very careful as each image format requires specific blocks. Provided reference settings should always be used as a
guideline.

table 5-1 DSP top registers (sheet 1 of 2)

default
address register name value R/W description
C

Bit[7]: Color matrix enable

Bit[6]: Color interpolation enable
on ac

Bit[5]: Denoise enable

Bit[4]: white defect pixel correction
enable
0x5000 ISP RW00 0xFF RW
Bit[3]: Black defect pixel correction
W
fid in

enable
Bit[2]: AWB statistic enable
Bit[1]: AWB gain enable
Bit[0]: Lens shading correction enable
en g o

Bit[7]: Data and its weight

synchronization enable
h

Bit[6]: Black/white mode enable

Bit[5]: Dark level filter enable
tia nly

0x5001 ISP RW01 0xBF RW Bit[4]: Buffer control enable

Bit[3]: AEC enable
Bit[2]: Tone mapping enable
Bit[1]: Normalize enable
lf

Bit[0]: Long-short combination enable

Bit[7]: OTP manual offset enable

or

Bit[6]: OTP function enable

Bit[5]: Inter frame calculation
Bit[4]: CT AWB function enable
0x5002 ISP RW02 0x7E RW
Bit[3]: Digital gain enable
Bit[2]: Window border cut enable
Bit[1]: Dithering enable
Bit[0]: Chip debug

Bit[7:5]: Not used

Bit[4]: Auto window enable
0: Manually set image window
for DSP blocks
0x5004 ISP RW04 0x14 RW
1: Automatically handle image
window
Bit[3]: Not used
Bit[2:0]: Dummy line number for ISP

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 5-1 DSP top registers (sheet 2 of 2)

default
address register name value R/W description
Bit[7]: Vertical subsampling enable
0: Disable
1: Enable
Bit[6]: Lens shading correction center
option
0: Manually set by register
1: Automatically set based on
image window
Bit[5]: Output row in drop mode of
subsampling
0: First row
C

1: Second row
Bit[4]: Output column in drop mode of
subsampling
on ac

0: First pair
0x5005 ISP RW05 0x08 RW 1: Second pair
Bit[3]: Average enable in non-drop
mode of subsampling
W
fid in

0: Sum
1: Average
Bit[2]: Green/Y channel subsampling
mode
en g o

0: Non-drop
1: Drop
Bit[1]: RB/UV channel subsampling
h

mode
tia nly

0: Non-drop
1: Drop
Bit[0]: Subsampling mode enable
0: Full resolution
lf

1: Subsampling
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-3

5.2 LENC

The lens correction (LENC) algorithm compensates for the illumination drop off in the corners due to the lens. Based on
the radius of each pixel to the lens, the algorithm calculates a gain for each pixel and then corrects each pixel with the
calculated gain to compensate for the light distribution due to the lens curvature.

The LENC register settings are calculated from a lens correction tool developed by OmniVision and run with the specific
lens used on the application.

figure 5-1 LENC coefficient versus sensor gain

C

100%
on ac
LENC coefficient

W
fid in
en g o

register 0x509C/16
h

tia nly
lf

register 0x509D/E register 0x509F/A0

sensor gain
or

LENC gain is fixed by default. Register 0x5080[5] turns on the gain adaptive LENC.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 5-2 LENC control registers (sheet 1 of 3)

default
address register name value R/W description
Bit[7]: Not used
Bit[6]: Gain manual mode enable
0: Use auto gain
1: Use manual gain set by user
0x5080 LENC CTRL0 0x10 RW Bit[5]: Auto LENC switch enable
0: LENC gain is fixed
1: LENC gain adjusts according to sensor
gain
Bit[4:0]: Manual gain input

Bit[7:3]: Not used

0x5081 LENC CTRL1 0x00 RW
C

Bit[2:0]: long_red_x0[10:8]

0x5082 LENC CTRL2 0x00 RW Bit[7:0]: long_red_x0[7:0]

on ac

Bit[7:2]: Not used

0x5083 LENC CTRL3 0x00 RW
Bit[1:0]: long_red_y0[9:8]

0x5084 LENC CTRL4 0x00 RW Bit[7:0]: long_red_y0[7:0]

W
fid in

Bit[7]: Not used

0x5085 LENC CTRL5 0x00 RW
Bit[6:0]: long_red_a1

Bit[7:4]: Not used

en g o

0x5086 LENC CTRL6 0x01 RW

Bit[3:0]: long_red_a2

Bit[7]: long_red_sign
h

0x5087 LENC CTRL7 0x00 RW

Bit[6:0]: long_red_b1
tia nly

Bit[7:4]: Not used

0x5088 LENC CTRL8 0x01 RW
Bit[3:0]: long_red_b2
lf

Bit[7:3]: Not used

0x5089 LENC CTRL9 0x00 RW
Bit[2:0]: long_grn_x0[10:8]

0x508A LENC CTRL10 0x00 RW Bit[7:0]: long_grn_x0[7:0]

or

Bit[7:2]: Not used

0x508B LENC CTRL11 0x00 RW
Bit[1:0]: long_grn_y0[9:8]

0x508C LENC CTRL12 0x00 RW Bit[7:0]: long_grn_y0[7:0]

Bit[7]: Not used

0x508D LENC CTRL13 0x00 RW
Bit[6:0]: long_grn_a1

Bit[7:4]: Not used

0x508E LENC CTRL14 0x01 RW
Bit[3:0]: long_grn_a2

Bit[7]: long_grn_sign
0x508F LENC CTRL15 0x00 RW
Bit[6:0]: long_grn_b1

Bit[7:4]: Not used

0x5090 LENC CTRL16 0x01 RW
Bit[3:0]: long_grn_b2

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-5

table 5-2 LENC control registers (sheet 2 of 3)

default
address register name value R/W description
Bit[7:3]: Not used
0x5091 LENC CTRL17 0x00 RW
Bit[2:0]: long_blu_x0[10:8]

0x5092 LENC CTRL18 0x00 RW Bit[7:0]: long_blu_x0[7:0]

Bit[7:2]: Not used

0x5093 LENC CTRL19 0x00 RW
Bit[1:0]: long_blu_y0[9:8]

0x5094 LENC CTRL20 0x00 RW Bit[7:0]: long_blu_y0[7:0]

Bit[7]: Not used

0x5095 LENC CTRL21 0x00 RW
Bit[6:0]: long_blu_a1
C

Bit[7:4]: Not used

0x5096 LENC CTRL22 0x01 RW
Bit[3:0]: long_blu_a2
on ac

Bit[7]: long_blu_sign
0x5097 LENC CTRL23 0x0 RW
Bit[6:0]: long_blu_b1

Bit[7:4]: Not used

W
fid in

0x5098 LENC CTRL24 0x01 RW

Bit[3:0]: long_blu_b2

Bit[7:5]: Not used

0x509C LENC CTRL28 0x00 RW
Bit[4:0]: Min LENC gain
en g o

Bit[7:2]: Not used

0x509D LENC CTRL29 0x00 RW
Bit[1:0]: Gain threshold1[9:8] (must less than 0x200)
h

0x509E LENC CTRL30 0x00 RW Bit[7:0]: Gain threshold1[7:0]

tia nly

Bit[7:2]: Not used

0x509F LENC CTRL31 0x00 RW
Bit[1:0]: Gain threshold2[9:8] (must less than 0x200)
lf

0x50A0 LENC CTRL32 0x00 RW Bit[7:0]: Gain threshold2[7:0]

Bit[7:3]: Not used

0x50A1 LENC CTRL33 0x00 RW
Bit[2:0]: short_red_x0[10:8]
or

0x50A2 LENC CTRL34 0x00 RW Bit[7:0]: short_red_x0[7:0]

Bit[7:2]: Not used

0x50A3 LENC CTRL35 0x00 RW
Bit[1:0]: short_red_y0[9:8]

0x50A4 LENC CTRL36 0x00 RW Bit[7:0]: short_red_y0[7:0]

Bit[7]: Not used

0x50A5 LENC CTRL37 0x00 RW
Bit[6:0]: short_red_a1

Bit[7:4]: Not used

0x50A6 LENC CTRL38 0x01 RW
Bit[3:0]: short_red_a2

Bit[7]: short_red_sign
0x50A7 LENC CTRL39 0x00 RW
Bit[6:0]: short_red_b1

Bit[7:4]: Not used

0x50A8 LENC CTRL40 0x01 RW
Bit[3:0]: short_red_b2

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 5-2 LENC control registers (sheet 3 of 3)

default
address register name value R/W description
Bit[7:3]: Not used
0x50A9 LENC CTRL41 0x00 RW
Bit[2:0]: short_grn_x0[10:8]

0x50AA LENC CTRL42 0x00 RW Bit[7:0]: short_grn_x0[7:0]

Bit[7:2]: Not used

0x50AB LENC CTRL43 0x00 RW
Bit[1:0]: short_grn_y0[9:8]

0x50AC LENC CTRL44 0x00 RW Bit[7:0]: short_grn_y0[7:0]

Bit[7]: Not used

0x50AD LENC CTRL45 0x00 RW
Bit[6:0]: short_grn_a1
C

Bit[7:4]: Not used

0x50AE LENC CTRL46 0x01 RW
Bit[3:0]: short_grn_a2
on ac

Bit[7]: short_grn_sign
0x50AF LENC CTRL47 0x00 RW
Bit[6:0]: short_grn_b1

Bit[7:4]: Not used

W
fid in

0x50B0 LENC CTRL48 0x01 RW

Bit[3:0]: short_grn_b2

Bit[7:3]: Not used

0x50B1 LENC CTRL49 0x00 RW
Bit[2:0]: short_blu_x0[10:8]
en g o

0x50B2 LENC CTRL50 0x00 RW Bit[7:0]: short_blu_x0[7:0]

Bit[7:2]: Not used

h

0x50B3 LENC CTRL51 0x00 RW

Bit[1:0]: short_blu_y0[9:8]
tia nly

0x50B4 LENC CTRL52 0x00 RW Bit[7:0]: short_blu_y0[7:0]

Bit[7]: Not used

0x50B5 LENC CTRL53 0x00 RW
lf

Bit[6:0]: short_blu_a1

Bit[7:4]: Not used

0x50B6 LENC CTRL54 0x01 RW
Bit[3:0]: short_blu_a2
or

Bit[7]: short_blu_sign
0x50B7 LENC CTRL55 0x00 RW
Bit[6:0]: short_blu_b1

Bit[7:4]: Not used

0x50B8 LENC CTRL56 0x01 RW
Bit[3:0]: short_blu_b2

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-7

5.3 auto white balance (AWB)

The raw R, G, and B values of a white object detected by an image sensor vary with the spectrum of the light source.
The light source spectrum is usually described by "color temperature". The white balance process applies different gains
to each color channel to make the white object appear white in the image.

The OV9623 builds the AWB algorithm to automatically adjust the gain of each channel to achieve white balance. There
are two kinds of AWB: color Temperature (CT) based AWB and simple gray world AWB. CT AWB is based on the color
temperature of the scene, which is based on G/R and G/B ratios. Simple AWB calculates the gains based on scene
simple statistics of the final image.

For OV9623, AWB gets two sets of statistics separately from long and short channels. It can work in four modes:
separated mode, long channel mode, short channel mode and combination mode. In separated mode, the two channels
may apply different AWB gain. In other modes, they apply same AWB gain. Based on the two sets of statistics, the AWB
C

will estimate two sets of AWB gain at first. In long or short channel mode, the two channels apply one of the two sets. In
combination mode, a weighted average of the two sets of statistics is used to estimate the AWB gain. In separate mode,
on ac

the two channels will apply the two sets of AWB gain respectively.
W
fid in

table 5-3 AWB registers (sheet 1 of 2)

default
address register name value R/W description
en g o

Bit[2]: AWB statistics enable

0: Disable
h

1: Enable
0x5000 ISP RW00 0xFF RW
tia nly

Bit[1]: AWB gain enable

0: Disable
1: Enable

Bit[0]: White balance (WB) mode select

lf

0x5120 ISP_CTRL01 0x00 RW 0: Auto mode

1: Manual mode
or

Bit[0]: Select AWB algorithms

0: Select simple WB
1: Select advanced WB

0xC4B8 CT_AWB_EN – RW When register value is 0x00, it means function is

disabled; all other values mean function is
enabled. This register value must be initialized
by user and must not be removed from start up
sequence. Default value is random.

Bit[7:2]: Not used

0x5100 GAIN AWB CTRL0 0x00 RW
Bit[1:0]: manual_gain_b_long[9:8]

0x5101 GAIN AWB CTRL1 0x80 RW Bit[7:0]: manual_gain_b_long[7:0]

Bit[7:2]: Not used

0x5102 GAIN AWB CTRL2 0x00 RW
Bit[1:0]: manual_gain_gb_long[9:8]

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 5-3 AWB registers (sheet 2 of 2)

default
address register name value R/W description
0x5103 GAIN AWB CTRL3 0x80 RW Bit[7:0]: manual_gain_gb_long[7:0]

Bit[7:2]: Not used

0x5104 GAIN AWB CTRL4 0x00 RW
Bit[1:0]: manual_gain_gr_long[9:8]

0x5105 GAIN AWB CTRL5 0x80 RW Bit[7:0]: manual_gain_gr_long[7:0]

Bit[7:2]: Not used

0x5106 GAIN AWB CTRL6 0x00 RW
Bit[1:0]: manual_gain_r_long[9:8]

0x5107 GAIN AWB CTRL7 0x80 RW Bit[7:0]: manual_gain_r_long[7:0]

Bit[7:2]: Not used

C

0x5110 GAIN AWB CTRL16 0x00 RW

Bit[1:0]: manual_gain_b_short[9:8]

0x5111 GAIN AWB CTRL17 0x80 RW Bit[7:0]: manual_gain_b_short[7:0]

on ac

Bit[7:2]: Not used

0x5112 GAIN AWB CTRL18 0x00 RW
Bit[1:0]: manual_gain_gb_short[9:8]
W
fid in

0x5113 GAIN AWB CTRL19 0x80 RW Bit[7:0]: manual_gain_gb_short[7:0]

Bit[7:2]: Not used

0x5114 GAIN AWB CTRL20 0x00 RW
Bit[1:0]: manual_gain_gr_short[9:8]
en g o

0x5115 GAIN AWB CTRL21 0x80 RW Bit[7:0]: manual_gain_gr_short[7:0]

Bit[7:2]: Not used

0x5116 GAIN AWB CTRL22 0x00 RW
h

Bit[1:0]: manual_gain_r_short[9:8]
tia nly

0x5117 GAIN AWB CTRL23 0x80 RW Bit[7:0]: manual_gain_r_short[7:0]

lf

5.3.1 simple AWB

Simple AWB algorithm is based on the gray world assumption, meaning the sensor will make the R, G and B average of
or

all pixels equal to each other by adjusting the gain of each color channel.

5.3.2 CT AWB
CT AWB algorithm adjusts R, G and B gain based on the color temperature of the ambient light. It will make the R, G
and B channel average of gray pixels equal to each other by adjusting the gain of each color channel. To identify the gray
pixels over the color temperature range, the characteristics of a gray object must be calibrated first using the target lens.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-9

table 5-4 AWB long calibration registers (sheet 1 of 3)

default
address register name value R/W description
Bit[7:0]: AWB_M_RNG[7:0]
Tolerance of AWB_M_X and
AWB_M_Y in middle color temperature
range.
0x5586 AWB_M_RNG 0x10 RW
Too small of a tolerance results in
unstable AWB, while too great of a
tolerance results in inaccurate AWB.

Bit[7:0]: AWB_L_XRNG[7:0]
Tolerance of AWB_L_X in low color
C

temperature range, where AWB_L_X is

X characteristics of gray object in low
color temperature range.
on ac

0x5587 AWB_L_XRNG 0x10 RW

Too small of a tolerance results in
unstable AWB, while too great of a
tolerance results in inaccurate AWB.
W
fid in

Typical value ranges from 0x08~0x18.

Bit[7:0]: AWB_H_YRNG[7:0]
Tolerance of AWB_H_Y in low color
temperature range, where AWB_H_Y
en g o

is Y characteristics of gray object in

high color temperature range.
h

0x5588 AWB_H_YRNG 0x10 RW

Too small of a tolerance results in
tia nly

unstable AWB, while too great of a

tolerance results in inaccurate white
balance. Typical value ranges from
0x08~0x10.
lf

Bit[7:0]: AWB_M_X[7:0]
X characteristics of gray object in
or

middle color temperature range.

When AWB_M_X increases, gray will

shift toward blue in low color
temperature light, or red in high color
0x5589 AWB_M_X 0x40 RW temperature light. When AWB_M_X
decreases, gray will shift toward yellow
in low color temperature light, or cyan in
high color temperature light. If
AWB_M_X is too big or too small, AWB
algorithm may fail to identify gray object
and result is not stable and
unpredictable.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 5-4 AWB long calibration registers (sheet 2 of 3)

default
address register name value R/W description
Bit[7:0]: AWB_M_Y[7:0]
Y characteristics of gray object in
middle color temperature range.

When AWB_M_Y increases, gray will

shift toward blue in low color
temperature light, or red in high color
0x558A AWB_M_Y 0x40 RW temperature light. When AWB_M_Y
decreases, gray will shift toward yellow
in low color temperature light, or cyan in
high color temperature light. If
C

AWB_M_Y is too big or too small, AWB

algorithm will fail to identify gray object
and result is not stable and
on ac

unpredictable

Bit[7:0]: AWB_L_K
K characteristics of gray object in low
W
fid in

color temperature range

When AWB_L_K increases/decreases,

0x558B AWB_L_K 0x00 RW
gray color will slightly shift toward
en g o

yellow/blue, respectively, in low color

temperature range.
In general, AWB_L_K should be no
h

less than 0x80

tia nly

Bit[7:0]: AWB_H_K
K characteristics of gray object in high
color temperature range
lf

0x558C AWB_H_K 0x00 RW When AWB_H_K

increases/decreases, gray color will
slightly shift toward cyan/red,
or

respectively, in high color temperature

range.

Bit[7:0]: AWB_H_LMT[7:0]
Lower limit of AWB_H_X, where
AWB_H_X is X characteristics of gray
object in high color temperature range.
0x558D AWB_H_LMT 0x00 RW
Smaller AWB_H_LMT covers greater
upper limit of color temperature;
however, it also results in less accurate
white balance

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-11

table 5-4 AWB long calibration registers (sheet 3 of 3)

default
address register name value R/W description
Bit[7:0]: AWB_L_LMT[7:0]
Lower limit of AWB_L_Y, where
AWB_L_Y is Y characteristics of gray
object in low color temperature range.
0x558E AWB_L_LMT 0x00 RW
Smaller AWB_L_LMT covers smaller
lower limit of color temperature;
however, it also results in less accurate
white balance.

Bit[7:0]: AWB_DBG1
0x558F AWB_DBG1 0x20 RW Debug control register, not effective in
C

normal usage
on ac

Bit[7:0]: AWB_DBG2
0x5590 AWB_DBG2 0x20 RW Debug control register, not effective in
normal usage

Bit[7:0]: AWB_DATA_ULMT
W
fid in

Pixels with output value greater than

0x5591 AWB_DATA_ULMT 0xFF RW
AWB_DATA_ULMT are excluded in
AWB statistics
en g o

Bit[7:0]: AWB_DATA_LLMT
Pixels with output value smaller than
0x5592 AWB_DATA_LLMT 0x00 RW
AWB_DATA_LLMT are excluded in
h

AWB statistics
tia nly

table 5-5 AWB short calibration registers (sheet 1 of 4)

lf

default
or

address register name value R/W description

Bit[7:0]: AWB_M_RNG[7:0]
Tolerance of AWB_M_X and AWB_M_Y
in middle color temperature range
0x559F AWB_M_RNG 0x10 RW
Too small of a tolerance results in
unstable AWB, while too great of a
tolerance results in inaccurate AWB.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 5-5 AWB short calibration registers (sheet 2 of 4)

default
address register name value R/W description
Bit[7:0]: AWB_L_XRNG[7:0]
Tolerance of AWB_L_X in low color
temperature range, where AWB_L_X is
X characteristics of gray object in low
color temperature range.
0x55A0 AWB_L_XRNG 0x10 RW
Too small of a tolerance results in
unstable AWB, while too great of a
tolerance results in inaccurate AWB.
Typical value ranges from 0x08~0x18.

Bit[7:0]: AWB_H_YRNG[7:0]
C

Tolerance of AWB_H_Y in low color

temperature range, where AWB_H_Y is
on ac

Y characteristics of gray object in high

color temperature range.
0x55A1 AWB_H_YRNG 0x10 RW
Too small of a tolerance results in
W
fid in

unstable AWB, while too great of a

tolerance results in inaccurate white
balance. Typical value ranges from
0x08~0x10.
en g o

Bit[7:0]: AWB_M_X[7:0]
X characteristics of gray object in
h

middle color temperature range.

tia nly

When AWB_M_X increases, gray will

shift toward blue in low color
temperature light, or red in high color
0x55A2 AWB_M_X 0x40 RW temperature light. When AWB_M_X
lf

decreases, gray will shift toward yellow

in low color temperature light, or cyan in
high color temperature light. If
or

AWB_M_X is too big or too small, AWB

algorithm may fail to identify gray object
and result is not stable and
unpredictable.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-13

table 5-5 AWB short calibration registers (sheet 3 of 4)

default
address register name value R/W description
Bit[7:0]: AWB_M_Y[7:0]
Y characteristics of gray object in
middle color temperature range.

When AWB_M_Y increases, gray will

shift toward blue in low color
temperature light, or red in high color
0x55A3 AWB_M_Y 0x40 RW temperature light. When AWB_M_Y
decreases, gray will shift toward yellow
in low color temperature light, or cyan in
high color temperature light. If
C

AWB_M_Y is too big or too small, AWB

algorithm will fail to identify gray object
and result is not stable and
on ac

unpredictable

Bit[7:0]: AWB_L_K
K characteristics of gray object in low
W
fid in

color temperature range

When AWB_L_K increases/decreases,

0x55A4 AWB_L_K 0x00 RW
gray color will slightly shift toward
en g o

yellow/blue, respectively, in low color

temperature range.
In general, AWB_L_K should be no less
h

than 0x80
tia nly

Bit[7:0]: AWB_H_K
K characteristics of gray object in high
color temperature range
lf

0x55A5 AWB_H_K 0x00 RW

When AWB_H_K increases/decreases,
gray color will slightly shift toward
cyan/red, respectively, in high color
or

temperature range.

Bit[7:0]: AWB_H_LMT[7:0]
Lower limit of AWB_H_X, where
AWB_H_X is X characteristics of gray
object in high color temperature range.
0x55A6 AWB_H_LMT 0x00 RW
Smaller AWB_H_LMT covers greater
upper limit of color temperature;
however, it also results in less accurate
white balance

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 5-5 AWB short calibration registers (sheet 4 of 4)

default
address register name value R/W description
Bit[7:0]: AWB_L_LMT[7:0]
Lower limit of AWB_L_Y, where
AWB_L_Y is Y characteristics of gray
object in low color temperature range.
0x55A7 AWB_L_LMT 0x00 RW
Smaller AWB_L_LMT covers smaller
lower limit of color temperature;
however, it also results in less accurate
white balance.

Bit[7:0]: AWB_DBG1
0x55A8 AWB_DBG1 0x20 RW Debug control register, not effective in
C

normal usage
on ac

Bit[7:0]: AWB_DBG2
0x55A9 AWB_DBG2 0x20 RW Debug control register, not effective in
normal usage

Bit[7:0]: AWB_DATA_ULMT
W
fid in

Pixels with output value greater than

0x55AA AWB_DATA_ULMT 0xFF RW
AWB_DATA_ULMT are excluded in
AWB statistics
en g o

Bit[7:0]: AWB_DATA_LLMT
Pixels with output value smaller than
0x55AB AWB_DATA_LLMT 0x00 RW
AWB_DATA_LLMT are excluded in
h

AWB statistics
tia nly

5.3.3 AWB control

lf

table 5-6 AWB control registers (sheet 1 of 2)

or

default
address register name value R/W description
Bit[7:4]: Not used
Bit[3:2]: Scale of AWB_L_K and AWB_H_K for long
exposure. It is usually set to 2’b01
00: 2x
01: 4x
0x5581 AWB CT CTRL1 0x5B RW
10: 8x
11: Not allowed
Bit[1:0]: AWB debug mode
Changing these registers is not
recommended.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-15

table 5-6 AWB control registers (sheet 2 of 2)

default
address register name value R/W description
Bit[7:6]: Scale of AWB_L_K and AWB_H_K for
short exposure, it is usually set to 2’b01
00: 2x
01: 4x
10: 8x
11: Not allowed
Bit[4]: Fast adjustment enable in simple AWB
mode
0: Disable, AWB speed is slow
1: Enable, AWB adjustment is fast for
fast scene change
0x5583 AWB CT CTRL3 0x10 RW
C

Bit[3:2]: AWB statistics window selection

00: Full image
01: Exclude 8 rows and columns at each
on ac

image boundary
10: Exclude 1/8 of total rows and columns
at each image boundary
11: Exclude 1/4 of total rows and columns
W
fid in

at each image boundary

Bit[1:0]: AWB debug control
Changing these registers is not
recommended
en g o
h

5.3.4 AWB stable range and gain range

tia nly

The R, G and B gain can be further limited by register MAX_AWB_GAIN.

table 5-7 AWB range registers

lf

default
or

address register name value R/W description

Bit[7:0]: Maximum gain MSB of R/G/B channel
0xC2E6 MAX_AWB_GAIN1 – RW
This register value will be automatically initialized by
sensor after powering up. Default value is random.

Bit[7:0]: Maximum gain LSB of R/G/B channel

0xC2E7 MAX_AWB_GAIN2 – RW
This register value will be automatically initialized by
sensor after powering up. Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

5.4 de-noise (DNS)

The DNS block uses a low pass filter to remove white noise in each color channel and white noise between Gb and Gr.
Control parameters are separated for long and short exposures. A difference below the threshold is treated as noise and
will be smoothed. A difference above the threshold is treated as an edge and will be preserved. The low pass filter is
adaptive to the gain value.

figure 5-2 RAW domain DNS - long

{0x522E, 0x522F}

0x5220
C

{0x522C, 0x522D}
long
on ac

0x521f
threshold

{0x522A, 0x522B}

0x521e
W
fid in

0x521D

0x521C
0x521B {0x5228,
en g o

0x521A 0x5229}
{0x5226,
0x5227}
h

{0x5224,
{0x5222, 0x5225}
tia nly

0x5223}

1x 2x 4x 8x 16x 32x 64x

gain
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-17

figure 5-3 RAW domain DNS - short

{0x5255, 0x5256}

0x5248

{0x5253, 0x5254}
short

0x5247
threshold

{0x5251, 0x5252}

0x5246
0x5245

0x5244
C

0x5243 {0x524F,
0x5242 0x5250}
on ac

{0x524D,
{0x524B, 0x524E}
{0x5249, 0x524C}
0x524A}
W
fid in

1x 2x 4x 8x 16x 32x 64x

gain
en g o
h

table 5-8 DNS control registers (sheet 1 of 4)

tia nly

default
address register name value R/W description
lf

0x5000 ISP RW00 0xFF RW Bit[5]: dns_en

Bit[7:4]: Not used

0x5210 DNS CTRL10 0x04 RW
Bit[3:0]: noise_y_a for long exposure sub-pixel
or

Bit[7:5]: Not used

0x5211 DNS CTRL11 0x08 RW
Bit[4:0]: noise_uv_a for long exposure sub-pixel

Bit[7:1]: Not used

0x5212 DNS CTRL12 0x00 RW
Bit[0]: dns_manual for long exposure sub-pixel

0x5213 DNS CTRL13 0x02 RW Bit[7:0]: noise_y for long exposure sub-pixel

Bit[7:1]: Not used

0x5214 DNS CTRL14 0x00 RW
Bit[0]: noise_u[8] for long exposure sub-pixel

0x5215 DNS CTRL15 0x02 RW Bit[7:0]: noise_u[7:0] for long exposure sub-pixel

Bit[7:1]: Not used

0x5216 DNS CTRL16 0x00 RW
Bit[0]: noise_v[8] for long exposure sub-pixel

0x5217 DNS CTRL17 0x02 RW Bit[7:0]: noise_v[7:0] for long exposure sub-pixel

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 5-8 DNS control registers (sheet 2 of 4)

default
address register name value R/W description
0x5218 DNS CTRL18 0x06 RW Bit[7:0]: dns_edgethre for long exposure sub-pixel

Bit[7:4]: Not used

0x5219 DNS CTRL19 0x04 RW Bit[3]: Reserved
Bit[2:0]: dns_gbgr_extra[2:0] for long exposure sub-pixel

0x521A DNS CTRL20 0x02 RW Bit[7:0]: noise_y_list_0 for long exposure sub-pixel

0x521B DNS CTRL21 0x04 RW Bit[7:0]: noise_y_list_1 for long exposure sub-pixel

0x521C DNS CTRL22 0x08 RW Bit[7:0]: noise_y_list_2 for long exposure sub-pixel

0x521D DNS CTRL23 0x14 RW Bit[7:0]: noise_y_list_3 for long exposure sub-pixel
C

0x521E DNS CTRL24 0x1E RW Bit[7:0]: noise_y_list_4 for long exposure sub-pixel
on ac

0x521F DNS CTRL25 0x28 RW Bit[7:0]: noise_y_list_5 for long exposure sub-pixel

0x5220 DNS CTRL26 0x32 RW Bit[7:0]: noise_y_list_6_l for long exposure sub-pixel

Bit[7:1]: Not used

W
fid in

0x5222 DNS CTRL28 0x00 RW

Bit[0]: noise_uv_list_0[8] for long exposure sub-pixel

0x5223 DNS CTRL29 0x02 RW Bit[7:0]: noise_uv_list_0[7:0] for long exposure sub-pixel
en g o

Bit[7:1]: Not used

0x5224 DNS CTRL30 0x00 RW
Bit[0]: noise_uv_list_1[8] for long exposure sub-pixel
h

0x5225 DNS CTRL31 0x04 RW Bit[7:0]: noise_uv_list_1[7:0] for long exposure sub-pixel
tia nly

Bit[7:1]: Not used

0x5226 DNS CTRL32 0x00 RW
Bit[0]: noise_uv_list_2[8] for long exposure sub-pixel

0x5227 DNS CTRL33 0x0C RW Bit[7:0]: noise_uv_list_2[7:0] for long exposure sub-pixel
lf

Bit[7:1]: Not used

0x5228 DNS CTRL34 0x00 RW
Bit[0]: noise_uv_list_3[8] for long exposure sub-pixel
or

0x5229 DNS CTRL35 0x28 RW Bit[7:0]: noise_uv_list_3[7:0] for long exposure sub-pixel

Bit[7:1]: Not used

0x522A DNS CTRL36 0x00 RW
Bit[0]: noise_uv_list_4[8] for long exposure sub-pixel

0x522B DNS CTRL37 0x32 RW Bit[7:0]: noise_uv_list_4[7:0] for long exposure sub-pixel

Bit[7:1]: Not used

0x522C DNS CTRL38 0x00 RW
Bit[0]: noise_uv_list_5[8] for long exposure sub-pixel

0x522D DNS CTRL39 0x3C RW Bit[7:0]: noise_uv_list_5[7:0] for long exposure sub-pixel

Bit[7:1]: Not used

0x522E DNS CTRL40 0x00 RW
Bit[0]: noise_uv_list_6[8] for long exposure sub-pixel

0x522F DNS CTRL41 0x4C RW Bit[7:0]: noise_uv_list_6[7:0] for long exposure sub-pixel

Bit[7:4]: Not used

0x5238 DNS CTRL50 0x04 RW
Bit[3:0]: noise_y_a for short exposure sub-pixel

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-19

table 5-8 DNS control registers (sheet 3 of 4)

default
address register name value R/W description
Bit[7:5]: Not used
0x5239 DNS CTRL51 0x08 RW
Bit[4:0]: noise_uv_a for short exposure sub-pixel

Bit[7:1]: Not used

0x523A DNS CTRL52 0x00 RW
Bit[0]: dns_manual for short exposure sub-pixel

0x523B DNS CTRL53 0x02 RW Bit[7:0]: noise_y for short exposure sub-pixel

Bit[7:1]: Not used

0x523C DNS CTRL54 0x00 RW
Bit[0]: noise_u[8] for short exposure sub-pixel

0x523D DNS CTRL55 0x02 RW Bit[7:0]: noise_u[7:0] for short exposure sub-pixel
C

Bit[7:1]: Not used

0x523E DNS CTRL56 0x00 RW
Bit[0]: noise_v[8] for short exposure sub-pixel
on ac

0x523F DNS CTRL57 0x02 RW Bit[7:0]: noise_v[7:0] for short exposure sub-pixel

0x5240 DNS CTRL58 0x06 RW Bit[7:0]: dns_edgethre for short exposure sub-pixel
W
fid in

Bit[7:4]: Not used

0x5241 DNS CTRL59 0x04 RW Bit[3]: Reserved
Bit[2:0]: dns_gbgr_extra[2:0] for short exposure sub-pixel

0x5242 DNS CTRL60 0x02 RW Bit[7:0]: noise_y_list_0 for short exposure sub-pixel
en g o

0x5243 DNS CTRL61 0x04 RW Bit[7:0]: noise_y_list_1 for short exposure sub-pixel
h

0x5244 DNS CTRL62 0x08 RW Bit[7:0]: noise_y_list_2 for short exposure sub-pixel
tia nly

0x5245 DNS CTRL63 0x14 RW Bit[7:0]: noise_y_list_3 for short exposure sub-pixel

0x5246 DNS CTRL64 0x1E RW Bit[7:0]: noise_y_list_4 for short exposure sub-pixel
lf

0x5247 DNS CTRL65 0x28 RW Bit[7:0]: noise_y_list_5 for short exposure sub-pixel

0x5248 DNS CTRL66 0x32 RW Bit[7:0]: noise_y_list_6 for short exposure sub-pixel
or

Bit[7:1]: Not used

0x5249 DNS CTRL67 0x00 RW
Bit[0]: noise_uv_list_0[8] for short exposure sub-pixel

0x524A DNS CTRL68 0x02 RW Bit[7:0]: noise_uv_list_0[7:0] for short exposure sub-pixel

Bit[7:1]: Not used

0x524B DNS CTRL69 0x00 RW
Bit[0]: noise_uv_list_1[8] for short exposure sub-pixel

0x524C DNS CTRL70 0x04 RW Bit[7:0]: noise_uv_list_1[7:0] for short exposure sub-pixel

Bit[7:1]: Not used

0x524D DNS CTRL71 0x00 RW
Bit[0]: noise_uv_list_2[8] for short exposure sub-pixel

0x524E DNS CTRL72 0x0C RW Bit[7:0]: noise_uv_list_2[7:0] for short exposure sub-pixel

Bit[7:1]: Not used

0x524F DNS CTRL73 0x00 RW
Bit[0]: noise_uv_list_3[8] for short exposure sub-pixel

0x5250 DNS CTRL74 0x28 RW Bit[7:0]: noise_uv_list_3[7:0] for short exposure sub-pixel

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 5-8 DNS control registers (sheet 4 of 4)

default
address register name value R/W description
Bit[7:1]: Not used
0x5251 DNS CTRL75 0x00 RW
Bit[0]: noise_uv_list_4[8] for short exposure sub-pixel

0x5252 DNS CTRL76 0x32 RW Bit[7:0]: noise_uv_list_4[7:0] for short exposure sub-pixel

Bit[7:1]: Not used

0x5253 DNS CTRL77 0x00 RW
Bit[0]: noise_uv_list_5[8] for short exposure sub-pixel

0x5254 DNS CTRL78 0x3C RW Bit[7:0]: noise_uv_list_5[7:0] for short exposure sub-pixel

Bit[7:1]: Not used

0x5255 DNS CTRLl79 0x00 RW
Bit[0]: noise_uv_list_6[8] for short exposure sub-pixel
C

0x5256 DNS CTRLl80 0x4C RW Bit[7:0]: noise_uv_list_6[7:0] for short exposure sub-pixel
on ac

5.5 color interpolation (CIP)

W
fid in

CIP block interpolates raw R,G,B pixels to RGB space. It also contains the sharpen function.

figure 5-4 CIP sharpen curve

en g o

LONG SHORT
h

Reg. 0x528d Reg. 0x52cd

nMaxSharpen nMaxSharpen
tia nly
sharpen amount

sharpen amount

lf

Reg. 0x528c Reg. 0x52cc

nMinSharpen nMinSharpen
or

Reg. {0x5280, 0x5281} Reg. {0x5282, 0x5283} Reg. {0x52c0, 0x52c1} Reg. {0x52c2, 0x52c3}

gain gain

table 5-9 CIP control registers (sheet 1 of 6)

default
address register name value R/W description
0x5000 ISP RW00 1'b1 RW Bit[6]: cip_en

Bit[1:0]: min_gain[9:8] for long exposure

0x5280 CIP CTRL00 0x00 RW Min_gain is used in CIP_start module and is used
to judge in which range current sensor is in

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-21

table 5-9 CIP control registers (sheet 2 of 6)

default
address register name value R/W description
Bit[7:0]: min_gain[7:0] for long exposure
0x5281 CIP CTRL01 0x10 RW Min_gain is used in CIP_start module and is used
to judge in which range current sensor is in

Bit[1:0]: max_gain[9:8] for long exposure

0x5282 CIP CTRL02 0x00 RW Max_gain is used in CIP_start module and is
used to judge in which range current sensor is in

Bit[7:0]: max_gain[7:0] for long exposure

0x5283 CIP CTRL03 0x80 RW Max_gain is used in CIP_start module and is
used to judge in which range current sensor is in
C

Bit[0]: min_noise[8] for long exposure

0x5284 CIP CTRL04 0x00 RW Min_noise is used for calculating int_noise in
auto mode
on ac

Bit[7:0]: min_noise[7:0] for long exposure

0x5285 CIP CTRL05 0x10 RW Min_noise is used for calculating int_noise in
auto mode
W
fid in

Bit[1:0]: noise_slope[9:8] for long exposure

0x5286 CIP CTRL06 0x01 RW Slope value used for calculating int_noise in auto
mode
en g o

Bit[7:0]: noise_slope[7:0] for long exposure

0x5287 CIP CTRL07 0x00 RW Slope value used for calculating int_noise in auto
mode
h

tia nly

Bit[7:0]: unsharpen_mask0 for long exposure

0x5288 CIP CTRL08 0x10 RW UnSharpenMask0 used in some filters as
multipliers

Bit[7:0]: unsharpen_mask1 for long exposure

lf

0x5289 CIP CTRL09 0x30 RW UnSharpenMask0 used in some filters as

multipliers
or

Bit[1]: man_en for long exposure

Enable manual mode
0x528A CIP CTRL0A 0x10 RW
Bit[0]: anti_aliasing for long exposure
Enable anti-aliasing

Bit[3:0]: combine_alpha[3:0] for long exposure

0x528B CIP CTRL0B 0x02 RW
Combine coefficients for U, V and H components

Bit[4:0]: min_sharpen[4:0] for long exposure

0x528C CIP CTRL0C 0x00 RW Min_sharpen is used for sharpen_p calculation in
auto mode

Bit[5:0]: max_sharpen[5:0] for long exposure

0x528D CIP CTRL0D 0x10 RW Max_sharpen is used for sharpen_p calculation
in auto mode

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 5-9 CIP control registers (sheet 3 of 6)

default
address register name value R/W description
Bit[5:0]: min_sharpen_tp[5:0] for long exposure
0x528E CIP CTRL0E 0x10 RW Min_sharpen_tp is used for sharpen_tp
computation in auto mode

Bit[7:0]: max_sharpen_tp[7:0] for long exposure

0x528F CIP CTRL0F 0x60 RW Max_sharpen_tp is used for sharpen_tp
calculation in auto mode

Bit[5:0]: min_sharpen_tm[5:0] for long exposure

0x5290 CIP CTRL10 0x20 RW Min_sharpen_tm is used for sharpen_tm
calculation in auto mode
C

Bit[7:0]: max_sharpen_tm[7:0] for long exposure

0x5291 CIP CTRL11 0x60 RW Max_sharpen_tm is used for sharpen_tm
calculation in auto mode
on ac

Bit[7:0]: sharpen_tya[7:0] for long exposure

0x5292 CIP CTRL12 0x40 RW
Threshold used for function of adaptive sharpen

Bit[4:0]: sharpen_alpha[4:0] for long exposure

W
fid in

0x5293 CIP CTRL13 0x10 RW Sharpen_alpha is used for calculating

sharpen_m after sharpen_p is obtained

Bit[5:0]: mthre[5:0] for long exposure

en g o

0x5294 CIP CTRL14 0x06 RW

Threshold for medium frequency signals

Bit[5:0]: hthre[5:0] for long exposure

h

0x5295 CIP CTRL15 0x08 RW

Threshold for high frequency signals
tia nly

Bit[3:0]: hfreq_coef[3:0] for long exposure

0x5297 CIP CTRL17 0x06 RW
Coefficients for high frequency signals

Bit[1:0]: efreq_coef[1:0] for long exposure

lf

0x5298 CIP CTRL18 0x00 RW

Coefficients for E frequency signals

Bit[5:0]: lthre[5:0] for long exposure

0x5299 CIP CTRL19 0x08 RW
or

Threshold for low frequency signals

Bit[1:0]: man_int_noise[9:8] for long exposure

0x529A CIP CTRL1A 0x00 RW Int_noise is input only in manual mode and is
used as threshold in some filters

Bit[7:0]: man_int_noise[7:0] for long exposure

0x529B CIP CTRL1B 0x30 RW Int_noise is input only in manual mode and is
used as threshold in some filters

Bit[0]: man_inv_noise[8] for long exposure

0x529C CIP CTRL1C 0x00 RW Inv_noise is input only in manual mode and is
used as threshold in some filters

Bit[7:0]: man_inv_noise[7:0] for long exposure

0x529D CIP CTRL1D 0x55 RW Inv_noise is input only in manual mode and is
used as threshold in some filters

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-23

table 5-9 CIP control registers (sheet 4 of 6)

default
address register name value R/W description
Bit[5:0]: man_sharpen_p[5:0] for long exposure
0x529E CIP CTRL1E 0x08 RW Sharpen_p is input only in manual mode and is
used for function of adaptive sharpen

Bit[6:0]: man_sharpen_m[6:0] for long exposure

0x529F CIP CTRL1F 0x08 RW Sharpen_m is input only in manual mode and is
used for function of adaptive sharpen

Bit[7:0]: man_sharpen_tp[7:0] for long exposure

0x52A0 CIP CTRL20 0x06 RW Sharpen_tp is input only in manual mode and is
used for function of adaptive sharpen
C

Bit[7:0]: man_sharpen_tm[7:0] for long exposure

0x52A1 CIP CTRL21 0x08 RW Sharpen_tm is input only in manual mode and is
used for function of adaptive sharpen
on ac

Bit[1:0]: min_gain[9:8] for short exposure

0x52C0 CIP CTRL40 0x00 RW Min_gain is used in CIP_start module and is used
to judge in which range current sensor is in
W
fid in

Bit[7:0]: min_gain[7:0] for short exposure

0x52C1 CIP CTRL41 0x10 RW Min_gain is used in CIP_start module and is used
to judge in which range current sensor is in
en g o

Bit[1:0]: max_gain[9:8] for short exposure

0x52C2 CIP CTRL42 0x00 RW Max_gain is used in CIP_start module and is
used to judge in which range current sensor is in
h

tia nly

Bit[7:0]: max_gain[7:0] for short exposure

0x52C3 CIP CTRL43 0x80 RW Max_gain is used in CIP_start module and is
used to judge in which range current sensor is in

Bit[0]: min_noise[8] for short exposure

lf

0x52C4 CIP CTRL44 0x00 RW Min_noise used for calculating int_noise in auto
mode
or

Bit[7:0]: min_noise[7:0] for short exposure

0x52C5 CIP CTRL45 0x10 RW Min_noise used for calculating int_noise in auto
mode

Bit[1:0]: noise_slope[9:8] for short exposure

0x52C6 CIP CTRL46 0x01 RW Slope value used for calculating int_noise in auto
mode

Bit[7:0]: noise_slope[7:0] for short exposure

0x52C7 CIP CTRL47 0x00 RW Slope value used for calculating int_noise in auto
mode

Bit[7:0]: unsharpen_mask0 for short exposure

0x52C8 CIP CTRL48 0x10 RW UnSharpenMask0 used in some filters as
multipliers

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 5-9 CIP control registers (sheet 5 of 6)

default
address register name value R/W description
Bit[7:0]: unsharpen_mask1 for short exposure
0x52C9 CIP CTRL49 0x30 RW UnSharpenMask0 used in some filters as
multipliers

Bit[1]: man_en for short exposure

Enable manual mode
0x52CA CIP CTRL4A 0x01 RW
Bit[0]: anti_aliasing for short exposure
Enable anti-aliasing

Bit[3:0]: combine_alpha[3:0] for short exposure

0x52CB CIP CTRL4B 0x02 RW
Combine coefficients for U, V and H components
C

Bit[4:0]: min_sharpen[4:0] for short exposure

0x52CC CIP CTRL4C 0x00 RW Min_sharpen is used for sharpen_p calculation in
auto mode
on ac

Bit[5:0]: max_sharpen[5:0] for short exposure

0x52CD CIP CTRL4D 0x00 RW Max_sharpen is used for sharpen_p calculation
in auto mode
W
fid in

Bit[5:0]: min_sharpen_tp[5:0] for short exposure

0x52CE CIP CTRL4E 0x10 RW Min_sharpen_tp is used for sharpen_tp
calculation in auto mode
en g o

Bit[7:0]: max_sharpen_tp[7:0] for short exposure

0x52CF CIP CTRL4F 0x60 RW Max_sharpen_tp is used for sharpen_tp
calculation in auto mode
h

tia nly

Bit[5:0]: min_sharpen_tm[5:0] for short exposure

0x52D0 CIP CTRL50 0x20 RW Min_sharpen_tm is used for sharpen_tm
calculation in auto mode

Bit[7:0]: max_sharpen_tm[7:0] for short exposure

lf

0x52D1 CIP CTRL51 0x60 RW Max_sharpen_tm is used for sharpen_tm

calculation in auto mode
or

Bit[7:0]: sharpen_tya[7:0] for short exposure

0x52D2 CIP CTRL52 0x40 RW
Threshold used for function of adaptive sharpen

Bit[4:0]: sharpen_alpha[4:0] for short exposure

0x52D3 CIP CTRL53 0x10 RW Sharpen_alpha is used for calculating
sharpen_m after sharpen_p is obtained

Bit[5:0]: mthre[5:0] for short exposure

0x52D4 CIP CTRL54 0x06 RW
Threshold for medium frequency signals

Bit[5:0]: hthre[5:0] for short exposure

0x52D5 CIP CTRL55 0x08 RW
Threshold for high frequency signals

Bit[3:0]: hfreq_coef[3:0] for short exposure

0x52D7 CIP CTRL57 0x06 RW
Coefficients for high frequency signals

Bit[1:0]: efreq_coef[1:0] for short exposure

0x52D8 CIP CTRL58 0x00 RW
Coefficients for E frequency signals

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-25

table 5-9 CIP control registers (sheet 6 of 6)

default
address register name value R/W description
Bit[5:0]: lthre[5:0] for short exposure
0x52D9 CIP CTRL59 0x08 RW
Threshold for low frequency signals

Bit[1:0]: man_int_noise[9:8] for short exposure

0x52DA CIP CTRL5A 0x00 RW Int_noise is input only in manual mode and is
used as threshold in some filters

Bit[7:0]: man_int_noise[7:0] for short exposure

0x52DB CIP CTRL5B 0x30 RW Int_noise is input only in manual mode and is
used as threshold in some filters

Bit[0]: man_inv_noise[8] for short exposure

C

0x52DC CIP CTRL5C 0x00 RW Inv_noise is input only in manual mode and is
used as threshold in some filters
on ac

Bit[7:0]: man_inv_noise[7:0] for short exposure

0x52DD CIP CTRL5D 0x55 RW Inv_noise is input only in manual mode and is
used as threshold in some filters

Bit[5:0]: man_sharpen_p[5:0] for short exposure

W
fid in

0x52DE CIP CTRL5E 0x08 RW Sharpen_p is input only in manual mode and is
used for function of adaptive sharpen

Bit[6:0]: man_sharpen_m[6:0] for short exposure

en g o

0x52DF CIP CTRL5F 0x08 RW Sharpen_m is input only in manual mode and is
used for function of adaptive sharpen
h

Bit[7:0]: man_sharpen_tp[7:0] for short exposure

tia nly

0x52E0 CIP CTRL60 0x06 RW Sharpen_tp is input only in manual mode and is
used for function of adaptive sharpen

Bit[7:0]: man_sharpen_tm[7:0] for short exposure

0x52E1 CIP CTRL61 0x08 RW Sharpen_tm is input only in manual mode and is
lf

used for function of adaptive sharpen

or

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

5.6 color matrix (CMX)

The main purpose of color matrix (CMX) is color correction. There is generally no need to change these register values.

{0xC318, 0xC319} {0xC31A, 0xC31B} {0xC31C, 0xC31D} 0.114 0.587 0.299

{0xC31E, 0xC31F} {0xC320, 0xC321} {0xC322, 0xC323} 0.5 -0.331 -0.169
=256 x x [CCM] long
{0xC324, 0xC325} {0xC326, 0xC327} {0xC328, 0xC329} -0.056 0.278 -0.222
{0xC32A, 0xC32B} {0xC32C,0xC32D} {0xC32E, 0xC32F} -0.081 -0.419 0.5

{0xC330, 0xC331} {0xC332, 0xC333} {0xC334, 0xC335} 0.114 0.587 0.299

{0xC336, 0xC337} {0xC338, 0xC339} {0xC33A, 0xC33B} 0.5 -0.331 -0.169 x [CCM] short
=256 x
{0xC33C, 0xC33D} {0xC33E, 0xC33F} {0xC340, 0xC341} -0.056 -0.278 -0.222
{0xC342, 0xC343} {0xC344, 0xC345} {0xC346, 0xC347} -0.081 -0.419 0.5
C
on ac

table 5-10 CMX control registers (sheet 1 of 6)

default
address register name value R/W description
W
fid in

Bit[7]: cmx_en
0x5000 ISP CTRL00 0x01 RW 0: Disable CMX
1: Enable CMX
en g o

Bit[7:0]: Long color matrix 1[15:8]

h

0xC318 COLOR_MATRIX_L_1_1 – RW This register value must be initialized by

user and must not be removed from start
tia nly

up sequence. Default value is random.

Bit[7:0]: Long color matrix 1[7:0]

lf

0xC319 COLOR_MATRIX_L_1_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.
or

Bit[7:0]: Long color matrix 2[15:8]

0xC31A COLOR_MATRIX_L_2_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Long color matrix 2[7:0]

0xC31B COLOR_MATRIX_L_2_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Long color matrix 3[15:8]

0xC31C COLOR_MATRIX_L_3_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-27

table 5-10 CMX control registers (sheet 2 of 6)

default
address register name value R/W description
Bit[7:0]: Long color matrix 3[7:0]

0xC31D COLOR_MATRIX_L_3_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Long color matrix 4[15:8]

0xC31E COLOR_MATRIX_L_4_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.
C

Bit[7:0]: Long color matrix 4[7:0]

on ac

0xC31F COLOR_MATRIX_L_4_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Long color matrix 5[15:8]

W
fid in

0xC320 COLOR_MATRIX_L_5_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.
en g o

Bit[7:0]: Long color matrix 5[7:0]

h

0xC321 COLOR_MATRIX_L_5_2 – RW This register value must be initialized by

tia nly

user and must not be removed from start

up sequence. Default value is random.

Bit[7:0]: Long color matrix 6[15:8]

lf

0xC322 COLOR_MATRIX_L_6_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.
or

Bit[7:0]: Long color matrix 6[7:0]

0xC323 COLOR_MATRIX_L_6_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Long color matrix 7[15:8]

0xC324 COLOR_MATRIX_L_7_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Long color matrix 7[7:0]

0xC325 COLOR_MATRIX_L_7_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 5-10 CMX control registers (sheet 3 of 6)

default
address register name value R/W description
Bit[7:0]: Long color matrix 8[15:8]

0xC326 COLOR_MATRIX_L_8_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Long color matrix 8[7:0]

0xC327 COLOR_MATRIX_L_8_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.
C

Bit[7:0]: Long color matrix 9[15:8]

on ac

0xC328 COLOR_MATRIX_L_9_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Long color matrix 9[7:0]

W
fid in

0xC329 COLOR_MATRIX_L_9_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.
en g o

Bit[7:0]: Long color matrix 10[15:8]

h

0xC32A COLOR_MATRIX_L_10_1 – RW This register value must be initialized by

tia nly

user and must not be removed from start

up sequence. Default value is random.

Bit[7:0]: Long color matrix 10[7:0]

lf

0xC32B COLOR_MATRIX_L_10_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.
or

Bit[7:0]: Long color matrix 11[15:8]

0xC32C COLOR_MATRIX_L_11_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Long color matrix 11[7:0]

0xC32D COLOR_MATRIX_L_11_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Long color matrix 12[15:8]

0xC32E COLOR_MATRIX_L_12_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-29

table 5-10 CMX control registers (sheet 4 of 6)

default
address register name value R/W description
Bit[7:0]: Long color matrix 12[7:0]

0xC32F COLOR_MATRIX_L_12_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Short color matrix 1[15:8]

0xC330 COLOR_MATRIX_S_1_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.
C

Bit[7:0]: Short color matrix 1[7:0]

on ac

0xC331 COLOR_MATRIX_S_1_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Short color matrix 2[15:8]

W
fid in

0xC332 COLOR_MATRIX_S_2_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.
en g o

Bit[7:0]: Short color matrix 2[7:0]

h

0xC333 COLOR_MATRIX_S_2_2 – RW This register value must be initialized by

tia nly

user and must not be removed from start

up sequence. Default value is random.

Bit[7:0]: Short color matrix 3[15:8]

lf

0xC334 COLOR_MATRIX_S_3_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.
or

Bit[7:0]: Short color matrix 3[7:0]

0xC335 COLOR_MATRIX_S_3_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Short color matrix 4[15:8]

0xC336 COLOR_MATRIX_S_4_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Short color matrix 4[7:0]

0xC337 COLOR_MATRIX_S_4_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 5-10 CMX control registers (sheet 5 of 6)

default
address register name value R/W description
Bit[7:0]: Short color matrix 5[15:8]

0xC338 COLOR_MATRIX_S_5_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Short color matrix 5[7:0]

0xC339 COLOR_MATRIX_S_5_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.
C

Bit[7:0]: Short color matrix 6[15:8]

on ac

0xC33A COLOR_MATRIX_S_6_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Short color matrix 6[7:0]

W
fid in

0xC33B COLOR_MATRIX_S_6_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.
en g o

Bit[7:0]: Short color matrix 7[15:8]

h

0xC33C COLOR_MATRIX_S_7_1 – RW This register value must be initialized by

tia nly

user and must not be removed from start

up sequence. Default value is random.

Bit[7:0]: Short color matrix 7[7:0]

lf

0xC33D COLOR_MATRIX_S_7_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.
or

Bit[7:0]: Short color matrix 8[15:8]

0xC33E COLOR_MATRIX_S_8_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Short color matrix 8[7:0]

0xC33F COLOR_MATRIX_S_8_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Short color matrix 9[15:8]

0xC340 COLOR_MATRIX_S_9_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-31

table 5-10 CMX control registers (sheet 6 of 6)

default
address register name value R/W description
Bit[7:0]: Short color matrix 9[7:0]

0xC341 COLOR_MATRIX_S_9_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Short color matrix 10[15:8]

0xC342 COLOR_MATRIX_S_10_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.
C

Bit[7:0]: Short color matrix 10[7:0]

on ac

0xC343 COLOR_MATRIX_S_10_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

Bit[7:0]: Short color matrix 11[15:8]

W
fid in

0xC344 COLOR_MATRIX_S_11_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.
en g o

Bit[7:0]: Short color matrix 11[7:0]

h

0xC345 COLOR_MATRIX_S_11_2 – RW This register value must be initialized by

tia nly

user and must not be removed from start

up sequence. Default value is random.

Bit[7:0]: Short color matrix 12[15:8]

lf

0xC346 COLOR_MATRIX_S_12_1 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.
or

Bit[7:0]: Short color matrix 12[7:0]

0xC347 COLOR_MATRIX_S_12_2 – RW This register value must be initialized by

user and must not be removed from start
up sequence. Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

5.7 auto color saturation

The auto color saturation block can adjust the color saturation level based on the sensor gain. Thus, in low light, when
the gain setting is high, the color saturation can be reduced to effectively reduce spatial noise in the scene (i.e., resulting
image will lose some color saturation but will be less noisy). In bright conditions, when gain is low and noise is also
relatively low, the color saturation will be at a high level.

figure 5-5 auto color saturation graph

0x20
C
on ac
16xs

W
fid in

0xC317
en g o

MinSaturation
h

tia nly

0 0xC315 0xC316
gain
lf

table 5-11 auto color saturation control registers (sheet 1 of 2)

or

default
address register name value R/W description
Bit[1:0]: Saturation adjust enable
00: Keep previous saturation
01: Auto adjust color
saturation
10: Keep minimum saturation
0xC314 SATURATION_ADJ_EN – RW
11: Keep maximum saturation

This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-33

table 5-11 auto color saturation control registers (sheet 2 of 2)

default
address register name value R/W description
Minimum Gain To Adjust Color Saturation

0xC315 SATURATION_MINGAIN – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Maximum Gain To Adjust Color Saturation

0xC316 SATURATION_MAXGAIN – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
C

Minimum Threshold When Adjusting Color

Saturation
on ac

0xC317 SATURATION_MINTHRE – RW
This register value must be initialized by user
and must not be removed from start up
sequence. Default value is random.
W
fid in
en g o
h

tia nly
lf
or

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

5.8 combine

The purpose of the combine block is to combine the long exposure and short exposure channels into a single pixel. The
registers define the relative weight of each channel and the overlap.

table 5-12 combine control registers (sheet 1 of 5)

default
address register name value R/W description
Bit[0]: Combine enable
0x5001 ISP RW01 1'b1 RW 0: Disable
1: Enable
C

Bit[7:4]: Not used

Bit[3]: Dark boost enable
0: Dark boost disable
on ac

1: Dark boost enable

Bit[2]: combine_uv_weight enable
0: Combine without UV weight
0x5400 COMB CTRL0 0x0F RW 1: Combine with UV weight
W
fid in

Bit[1]: color_diff_compensate enable

0: Compensate disable
1: Compensate enable
Bit[0]: Compensate error enable
en g o

0: Compensate error disable

1: Compensate error enable
h

Bit[7:4]: Not used

tia nly

0x5401 COMB CTRL1 0x05 RW Bit[3:0]: comb_thre_s0

Threshold1 of short channel

Bit[7:4]: Not used

0x5402 COMB CTRL2 0x08 RW Bit[3:0]: comb_thre_s1
lf

Threshold2 of short channel

Bit[7:4]: Not used

or

0x5403 COMB CTRL3 0x0A RW Bit[3:0]: comb_thre_s2

Threshold3 of short channel

Bit[7:4]: Not used

0x5404 COMB CTRL4 0x09 RW Bit[3:0]: comb_thre_l0
Threshold1 of long channel

Bit[7:4]: Not used

0x5405 COMB CTRL5 0x0A RW Bit[3:0]: comb_thre_l1
Threshold2 of long channel

Bit[3:0]: comb_thre_l2
0x5406 COMB CTRL6 0x0A RW
Threshold3 of long channel

Bit[3:0]: comb_uv_thre_s0
0x5407 COMB CTRL7 0x05 RW
UV threshold1 of short channel

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-35

table 5-12 combine control registers (sheet 2 of 5)

default
address register name value R/W description
Bit[3:0]: comb_uv_thre_s1
0x5408 COMB CTRL8 0x08 RW
UV threshold2 of short channel

Bit[3:0]: comb_uv_thre_s2
0x5409 COMB CTRL9 0x0A RW
UV threshold3 of short channel

Bit[3:0]: comb_uv_thre_l0
0x540A COMB CTRL10 0x09 RW
UV threshold1 of long channel

Bit[3:0]: comb_uv_thre_l1
0x540B COMB CTRL11 0x0A RW
UV threshold2 of long channel

Bit[3:0]: comb_uv_thre_l2
C

0x540C COMB CTRL12 0x0A RW

UV threshold3 of long channel
on ac

0x540D COMB CTRL13 0x80 RW Bit[7:0]: comb_weight00

0x540E COMB CTRL14 0x80 RW Bit[7:0]: comb_weight01

0x540F COMB CTRL15 0x60 RW Bit[7:0]: comb_weight02

W
fid in

0x5410 COMB CTRL16 0x40 RW Bit[7:0]: comb_weight03

0x5411 COMB CTRL17 0x80 RW Bit[7:0]: comb_weight10

en g o

0x5412 COMB CTRL18 0x80 RW Bit[7:0]: comb_weight11

0x5413 COMB CTRL19 0x20 RW Bit[7:0]: comb_weight12

h

0x5414 COMB CTRL20 0x10 RW Bit[7:0]: comb_weight13

tia nly

0x5415 COMB CTRL21 0x80 RW Bit[7:0]: comb_weight20

0x5416 COMB CTRL22 0x80 RW Bit[7:0]: comb_weight21

lf

0x5417 COMB CTRL23 0x00 RW Bit[7:0]: comb_weight22

0x5418 COMB CTRL24 0x00 RW Bit[7:0]: comb_weight23

or

0x5419 COMB CTRL25 0x80 RW Bit[7:0]: comb_weight30

0x541A COMB CTRL26 0x80 RW Bit[7:0]: comb_weight31

0x541B COMB CTRL27 0x00 RW Bit[7:0]: comb_weight32

0x541C COMB CTRL28 0x00 RW Bit[7:0]: comb_weight33

0x541D COMB CTRL29 0x80 RW Bit[7:0]: comb_uv_weight00

0x541E COMB CTRL30 0x80 RW Bit[7:0]: comb_uv_weight01

0x541F COMB CTRL31 0x80 RW Bit[7:0]: comb_uv_weight02

0x5420 COMB CTRL32 0x80 RW Bit[7:0]: comb_uv_weight03

0x5421 COMB CTRL33 0x80 RW Bit[7:0]: comb_uv_weight10

0x5422 COMB CTRL34 0x80 RW Bit[7:0]: comb_uv_weight11

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 5-12 combine control registers (sheet 3 of 5)

default
address register name value R/W description
0x5423 COMB CTRL35 0x60 RW Bit[7:0]: comb_uv_weight12

0x5424 COMB CTRL36 0x40 RW Bit[7:0]: comb_uv_weight13

0x5425 COMB CTRL37 0x80 RW Bit[7:0]: comb_uv_weight20

0x5426 COMB CTRL38 0x80 RW Bit[7:0]: comb_uv_weight21

0x5427 COMB CTRL39 0x00 RW Bit[7:0]: comb_uv_weight22

0x5428 COMB CTRL40 0x00 RW Bit[7:0]: comb_uv_weight23

0x5429 COMB CTRL41 0x80 RW Bit[7:0]: comb_uv_weight30

C

0x542A COMB CTRL42 0x80 RW Bit[7:0]: comb_uv_weight31

on ac

0x542B COMB CTRL43 0x00 RW Bit[7:0]: comb_uv_weight32

0x542C COMB CTRL44 0x00 RW Bit[7:0]: comb_uv_weight33

0x542D COMB CTRL45 0x3C RW Debug Mode for Combine

W
fid in

Bit[0]: Cut black level

0: Disable
1: Enable
en g o

When register value is 0x00, it means function

0xC4B4 CUT_BL_EN – RW
is disabled; all other values mean function is
h

enabled. This register value must be

tia nly

initialized by user and must not be removed

from start up sequence. Default value is
random.

Bit[0]: Dark boost auto switch

lf

0: Disable
1: Enable
or

When register value is 0x00, it means function

0xC4B5 DARKBOOST_AUTO_EN – RW
is disabled; all other values mean function is
enabled. This register value must be
initialized by user and must not be removed
from start up sequence. Default value is
random.

Bit[0]: Auto low level

0: Disable
1: Enable

When register value is 0x00, it means function

0xC4B6 AUTO_LOW_LEVEL_EN – RW
is disabled; all other values mean function is
enabled. This register value must be
initialized by user and must not be removed
from start up sequence. Default value is
random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-37

table 5-12 combine control registers (sheet 4 of 5)

default
address register name value R/W description
Bit[7:0]: Max curve gain[15:8]

When register value is 0x00, it means function

is disabled; all other values mean function is
0xC4BC MAX_CURVE_GAIN_1 – RW
enabled. This register value must be
initialized by user and must not be removed
from start up sequence. Default value is
random.

Bit[7:0]: Max curve gain[7:0]

0xC4BD MAX_CURVE_GAIN_2 – RW This register value will be automatically

C

initialized by sensor after powering up.

Default value is random.
on ac

Bit[7:0]: Manual gamma[15:8]

0xC4BE MANUAL_GAMMA_1 – RW This register value must be initialized by user

and must not be removed from start up
W
fid in

sequence. Default value is random.

Bit[7:0]: Manual gamma[7:0]

en g o

0xC4BF MANUAL_GAMMA_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
h

tia nly

Bit[7:0]: Dark boost gain threshold 1[15:8]

0xC4C0 DB_GAIN_THRE_11 – RW This register value will be automatically

initialized by sensor after powering up.
lf

Default value is random.

Bit[7:0]: Dark boost gain threshold 1[7:0]

or

0xC4C1 DB_GAIN_THRE_12 – RW This register value will be automatically

initialized by sensor after powering up.
Default value is random.

Bit[7:0]: Dark boost gain threshold 2[15:8]

0xC4C2 DB_GAIN_THRE_21 – RW This register value will be automatically

initialized by sensor after powering up.
Default value is random.

Bit[7:0]: Dark boost gain threshold 2[7:0]

0xC4C3 DB_GAIN_THRE_22 – RW This register value will be automatically

initialized by sensor after powering up.
Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 5-12 combine control registers (sheet 5 of 5)

default
address register name value R/W description
Dark Boost Amount

0xC4C4 DB_AMT – RW This register value will be automatically

initialized by sensor after powering up.
Default value is random.

Min Dark Boost Amount

0xC4C5 DB_AMT_MIN – RW This register value will be automatically

initialized by sensor after powering up.
Default value is random.
C

Max Dark Boost Amount

on ac

0xC4C6 DB_AMT_MAX – RW This register value will be automatically

initialized by sensor after powering up.
Default value is random.

Bit[7:0]: Max dark boost gamma[15:8]

W
fid in

0xC4C8 DB_MAX_GAMMA_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
en g o

Bit[7:0]: Max dark boost gamma[7:0]

h

0xC4C9 DB_MAX_GAMMA_2 – RW This register value must be initialized by user

tia nly

and must not be removed from start up

sequence. Default value is random.

Bit[7:0]: Dark boost tone width[15:8]

lf

0xC4CA DARK_TONE_WIDTH_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
or

Bit[7:0]: Dark boost tone width[7:0]

0xC4CB DARK_TONE_WIDTH_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-39

5.9 normalize

Normalize module is designed to adjust the image contrast. Normalize supports auto and manual mode. In manual
mode, the normalize algorithm uses the manual input high level and low level. In auto mode, the algorithm will
automatically update the low level and high levels.

table 5-13 normalize control registers

default
address register name value R/W description
Bit[1]: Normalize enable
0x5001 ISP_CTRL1 1'b1 R/W 0: Disable normalize
1: Enable normalize
C

Bit[7:6]: Not used

on ac

0x5480 NORM RW00 0x21 RW Bit[5]: Debug mode

Bit[4:0]: Step

Bit[7]: Not used

0x5481 NORM RW01 0x10 RW Bit[6:0]: max_low_level
W
fid in

16 ~ 127

Bit[7:0]: min_low_level
0x5482 NORM RW02 0xF8 RW -128 to -16, complementary
en g o

code

Bit[7]: Not used

0x5483 NORM RW03 0x04 RW
h

Bit[6:0]: ps_thres[14:8]
tia nly

0x5484 NORM RW04 0x00 RW Bit[7:0]: ps_thres[7:0]

lf
or

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

5.10 tone_mapping

The tone-mapping function further adjusts the histogram and contrast.

table 5-14 tone_mapping registers (sheet 1 of 4)

default
address register name value R/W description
Bit[2]: tone_mapping enable
0x5001 ISP CTRL01 1'b1 RW 0: Disable tone_mapping
1: Enable tone_mapping

Bit[7:3]: Not used

Bit[2:0]: edge_thre
C

000: 16
001: 32
0x5500 TOMP RW00 0x03 RW
on ac

010: 64
011: 128
100: 256
101: 512
W
fid in

Bit[7:6]: Not used

Bit[5]: h_dark_en
Bit[4]: uv_dark_en
Bit[3:2]: h_dark_thre
en g o

00: 16
01: 32
h

0x5501 TOMP RW01 0x3A RW 10: 48

11: 64
tia nly

Bit[1:0]: uv_dark_thre
00: 16
01: 32
10: 48
lf

11: 64

0x5509 TOMP RW09 0x00 RW Bit[7:0]: max_dynamic_range[7:0]

or

0x550A TOMP RW10 0x00 RW Bit[7:0]: dbg_ctrl_0

0x550B TOMP RW11 0x00 RW Bit[7:0]: dbg_ctrl_1

0x550C TOMP RW12 0x00 RW Bit[7:0]: dbg_ctrl_2

Bit[7:1]: Not used

0x550D TOMP RW13 0x00 RW
Bit[0]: dbg_sram_freeze

0x550E TOMP RW14 0x00 RW Bit[7:0]: dbg_addr

Contrast Curve 1

0xC4E4 CONTRAST_CURVE_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-41

table 5-14 tone_mapping registers (sheet 2 of 4)

default
address register name value R/W description
Contrast Curve 2

0xC4E5 CONTRAST_CURVE_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Contrast Curve 3

0xC4E6 CONTRAST_CURVE_3 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
C

Contrast Curve 4
on ac

0xC4E7 CONTRAST_CURVE_4 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Contrast Curve 5
W
fid in

0xC4E8 CONTRAST_CURVE_5 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
en g o

Contrast Curve 6
h

0xC4E9 CONTRAST_CURVE_6 – RW This register value must be initialized by user

tia nly

and must not be removed from start up

sequence. Default value is random.

Contrast Curve 7
lf

0xC4EA CONTRAST_CURVE_7 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
or

Contrast Curve 8

0xC4EB CONTRAST_CURVE_8 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Contrast Curve 9

0xC4EC CONTRAST_CURVE_9 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Contrast Curve 10

0xC4ED CONTRAST_CURVE_10 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 5-14 tone_mapping registers (sheet 3 of 4)

default
address register name value R/W description
Contrast Curve 11

0xC4EE CONTRAST_CURVE_11 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Contrast Curve 12

0xC4EF CONTRAST_CURVE_12 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
C

Contrast Curve 13
on ac

0xC4F0 CONTRAST_CURVE_13 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Contrast Curve 14
W
fid in

0xC4F1 CONTRAST_CURVE_14 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
en g o

Contrast Curve 15
h

0xC4F2 CONTRAST_CURVE_15 – RW This register value must be initialized by user

tia nly

and must not be removed from start up

sequence. Default value is random.

Curve Adjustment Step

lf

0xC4F3 CURVE_STEP – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
or

Bit[7:0]: Curve min dynamic range[15:8]

0xC4F4 CURVE_MIN_DR_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Curve min dynamic range[7:0]

0xC4F5 CURVE_MIN_DR_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Curve max dynamic range[15:8]

0xC4F6 CURVE_MAX_DR_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-43

table 5-14 tone_mapping registers (sheet 4 of 4)

default
address register name value R/W description
Bit[7:0]: Curve max dynamic range[7:0]

0xC4F7 CURVE_MAX_DR_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Min Curve Alpha

0xC4F8 CURVE_MIN_ALPHA – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
C

Max Curve Alpha

on ac

0xC4F9 CURVE_MAX_ALPHA – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
W
fid in
en g o
h

tia nly
lf
or

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

5.11 windowing cropping and subsampling

table 5-15 WINC control registers

default
address register name value R/W description
Bit[2]: winc_en
0: Disable window
0x5002 ISP CTRL02 1'b1 RW cropping
1: Enable window
cropping

Bit[7]: Vertical subsampling

C

enable
0: Disable
1: Enable
on ac

Bit[6]: Lens shading correction

center option
0: Manually
1: Automatically
W
fid in

Bit[5]: Output row in drop mode

of subsampling
0: First row
1: Second row
en g o

Bit[4]: Output column in drop

mode of subsampling
0: First pair
h

1: Second pair
tia nly

0x5005 ISP RW05 0x08 RW Bit[3]: Average enable in

non-drop mode of
subsampling
0: Sum
lf

1: Average
Bit[2]: Green/Y channel
subsampling mode
or

0: Non-drop
1: Drop
Bit[1]: RB/UV channel
subsampling mode
0: Non-drop
1: Drop
Bit[0]: Subsampling mode
enable
0: Full resolution
1: Subsampling

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 5-45

5.12 defect pixel correction (DPC)

The DPC function detects the defect pixel/cluster by using a programmable threshold which can be set manually by
registers or automatically calculated based on analog gain from a programmable threshold gain curve.

5.13 group control

The OV9623 supports up to four groups. Each group can have up to 128 registers. For group operation, you must first
record the group, then write the related register values, and last, set record end.

table 5-16 group control registers

default
C

address register name value R/W description

on ac

Bit[7:6]: Operation code

00: Group record end
01: Group launch (only once)
10: Group launch (ABC mode)
11: Group record start
W
fid in

In ABC mode, group0 is for frame A,

GROUP WRITER
0x6F00 0x00 RW group1 is for frame B and group2 is
COMMAND
for frame C. Three groups launch
periodically.
en g o

Bit[5:4]: Group ID
Bit[3:2]: Chip debug
h

Bit[1:0]: Group write function enable, must be

2'b11
tia nly

0xCFF2 GROUP TABLE0H 0xDD RW Group Table0 Start Address MSB

0xCFF3 GROUP TABLE0L 0x00 RW Group Table0 Start Address LSB

lf

0xCFF6 GROUP TABLE1H 0xDD RW Group Table1 Start Address MSB

0xCFF7 GROUP TABLE1L 0x80 RW Group Table1 Start Address LSB

or

0xCFFA GROUP TABLE2H 0xDE RW Group Table2 Start Address MSB

0xCFFB GROUP TABLE2L 0x00 RW Group Table2 Start Address LSB

0xCFFE GROUP TABLE3H 0xDE RW Group Table3 Start Address MSB

0xCFFF GROUP TABLE3L 0x80 RW Group Table3 Start Address LSB

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

C
on ac
W
fid in
en g o
h

tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 6-1

6 image sensor output interface digital functions

6.1 embedded line

Embedded line contains register values. The embedded lines are prefixed to the normal image data. The line length of
the embedded line is the same as the normal image line. Embedded line only contains register values that are followed
with a 0x369 tag (10-bit) or 0xDA tag (8-bit). The 8-bit register values are output D[9:2].

There are two embedded lines. Only the last embedded line contains valid register data for each frame. The first
embedded line is a dummy line used to make an even number of lines per frame. Please refer to the Embedded Line
Application Note for details, and how to customize the embedded line.
C

table 6-1 embedded line control

default
on ac

address register name value R/W description

0x6800 EMB_LINE_EN 0x00 RW Bit[0]: emb_line enable
W
fid in

0x6801 EMB_LINE_TAG 0xDA RW Bit[7:0]: emb_line tag[9:2]

0x6802 EMB_LINE_TAG 0x01 RW Bit[1:0]: emb_line tag[1:0]

Bit[7:4]: s2h_width
en g o

0x6803 EMB_LINE_SOF_CTRL 0x11 RW

Bit[3:0]: sof_width
h

0x6804 EMB_SIZE_MANU_EN 0x00 RW Bit[0]: emb_size manual enable

tia nly

Bit[7:4]: Not used

0x6805 EMB_SIZE_MANU 0x04 RW
Bit[3:0]: emb_size[11:8]

0x6806 EMB_SIZE_MANU 0x00 RW Bit[7:0]: emb_size[7:0]

lf

0x6807 EMB_MASK_EN 0x01 RW Bit[0]: emb_line mask enable

or

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

6.2 DVP timing

figure 6-1 DVP timing diagram

(1)

VSYNC
(2) (3) (4)

(7) (5)
(7)

HREF
(6) (6)

D[9:0] invalid data

C

10-bit YUV format 10-bit long and short raw format

on ac

PCLK
PCLK
B1S[9:0] B1L[9:0] G2S[9:0] G2L[9:0]
D[9:0]
Y1[9:0] U1[9:0] Y2[9:0] V2[9:0]
W
fid in

D[9:0]
G1S[9:0] G1L[9:0] R2S[9:0] R2L[9:0]
D[9:0]

10-bit long or short raw format up to 18-bit combined raw format

en g o

PCLK PCLK

B1[9:0] G2[9:0] B3[9:0] G4[9:0] B1[9:0] B1[17:8] G2[9:0] G2[17:8]

h

D[9:0] D[9:0]
tia nly

D[9:0] G1[9:0] R2[9:0] G3[9:0] R4[9:0] D[9:0] G1[9:0] G1[17:8] R2[9:0] R2[17:8]
lf

table 6-2 DVP timing specificationsa (sheet 1 of 3)

format
or

combined long and long or

resolution parameter YUV RAW short RAW short RAW
(1) frame period 840 lines 840 lines 840 lines 840 lines

(2) VSYNC width 128.5 tp 128.5 tp 128.5 tp 257 tp

(3) VSYNC to HREF 30758.5 tp 30750.5 tp 26906.5 tp 27005 tp

1280x800 (4) line period 1905 tp 1905 tp 1905 tp 1905 tp

(5) HREF to VSYNC 45313 tp 45321 tp 49165 tp 48938 tp

(6) active pixel 1280 tp 1280 tp 1280 tp 1280 tp

(7) horizontal blanking 625 tp 625 tp 625 tp 625 tp

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 6-3

table 6-2 DVP timing specificationsa (sheet 2 of 3)

format

combined long and long or

resolution parameter YUV RAW short RAW short RAW
(1) frame period 748 lines 748 lines 748 lines 748 lines

(2) VSYNC width 128.5 tp 128.5 tp 128.5 tp 257 tp

(3) VSYNC to HREF 28760.5 tp 28752.5 tp 25154.5 tp 25223 tp

1280x720 (4) line period 1782 tp 1782 tp 1782 tp 1782 tp

(5) HREF to VSYNC 21007 tp 21015 tp 24613 tp 24416 tp

(6) active pixel 1280 tp 1280 tp 1280 tp 1280 tp

C

(7) horizontal blanking 502 tp 502 tp 502 tp 502 tp

on ac

(1) frame period 520 lines 520 lines 520 lines 520 lines

(2) VSYNC width 128.5 tp 128.5 tp 128.5 tp 257 tp

(3) VSYNC to HREF 20660.5 tp 20746.5 tp 18148.5 tp 18021tp

W
fid in

752x480 (4) line period 1282 tp 1282 tp 1282 tp 1282 tp

(5) HREF to VSYNC 30491 tp 30405 tp 33003 tp 33002 tp

en g o

(6) active pixel 752 tp 752 tp 752 tp 752 tp

(7) horizontal blanking 530 tp 530 tp 530 tp 530 tp

h

(1) frame period 520 lines 520 lines 520 lines 520 lines
tia nly

(2) VSYNC width 128.5 tp 128.5 tp 128.5 tp 257 tp

(3) VSYNC to HREF 20636.5 tp 20694.5 tp 18096.5 tp 17969 tp

lf

640x480 (4) line period 1282 tp 1282 tp 1282 tp 1282 tp

(5) HREF to VSYNC 30515 tp 30457 tp 33055 tp 33054 tp

or

(6) active pixel 640 tp 640 tp 640 tp 640 tp

(7) horizontal blanking 642 tp 642 tp 642 tp 642 tp

(1) frame period 438 lines

(2) VSYNC width 128.5 tp

(3) VSYNC to HREF 14701 tp

640x400 (4) line period 914 tp

(5) HREF to VSYNC 19902.5 tp

(6) active pixel 640 tp

(7) horizontal blanking 274 tp

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 6-2 DVP timing specificationsa (sheet 3 of 3)

format

combined long and long or

resolution parameter YUV RAW short RAW short RAW
(1) frame period 328 lines

(2) VSYNC width 128.5 tp

(3) VSYNC to HREF 9748 tp

352x288 (4) line period 618 tp

(5) HREF to VSYNC 14443.5 tp

(6) active pixel 352 tp

C

(7) horizontal blanking 256 tp

on ac

(1) frame period 280 lines

(2) VSYNC width 128.5 tp

(3) VSYNC to HREF 7040 tp

W
fid in

320x240 (4) line period 440 tp

(5) HREF to VSYNC 10431.5 tp

en g o

(6) active pixel 320 tp

(7) horizontal blanking 120 tp

h

a. These parameters change with register settings. They are different with different register settings.
tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 6-5

6.2.1 DVP setup/hold time

figure 6-2 DVP setup/hold time diagram

tCKNVSR tCKNVSF
VSYNC

tCKNHRF tCKNHRR
HREF/HSYNC

tCLKF tCLKR

PCLK
tHOLD
C

optional: qualified or continuous

on ac

D[9:0] valid valid valid invalid data valid valid

tSETUP
W
fid in

table 6-3 DVP setup/hold timeab

en g o

symbol parameter min typ max unit

tCKNVSR PCLK falling edge to VSYNC rising edge delay – 0.5 1 ns
h

tCKNVSF PCLK falling edge to VSYNC falling edge delay – 1 1.5 ns

tia nly

tCKNHRF PCLK falling edge to HREF falling edge delay – 0 1 ns

tCKNHRR PCLK falling edge to HREF rising edge delay – -0.5 0.5 ns
lf

tCLKF PCLK fall time – 1.2 2.5 ns

tCLKR PLCK rise time – 1.8 3.5 ns

or

tSETUP data setup time 3 4 – ns

tHOLD data hold time 3 5 – ns

a. measured at 2.8V DOVDD and 96 MHz PCLK, with 2x drive strength

b. timing measurement shown at beginning of rising edge and/or end of falling edge signifies 10%,
timing measurement shown in middle of rising/falling edge signifies 50%,
timing measurement shown at end of rising edge and/or beginning of falling edge signifies 90%

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

C
on ac
W
fid in
en g o
h

tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-1

7 register tables
The following table provides a description of the device control registers contained in the OV9623. The 7-bit SCCB slave
device address is 0x30. The low 3 bits come from GPIO[2:0]/SID[2:0] which is controlled by 0x300C[0].

In order to guarantee reasonable performance, the initialization register sequence must be based on the register
settings provided by OmniVision. Contact your local AE for register settings that suit your application.

7.1 system control [0x0100, 0x0103, 0x3000 ~ 0x3049]

table 7-1 system control registers (sheet 1 of 6)

C

default
address register name value R/W description
on ac

Bit[7:1]: Not used

Bit[0]: Turn on video stream after
0x0100 STREAM MODE 0x00 RW power up, always set to "1"
0: Not used
W
fid in

1: Stream on

Software Reset will Auto Clear by Itself to

0x0103 SOFTWARE RESET 0x00 RW
0x00
en g o

Bit[7:2]: Reserved
0x3000 SC_CMMN_PAD_OEN0 0x00 RW
Bit[1:0]: io_y_oen[9:8]
h

Bit[7:4]: io_y_oen[7:0]
tia nly

0x3001 SC_CMMN_PAD_OEN1 0x00 RW

Bit[3:0]: Not used

Bit[7]: io_vsync_oen
Bit[6]: io_href_oen
lf

Bit[5]: io_pclk_oen
Bit[4]: Reserved
0x3002 SC_CMMN_PAD_OEN2 0x00 RW
Bit[3]: io_strobe_oen
or

Bit[2]: io_sda_oen
Bit[1]: io_gpio1_oen
Bit[0]: io_gpio0_oen

Bit[7:6]: SCLK PLL cp[1:0]

0x3003 SC_CMMN_PLL_CTRL0 0x20 RW
Bit[5:0]: SCLK PLL multi

Bit[7]: Bypass SCLK PLL

Bit[6:4]: SCLK PLL pre div
0x3004 SC_CMMN_PLL_CTRL1 0x00 RW
Bit[3]: SCLK PLL cp[2]
Bit[2:0]: SCLK PLL sdiv

Bit[7:6]: PCLK PLL cp[1:0]

0x3005 SC_CMMN_PLL_CTRL2 0x20 RW
Bit[5:0]: PCLK PLL multi

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-1 system control registers (sheet 2 of 6)

default
address register name value R/W description
Bit[7]: Bypass PCLK PLL
Bit[6:4]: PCLK PLL pre div
0x3006 SC_CMMN_PLL_CTRL3 0x00 RW
Bit[3]: PCLK PLL cp[2]
Bit[2:0]: PCLK PLL sdiv

0x3007 SC_CMMN_PCLK_DIV_CTRL 0x01 RW Bit[7:0]: Debug mode

Bit[7:2]: Reserved
0x3008 SC_CMMN_PAD_OUT0 0x00 RW
Bit[1:0]: io_y_o[9:8]

0x3009 SC_CMMN_PAD_OUT1 0x00 RW Bit[7:0]: io_y_o[7:0]

C

0x300A PID 0xA6 R Product ID Number MSB (Read only)

0x300B VER 0x35 R Product ID Number LSB (Read only)

on ac

Bit[7:1]: SCCB ID
Bit[0]: SCCB ID select
0x300C SC_CMMN_SCCB_ID 0x60 RW
0: {sccb_id[7:4],gpio_i[3:1]}
W
fid in

1: sccb_id[7:1]

Bit[7]: io_vsync_o
Bit[6]: io_href_o
0x300D SC_CMMN_PAD_OUT2 0x00 RW
Bit[5]: io_pclk_o
en g o

Bit[4:0]: Reserved

Bit[7:2]: Reserved
h

0x300E SC_CMMN_PAD_SEL0 0x00 RW

Bit[1:0]: io_y_sel[9:8]
tia nly

0x300F SC_CMMN_PAD_SEL1 0x00 RW Bit[7:0]: io_y_sel[7:0]

Bit[7]: io_vsync_sel
Bit[6]: io_href_sel
lf

0x3010 SC_CMMN_PAD_SEL2 0x00 RW

Bit[5]: io_pclk_sel
Bit[4:0]: Reserved
or

Bit[7:6]: Pad drive strength

0x3011 SC_CMMN_PAD 0x02 RW
Bit[5:0]: Reserved

Bit[7]: Sensor gate BLC enable

Bit[6]: Sensor gate ISP enable
Bit[5]: Not used
SC_CMMN_SENSOR_GATE_
0x3012 0x00 RW Bit[4]: Sensor gate VFIFO enable
CTRL
Bit[3]: Sensor gate DVP enable
Bit[2:1]: Not used
Bit[0]: Sensor gate OTP enable

0x3016~
SC_CMMN_CTRL – RW Bit[7:0]: Debug mode
0x3019

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-3

table 7-1 system control registers (sheet 3 of 6)

default
address register name value R/W description
Bit[7:6]: Reserved
Bit[5]: sclk_ac
Bit[4]: sclk_tc
0x301A SC_CMMN_CLKRST0 0x70 RW
Bit[3:2]: Reserved
Bit[1]: rst_ac
Bit[0]: rst_tc

Bit[7]: sclk_blc
Bit[6]: sclk_isp
Bit[5]: Chip debug
Bit[4]: sclk_vfifo
0x301B SC_CMMN_CLKRST1 0xB4 RW
Bit[3]: rst_blc
C

Bit[2]: rst_isp
Bit[1]: Chip debug
on ac

Bit[0]: rst_vfifo

Bit[7]: pclk_dvp
Bit[6:5]: Chip debug
Bit[4]: sclk_otp
W
fid in

0x301C SC_CMMN_CLKRST2 0xF0 RW

Bit[3]: rst_dvp
Bit[2:1]: Chip debug
Bit[0]: rst_otp
en g o

Bit[7]: sclk2x_isp
Bit[6:5]: Chip debug
0x301D SC_CMMN_CLKRST3 0xB4 RW Bit[4]: sclk_aec_pk
h

Bit[3:1]: Chip debug

tia nly

Bit[0]: rst_aec_pk

Bit[7:6]: Chip debug

Bit[5]: pclk_vfifo
0x301E SC_CMMN_CLKRST4 0xF0 RW
lf

Bit[4:2]: Chip debug

Bit[1:0]: Reserved

0x301F RSVD – – Reserved

or

Bit[7]: Not used

Bit[6:1]: Chip debug
Bit:0]: sclk2x option
0x3020 SC_CMMN_CLOCK_SEL 0x0B RW 0: Select from 1x system
clock
1: Select from 2x system
clock

Bit[7]: pclk_inv enable

Bit[6]: sclk_inv enable
0x3021 SC_CMMN_MISC_CTRL 0x03 RW Bit[5]: sclk2x_inv enable
Bit[4:1]: Reserved
Bit[0]: cen_global_o

0x3022 SC_CMMN_CORE_CTRL 0x00 RW Bit[7:0]: Chip debug

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-1 system control registers (sheet 4 of 6)

default
address register name value R/W description
Bit[7:6]: Chip debug
Bit[5]: bist_en
Bit[4]: Clock switch
0: Switch all clock to pad
0x3023 SC_CMMN_CORE_CTRL 0x00 RW
clock
1: Switch from pad clock to
all clock
Bit[3:0]: Chip debug

Bit[7:6]: Chip debug

Bit[5:4]: RAW mode
00: Long
C

01: Short
10: Long, short
on ac

11: Combined
Bit[3]: Debug mode
Bit[2:1]: YUV mode
0x3024 SC_CMMN_CORE_CTRL 0x04 RW
00: HDR
W
fid in

01: Long
10: Short
11: Not allowed
Bit[0]: PCLK PLL disable
en g o

0: PCLK from secondary

PLL
1: PCLK from system clock
h

0x3025 SC_CMMN_CORE_CTRL1 0x00 RW Bit[7:0]: Chip debug

tia nly

0x3028 SC_CMMN_BIST_EN 0x00 RW Chip Debug

0x3029 SC_CMMN_BIST_EN 0x00 RW Bit[7:0]: Debug control

lf

0x302A SC_CMMN_SB_ID 0xF1 R Chip Subversion ID

or

0x302B SC_CMMN_RS232_ID 0xFE RW Chip Debug

0x302C SC_CMMN_PWDN_CTRL1 0x00 RW Chip Debug

0x302D SC_CMMN_PWDN_CTRL2 0x2F RW Chip Debug

Bit[7:1]: Not used

0x302E SC_CMMN_FSIN_EN 0x00 RW
Bit[0]: FSIN enable

Bit[7]: gpio0_sel
Bit[6]: gpio0_dir
Bit[5]: gpio0_out
Bit[4]: Chip debug
0x302F SC_CMMN_GPIO01 0x88 RW
Bit[3]: gpio1_sel
Bit[2]: gpio1_dir
Bit[1]: gpio1_out
Bit[0]: Chip debug

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-5

table 7-1 system control registers (sheet 5 of 6)

default
address register name value R/W description
Bit[7]: gpio2_sel
Bit[6]: gpio2_dir
Bit[5]: gpio2_out
Bit[4]: Chip debug
0x3030 SC_CMMN_GPIO23 0x80 RW
Bit[3]: gpio3_sel
Bit[2]: gpio3_dir
Bit[1]: gpio3_out
Bit[0]: Chip debug

Bit[7]: gpio4_sel_fsin
Bit[6]: gpio4_dir_fsin
0x3031 SC_CMMN_GPIO45 0x00 RW
Bit[5]: gpio4_out
C

Bit[4:0]: Chip debug

on ac

Bit[7]: Not used

Bit[6:4]: n_pump_ck_sel
000: sclk
001: sclk/2
010: sclk/4
W
fid in

011: sclk/8
100: Pad clock
101: Pad clock/2
110: Pad clock/4
en g o

111: Not used

0x3032 SC_CMMN_PUMP_CLK_SEL 0x44 RW
Bit[3]: Reserved
h

Bit[2:0]: p_pump_clk_sel
000: sclk
tia nly

001: sclk/2
010: sclk/4
011: sclk/8
100: Pad clock
lf

101: Pad clock/2

110: Pad clock/4
111: Not used
or

Bit[7:4]: Not used

Bit[3:2]: System clock select
00: Reserved
0x3033 SC_CMMN_SCLK2X_SEL 0x08 RW 01: System clock/2
10: System clock/4
11: Reserved
Bit[1:0]: Reserved

0x3038 SC_CMMN_MAN_ID 0x7F R Manufacturer ID High Byte

0x3039 SC_CMMN_MAN_ID 0xA2 R Manufacturer ID Low Byte

Bit[7:1]: Not used

0x303C SC_CMMN_PWDN – R
Bit[0]: Power down signal from pad

0x303D~
RSVD – – Reserved
0x303E

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-1 system control registers (sheet 6 of 6)

default
address register name value R/W description
Bit[7]: sclk_isp_fc
Bit[6]: sclk_fc
Bit[5]: Reserved
Bit[4]: sclk_fmt
0x3040 SC_CMMN_CLKRST5 0xF0 RW
Bit[3]: rst_isp_fc
Bit[2]: rst_fc
Bit[1]: Reserved
Bit[0]: rst_fmt

0x3041 SC_CMMN_CLKRST6 0xF0 RW Chip Debug

Bit[7]: sclk_wb
C

Bit[6]: sclk_dr
Bit[5]: sclk_mp
on ac

Bit[4]: sclk_ct
0x3042 SC_SOC_CLKRST7 0xF9 RW
Bit[3]: rst_wb
Bit[2]: rst_dr
Bit[1]: rst_mp
Bit[0]: rst_ct
W
fid in

0x3043~
RSVD – – Reserved
0x3044
en g o

Bit[7:1]: Not used

0x3045 SC_CMMN_PWDN_CTRL_SOC 0x01 RW
Bit[0]: Enable SRB when PWDN
h

Bit[7:1]: Not used

0x3046 SC_CMMN_TIMEOUT 0x00 RW
Bit[0]: Timeout counter enable
tia nly

0x3047 SC_CMMN_CLKRST8 0x70 RW Bit[7:0]: Chip debug

0x3048 SC_CMMN_SNR_GATE_CTRL 0x00 RW Bit[7:0]: Chip debug

lf

0x3049 SC_CMMN_SNR_GATE_CTRL 0x00 RW Bit[7:0]: Chip debug

or

7.2 analog control [0x3600 ~ 0x3603, 0x3610 ~ 0x3618, 0x3620 ~ 0x3636]

table 7-2 analog control registers (sheet 1 of 2)

default
address register name value R/W description
0x3600 ANA_ADC1 0x54 RW ADC Control 1

0x3601 ANA_ADC2 0x03 RW ADC Control 2

0x3602 ANA_ADC3 0x2F RW ADC Control 3

0x3603 ANA_ADC4 0x00 RW ADC Control 4

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-7

table 7-2 analog control registers (sheet 2 of 2)

default
address register name value R/W description
0x3610 ANA_ANALOG1 0x2C RW Analog Control 1

0x3611 ANA_ANALOG2 0x66 RW Analog Control 2

0x3612 ANA_ANALOG3 0xE8 RW Analog Control 3

0x3613 ANA_ANALOG4 0x01 RW Analog Control 4

0x3614 ANA_ANALOG5 0x00 RW Analog Control 5

0x3615 ANA_ANALOG6 0x00 RW Analog Control 6

0x3616~
C

ANA_ANALOG7 0x00 RW Debug Registers

0x3618
on ac

0x3620 ANA_ARRAY2 0x88 RW Array Readout Control 2

0x3621 ANA_ARRAY1 0x03 RW Array Readout Control 1

0x3630 ANA_PWC1 0x00 RW Power/Reference Control 1

W
fid in

0x3631 ANA_PWC2 0x14 RW Power/Reference Control 2

0x3632 ANA_PWC3 0x40 RW Power/Reference Control 3

en g o

0x3633 ANA_PWC4 0xBA RW Power/Reference Control 4

h

0x3634 ANA_PWC5 0xB2 RW Power/Reference Control 5

tia nly

0x3635 ANA_PWC6 0x01 RW Power/Reference Control 6

0x3636 TPM_CTRL 0x00 RW Chip Debug

lf

7.3 sensor control [0x3700 ~ 0x3710, 0x3712 ~ 0x374F]

or

table 7-3 sensor control registers (sheet 1 of 2)

default
address register name value R/W description
0x3700 SENSOR_REG00 0x22 RW Timing Control 1

0x3701 SENSOR_CTRL01 0x28 RW Timing Control 2

0x3702 SENSOR_RSTGOLOW 0x20 RW Timing Control 3

0x3703 SENSOR HLDWIDTH 0x32 RW Timing Control 4

0x3704 SENSOR_TXWIDTH 0x32 RW Timing Control 5

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-3 sensor control registers (sheet 2 of 2)

default
address register name value R/W description
0x3705 SENSOR_REG05 0x61 RW Timing Control 6

0x3706 SENSOR_REG06 0x11 RW Debug Mode

0x3707 SENSOR_REG7 0x03 RW Timing Control 7

0x3708 SENSOR_REG8 0x00 RW Timing Control 8

0x3709 SENSOR_REG9 0x28 RW Timing Control 9

0x370A SENSOR_REGA 0x00 RW Timing Control 0A

0x370B SENSOR_REGB 0x11 RW Timing Control 0B

C

0x370C SENSOR_REGC 0x07 RW Timing Control 0C

on ac

0x370D SENSOR_REGD 0x00 RW Timing Control 0D

0x370E SENSOR_REGE 0x10 RW Debug Mode

W
fid in

0x370F SENSOR_REGF 0x40 RW Debug Mode

0x3710 SENSOR_REG10 0x33 RW Timing Control 10

SENSOR_RSTYZ_
en g o

0x3712 0x00 RW Timing Control 12

GOLOW

SENSOR_RSTYZ_
h

0x3713 0x20 RW Timing Control 13

GOLOW
tia nly

0x3714 SENSOR_EQ_GOLOW 0x08 RW Timing Control 14

0x3715 SENSOR_REG15 0x04 RW Timing Control 15

lf

0x3716~
SENSOR DEBUG 0x03 RW Chip Debug
0x374F
or

7.4 timing control [0x3800 ~ 0x382B, 0x3832 ~ 0x3835, 0x3844, 0x3848 ~

0x3849]

table 7-4 timing control registers (sheet 1 of 4)

default
address register name value R/W description
Manual Horizontal Start Address of Array for
0x3800 TIMING_X_START_ADDR 0x00 RW
Readout High Byte

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-9

table 7-4 timing control registers (sheet 2 of 4)

default
address register name value R/W description
Manual Horizontal Start Address of Array for
0x3801 TIMING_X_START_ADDR 0x00 RW
Readout Low Byte

Vertical Start Address of Array for Readout High

0x3802 TIMING_Y_START_ADDR 0x00 RW
Byte

Vertical Start Address of Array for Readout Low

0x3803 TIMING_Y_START_ADDR 0x00 RW
Byte

Manual Horizontal End Address of Array for

0x3804 TIMING_X_END_ADDR 0x05 RW
Readout High Byte

Manual Horizontal End Address of Array for

C

0x3805 TIMING_X_END_ADDR 0x0F RW

Readout Low Byte
on ac

Vertical End Address of Array for Readout High

0x3806 TIMING_Y_END_ADDR 0x03 RW
Byte

Vertical End Address of Array for Readout Low

0x3807 TIMING_Y_END_ADDR 0x28 RW
Byte
W
fid in

0x3808 TIMING_X_OUTPUT_SIZE 0x05 RW DVP Horizontal Output Size (Pixel) High Byte

0x3809 TIMING_X_OUTPUT_SIZE 0x00 RW DVP Horizontal Output Size (Pixel) Low Byte
en g o

0x380A TIMING_Y_OUTPUT_SIZE 0x03 RW DVP Vertical Output Size (Pixel) High Byte
h

0x380B TIMING_Y_OUTPUT_SIZE 0x20 RW DVP Vertical Output Size (Pixel) Low Byte
tia nly

0x380C TIMING_HTS 0x07 RW Horizontal Total Size High Byte

0x380D TIMING_HTS 0x70 RW Horizontal Total Size Low Byte

lf

0x380E TIMING_VTS 0x03 RW Vertical Total Size High Byte

0x380F TIMING_VTS 0x48 RW Vertical Total Size Low Byte

or

ISP Horizontal Windowing Start Address High

0x3810 TIMING_ISP_X_WIN 0x00 RW
Byte

0x3811 TIMING_ISP_X_WIN 0x00 RW ISP Horizontal Windowing Start Address Low Byte

0x3812 TIMING_ISP_Y_WIN 0x00 RW ISP Vertical Windowing Start Address High Byte

0x3813 TIMING_ISP_Y_WIN 0x00 RW ISP Vertical Windowing Start Address Low Byte

Bit[7]: Black line HREF enable

Bit[6]: Reserved
0x3815 TIMING_CTRL15 0x8C RW Bit[5]: Rip SOF enable
Bit[4]: Horizontal crop manual enable
Bit[3:0]: Black lines number

Bit[7:4]: Vertical start line number for tc_sof

0x3817 TIMING_CTRL17 0x00 RW
Bit[3:0]: Debug mode

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-4 timing control registers (sheet 3 of 4)

default
address register name value R/W description
Bit[7:4]: DVP SOF delay control
Bit[3]: BLC vflip
0x3819 TIMING_CTRL19 0x00 RW
Bit[2]: Enable use of left black line to do BLC
Bit[1:0]: Debug control

Bit[7]: Vflip to digital

Bit[6]: Vflip in array
0x381C TIMING_CTRL1C 0x00 RW Bit[5:2]: Chip debug
Bit[1]: Vsub4
Bit[0]: Vsub2

Bit[7]: Debug mode

C

Bit[6]: hdr_en
0x381D TIMING_CTRL1D 0x40 RW Bit[5:2]: Not used
on ac

Bit[1]: Mirror to digital

Bit[0]: Mirror to array

0x381E V_START_H 0x00 RW Vertical Start Offset High Byte

W
fid in

0x381F V_START_L 0x0C RW Vertical Start Offset Low Byte

0x3820~
TIMING_GRP – RW Chip Debug
0x3823
en g o

Bit[7]: Not used

Bit[6]: High temperature AWB disable
h

0x3824 TIMING_CTRL24 0x00 RW Bit[5]: Chip debug

Bit[3]: Use big size embedded table
tia nly

Bit[2:0]: Chip debug

Bit[7:2]: Not used

Bit[1:0]: Min frame rate when in night mode
lf

00: Insert one frame

0x3825 MIN_FRAME 0x01 RW
01: Insert two frame
10: Insert three frame
or

11: Debug mode

0x3826 TIMING_CTRL26 0x00 RW Chip Debug

0x3827 RSVD – – Reserved

Bit[7:2]: Chip debug

Bit[1]: ISP manual target enable for long
0x3828 TIMING_CTRL28 0x00 RW channel
Bit[0]: ISP manual target enable for short
channel

0x3829 TIMING_CTRL29 0x01 RW ISP Manual Target For Long Channel

0x382A TIMING_CTRL2A 0x00 RW ISP Manual Target For Short Channel

0x382B AWB_HT_RANGE 0x00 RW Bit[7:0]: AWB normal range

0x3832 TIMING_TC_CS_RST 0x00 RW Horizontal Counter Reset Value High Byte

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-11

table 7-4 timing control registers (sheet 4 of 4)

default
address register name value R/W description
0x3833 TIMING_TC_CS_RST 0x00 RW Horizontal Counter Reset Value Low Byte

Vertical Counter Reset Value (vts - tc_r_rst) High

0x3834 TIMING_TC_R_RST 0x00 RW
Byte

Vertical Counter Reset Value (vts - tc_r_rst) Low

0x3835 TIMING_TC_R_RST 0x10 RW
Byte

Bit[7:4]: Not used

0x3844 TIMING_GRP_STS – W
Bit[3:0]: Chip debug

0x3848~
TIMING_CTRL 0x00 RW Frame Counter For Debug
0x3849
C
on ac

7.5 OTP control [0x3D00 ~ 0x3D11, 0x3D1F, 0x3D30 ~ 0x3D5F]

W
fid in

table 7-5 OTP control registers (sheet 1 of 4)

default
en g o

address register name value R/W description

0x3D00 OTP_DATA_0 0x00 RW OTP Dump/load Data Buffer0
h

0x3D01 OTP_DATA_1 0x00 RW OTP Dump/load Data Buffer1

tia nly

0x3D02 OTP_DATA_2 0x00 RW OTP Dump/load Data Buffer2

0x3D03 OTP_DATA_3 0x00 RW OTP Dump/load Data Buffer3

lf

0x3D04 OTP_DATA_4 0x00 RW OTP Dump/load Data Buffer4

or

0x3D05 OTP_DATA_5 0x00 RW OTP Dump/load Data Buffer5

0x3D06 OTP_DATA_6 0x00 RW OTP Dump/load Data Buffer6

0x3D07 OTP_DATA_7 0x00 RW OTP Dump/load Data Buffer7

0x3D08 OTP_DATA_8 0x00 RW OTP Dump/load Data Buffer8

0x3D09 OTP_DATA_9 0x00 RW OTP Dump/load Data Buffer9

0x3D0A OTP_DATA_A 0x00 RW OTP Dump/load Data BufferA

0x3D0B OTP_DATA_B 0x00 RW OTP Dump/load Data BufferB

0x3D0C OTP_DATA_C 0x00 RW OTP Dump/load Data BufferC

0x3D0D OTP_DATA_D 0x00 RW OTP Dump/load Data BufferD

0x3D0E OTP_DATA_E 0x00 RW OTP Dump/load Data BufferE

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-5 OTP control registers (sheet 2 of 4)

default
address register name value R/W description
0x3D0F OTP_DATA_F 0x00 RW OTP Dump/load Data BufferF

Bit[7:6]: Not used

Bit[5:4]: Bank select
00: Select bank0
1x: Select all 4 banks
Bit[3:2]: Not used
0x3D10 OTP_MODE 0xC0 RW
Bit[1:0]: opt_mode
00: OTP OFF
01: Load/dump OTP
10: Write/program OTP
11: OTP OFF
C

Bit[7]: Not used

on ac

Bit[6:4]: write_speed
0x3D11 OTP_SPEED 0x46 RW
Bit[3]: Not used
Bit[2:0]: read_speed

Bit[7:1]: Not used

W
fid in

0x3D1F OTP_EF_STATUS – R
Bit[0]: otp_busy

0x3D30 OTP_DATA_10 0x00 RW OTP Dump/load Data Buffer10

en g o

0x3D31 OTP_DATA_11 0x00 RW OTP Dump/load Data Buffer11

0x3D32 OTP_DATA_12 0x00 RW OTP Dump/load Data Buffer12

h

0x3D33 OTP_DATA_13 0x00 RW OTP Dump/load Data Buffer13

tia nly

0x3D34 OTP_DATA_14 0x00 RW OTP Dump/load Data Buffer14

0x3D35 OTP_DATA_15 0x00 RW OTP Dump/load Data Buffer15

lf

0x3D36 OTP_DATA_16 0x00 RW OTP Dump/load Data Buffer16

0x3D37 OTP_DATA_17 0x00 RW OTP Dump/load Data Buffer17

or

0x3D38 OTP_DATA_18 0x00 RW OTP Dump/load Data Buffer18

0x3D39 OTP_DATA_19 0x00 RW OTP Dump/load Data Buffer19

0x3D3A OTP_DATA_1A 0x00 RW OTP Dump/load Data Buffer1A

0x3D3B OTP_DATA_1B 0x00 RW OTP Dump/load Data Buffer1B

0x3D3C OTP_DATA_1C 0x00 RW OTP Dump/load Data Buffer1C

0x3D3D OTP_DATA_1D 0x00 RW OTP Dump/load Data Buffer1D

0x3D3E OTP_DATA_1E 0x00 RW OTP Dump/load Data Buffer1E

0x3D3F OTP_DATA_1F 0x00 RW OTP Dump/load Data Buffer1F

0x3D40 OTP_DATA_20 0x00 RW OTP Dump/load Data Buffer20

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-13

table 7-5 OTP control registers (sheet 3 of 4)

default
address register name value R/W description
0x3D41 OTP_DATA_21 0x00 RW OTP Dump/load Data Buffer21

0x3D42 OTP_DATA_22 0x00 RW OTP Dump/load Data Buffer22

0x3D43 OTP_DATA_23 0x00 RW OTP Dump/load Data Buffer23

0x3D44 OTP_DATA_24 0x00 RW OTP Dump/load Data Buffer24

0x3D45 OTP_DATA_25 0x00 RW OTP Dump/load Data Buffer25

0x3D46 OTP_DATA_26 0x00 RW OTP Dump/load Data Buffer26

0x3D47 OTP_DATA_27 0x00 RW OTP Dump/load Data Buffer27

C

0x3D48 OTP_DATA_28 0x00 RW OTP Dump/load Data Buffer28

on ac

0x3D49 OTP_DATA_29 0x00 RW OTP Dump/load Data Buffer29

0x3D4A OTP_DATA_2A 0x00 RW OTP Dump/load Data Buffer2A

W
fid in

0x3D4B OTP_DATA_2B 0x00 RW OTP Dump/load Data Buffer2B

0x3D4C OTP_DATA_2C 0x00 RW OTP Dump/load Data Buffer2C

0x3D4D OTP_DATA_2D 0x00 RW OTP Dump/load Data Buffer2D

en g o

0x3D4E OTP_DATA_2E 0x00 RW OTP Dump/load Data Buffer2E

h

0x3D4F OTP_DATA_2F 0x00 RW OTP Dump/load Data Buffer2F

tia nly

0x3D50 OTP_DATA_30 0x00 RW OTP Dump/load Data Buffer30

0x3D51 OTP_DATA_31 0x00 RW OTP Dump/load Data Buffer31

lf

0x3D52 OTP_DATA_32 0x00 RW OTP Dump/load Data Buffer32

0x3D53 OTP_DATA_33 0x00 RW OTP Dump/load Data Buffer33

or

0x3D54 OTP_DATA_34 0x00 RW OTP Dump/load Data Buffer34

0x3D55 OTP_DATA_35 0x00 RW OTP Dump/load Data Buffer35

0x3D56 OTP_DATA_36 0x00 RW OTP Dump/load Data Buffer36

0x3D57 OTP_DATA_37 0x00 RW OTP Dump/load Data Buffer37

0x3D58 OTP_DATA_38 0x00 RW OTP Dump/load Data Buffer38

0x3D59 OTP_DATA_39 0x00 RW OTP Dump/load Data Buffer39

0x3D5A OTP_DATA_3A 0x00 RW OTP Dump/load Data Buffer3A

0x3D5B OTP_DATA_3B 0x00 RW OTP Dump/load Data Buffer3B

0x3D5C OTP_DATA_3C 0x00 RW OTP Dump/load Data Buffer3C

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-5 OTP control registers (sheet 4 of 4)

default
address register name value R/W description
0x3D5D OTP_DATA_3D 0x00 RW OTP Dump/load Data Buffer3D

0x3D5E OTP_DATA_3E 0x00 RW OTP Dump/load Data Buffer3E

0x3D5F OTP_DATA_3F 0x00 RW OTP Dump/load Data Buffer3F

7.6 BLC function [0x4000 ~ 0x405B, 0xC4B7 ~ 0xC50F, 0x5B1C ~ 0x5D30]

C

table 7-6 BLC function registers (sheet 1 of 11)

on ac

default
address register name value R/W description
Bit[7:4]: Not used
Bit[3:1]: Chip debug
W
fid in

0x4000 BLC CTRL00 0x09 RW Bit[0]: BLC enable

0: Disable
1: Enable
en g o

Bit[7:5]: Not used

Bit[4:0]: start_line
0x4001 START LINE 0x04 RW
Start line for calculating normal
h

offsets
tia nly

Bit[7]: format_change_en
0: Change of format will not
trigger BLC
lf

1: Change of format will trigger

BLC
Bit[6]: offset_auto_en
0x4002 BLC CTRL02 0xC5 RW
or

0: Use manual offsets

1: Use calculated offsets
Bit[5:0]: rest_frame_num
Number indicates how many
frames BLC will be updated
continuously when BLC is reset

Bit[7]: trig_man
BLC manual trigger signal
BLC will update
manual_frame_num frames
continuously from its rising edge
0x4003 BLC CTRL03 0x08 RW Bit[6]: freeze_en
When set, BLC will freeze
Bit[5:0]: manual_frame_num
Number indicates how many
frames BLC will be updated
continuously when trig_man is set

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-15

table 7-6 BLC function registers (sheet 2 of 11)

default
address register name value R/W description
Bit[7:5]: Not used
Bit[4:0]: line_num
0x4004 LINE NUM 0x08 RW
Line number specifies black lines
used in offsets calculation

Bit[7:6]: Not used

Bit[5]: one_line_mode
When set, BLC offsets for B and Gr
are the same. Gb and R offsets are
the same
Bit[4]: remove_black_line
0: Output image includes black
C

lines
1: Output image does not
on ac

include black lines

0x4005 BLC CTRL05 0x18 R/W Bit[3]: one_man_offset_mode
When set and manual offsets
enable is set, manual offsets for B,
W
fid in

Gb, Gr and R are same (first

manual offset)
Bit[2]: bl_rblue_rvs
When set, black lines' rblue signal
en g o

will be reversed
Bit[1]: blc_always_do
When set, BLC will always update
h

Bit[0]: Not used

tia nly

0x4006 NOT USED – – Not Used

Bit[7:5]: Not used

Bit[4:3]: hwin_sel
lf

00: Horizontal size will be full size

01: Horizontal size will exclude
16 left and 16 right pixels
or

10: Horizontal size will exclude

1/16 left and 1/16 right
window of full size
11: Horizontal size will exclude
0x4007 BLC CTRL07 0x00 R/W
1/8 left and 1/8 right window
of full size
Bit[2]: sub128_en
When set, output bypass data is
subtracted by 128
Bit[1:0]: bypass_mode
00: Output limited input data
01: Output 10 LSBs of input data
1x: Output 10 MSBs of input data

Bit[7:0]: long_blc_target
0x4008 LONG BLC TARGET 0x10 R/W
BLC target for long exposure data

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-6 BLC function registers (sheet 3 of 11)

default
address register name value R/W description
Bit[7:0]: short_blc_target
0x4009 SHORT BLC TARGET 0x10 R/W
BLC target for short exposure data

0x400A~
NOT USED – – Not Used
0x400B

Bit[7:1]: Not used

Bit[0]: man_offset00[8]
0x400C MANUAL OFFSET 00 0x00 R/W
Manual offset for B channel of long
exposure data

Bit[7:0]: man_offset00[7:0]
C

0x400D MANUAL OFFSET 00 0x00 R/W Manual offset for B channel of long
exposure data
on ac

Bit[7:1]: Not used

Bit[0]: man_offset01[8]
0x400E MANUAL OFFSET 01 0x00 R/W
Manual offset for Gb channel of
long exposure data
W
fid in

Bit[7:0]: man_offset01[7:0]
0x400F MANUAL OFFSET 01 0x00 RW Manual offset for Gb channel of
long exposure data
en g o

Bit[7:1]: Not used

Bit[0]: man_offset02[8]
0x4010 MANUAL OFFSET 02 0x00 RW
Manual offset for Gr channel of
h

long exposure data

tia nly

Bit[7:0]: man_offset02[7:0]
0x4011 MANUAL OFFSET 02 0x00 RW Manual offset for Gr channel of
long exposure data
lf

Bit[7:1]: Not used

Bit[0]: man_offset03[8]
0x4012 MANUAL OFFSET 03 0x00 RW
Manual offset for R channel of long
or

exposure data

Bit[7:0]: man_offset03[7:0]
0x4013 MANUAL OFFSET 03 0x00 RW Manual offset for R channel of long
exposure data

0x4014~
NOT USED – – Not Used
0x4033

Bit[7:1]: Not used

Bit[0]: man_offset10[8]
0x4034 MANUAL OFFSET 10 0x00 RW
Manual offset for B channel of short
exposure data

Bit[7:0]: man_offset10[7:0]
0x4035 MANUAL OFFSET 10 0x00 RW Manual offset for B channel of short
exposure data

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-17

table 7-6 BLC function registers (sheet 4 of 11)

default
address register name value R/W description
Bit[7:1]: Not used
Bit[0]: man_offset11[8]
0x4036 MANUAL OFFSET 11 0x00 RW
Manual offset for Gb channel of
short exposure data

Bit[7:0]: man_offset11[7:0]
0x4037 MANUAL OFFSET 11 0x00 RW Manual offset for Gb channel of
short exposure data

Bit[7:1]: Not used

Bit[0]: man_offset12[8]
0x4038 MANUAL OFFSET 12 0x00 RW
Manual offset for Gr channel of
C

short exposure data

Bit[7:0]: man_offset12[7:0]
on ac

0x4039 MANUAL OFFSET 12 0x00 RW Manual offset for Gr channel of

short exposure data

Bit[7:1]: Not used

W
fid in

Bit[0]: man_offset13[8]
0x403A MANUAL OFFSET 13 0x00 RW
Manual offset for R channel of
short exposure data

Bit[7:0]: man_offset13[7:0]
en g o

0x403B MANUAL OFFSET 13 0x00 RW Manual offset for R channel of

short exposure data
h

0x403C~
tia nly

NOT USED – – Not Used

0x404B

0x404C~ TOTAL BLACK LINE

– R Debug Information for BLC Control Function
0x404D NUM
lf

0x404E~
NOT USED – – Not Used
0x404F
or

0x4050 BLC AVG CTRL 1 0x20 RW BLC Average Control 1

0x4051 BLC AVG CTRL 2 0x22 RW BLC Average Control 2

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-6 BLC function registers (sheet 5 of 11)

default
address register name value R/W description
Bit[7:4]: BLC debug control
Bit[3]: short_option
0: Short exposure channel will
use BLC statistics of short
exposure channel
1: Short exposure channel will
use BLC statistics of long
exposure channel
Bit[2]: long_option
0: Long exposure channel will
use BLC statistics of long
0x4052 BLC CTRL52 0x00 RW
C

exposure channel
1: Long exposure channel will
use BLC statistics of short
on ac

exposure channel
Bit[1]: blc_mid_en
0: Keep black line data
1: Median for black line data
W
fid in

Bit[0]: one_channel
When set, used offsets will be
average of calculated offsets for B,
Gb, Gr and R channel
en g o

0x4053 BLC CTRL53 0x00 RW Bit[7:0]: BLC debug control

h

0x4054 BLC CTRL54 0x00 RW Bit[7:0]: BLC debug control

tia nly

Bit[7]: BLC debug control

Bit[6]: short_tmp_chg_en
Short channel temperature
changing enable signal
lf

Bit[5]: short_exp_chg_en
Short channel exposure changing
enable signal
or

Bit[4]: short_gain_chg_en
Short channel gain changing
enable signal
Bit[3]: long_ana_frz_en
0x4055 BLC CTRL55 0xFF RW
Long channel analog freeze enable
signal
Bit[2]: long_tmp_chg_en
Long channel temperature
changing enable signal
Bit[1]: long_exp_chg_en
long channel exposure changing
enable signal
Bit[0]: long_gain_chg_en
Long channel gain changing
enable signal

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-19

table 7-6 BLC function registers (sheet 6 of 11)

default
address register name value R/W description
OFFSET TOP LIMIT
0x4056 0x07 RW BLC Control 1
MSB

OFFSET TOP LIMIT

0x4057 0xFF RW BLC Control 2
LSB

OFFSET BOT LIMIT

0x4058 0x01 RW BLC Control 3
MSB

OFFSET BOT LIMIT

0x4059 0xE0 RW BLC Control 4
LSB

Bit[7]: Not used

C

0x405A BLC CTRL5A 0x70 RW

Bit[6:0]: BLC debug control
on ac

Bit[7:2]: Not used

0x405B BLC CTRL5B 0x00 RW
Bit[1:0]: BLC debug control

Bit[7:1]: Not used

Bit[0]: Auto black level cancelling
W
fid in

0: Disable
1: Enable
0xC4B7 AUTO_BLC_EN – RW
When register value is 0x00, it means function
en g o

is disabled; all other values mean function is

enabled. This register value must be initialized
by user and must not be removed from start up
h

sequence. Default value is random.

tia nly

BLC Adjustment Trigger Limitation

0xC4E0 BLC_TRIGGE_LIMIT – RW This register value must be initialized by user

lf

and must not be removed from start up

sequence. Default value is random.

BLC Adjustment Stable Limitation

or

0xC4E1 BLC_STABLE_LIMIT – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Auto BLC Adjustment Relative Step

0xC4E2 BLC_STEP – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-6 BLC function registers (sheet 7 of 11)

default
address register name value R/W description
Bit[7:1]: Not used
Bit[0]: Smooth offset statistics in first 16
frames
0: Disable
1: Enable
BLC_PRE_SMOOTH_
0xC4E3 – RW
EN
When register value is 0x00, it means function
is disabled; all other values mean function is
enabled. This register value will be
automatically initialized by sensor after
powering up. Default value is random.
C

Bit[7:1]: Not used

Bit[0]: High temperature BLC option1
on ac

enable
Increases stable and slow range
Decreases adjustment step
0: Disable
BLC_HT_OPTION1_
W
fid in

0xC4FA – RW 1: Enable
EN
When register value is 0x00, it means function
is disabled; all other values mean function is
en g o

enabled. This register value must be initialized

by user and must not be removed from start up
sequence. Default value is random.
h

Bit[7:1]: Not used

tia nly

Bit[0]: High temperature BLC option2

enable
Decreases maximum exposure
lines
lf

0: Disable
BLC_HT_OPTION2_
0xC4FB – RW 1: Enable
EN
or

When register value is 0x00, it means function

is disabled; all other values mean function is
enabled. This register value must be initialized
by user and must not be removed from start up
sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-21

table 7-6 BLC function registers (sheet 8 of 11)

default
address register name value R/W description
Bit[7:1]: Not used
Bit[0]: High temperature BLC option3
enable
Switches analog gain to digital gain
0: Disable
BLC_HT_OPTION3_ 1: Enable
0xC4FC – RW
EN
When register value is 0x00, it means function
is disabled; all other values mean function is
enabled. This register value must be initialized
by user and must not be removed from start up
C

sequence. Default value is random.

Bit[7:1]: Not used

on ac

Bit[0]: High temperature BLC

temperature limits exposure when
option2 is enabled
0: Disable
W
fid in

BLC_HT_TEMP_EXP_ 1: Enable
0xC4FD – RW
EN
When register value is 0x00, it means function
is disabled; all other values mean function is
en g o

enabled. This register value must be initialized

by user and must not be removed from start up
sequence. Default value is random.
h

High Temperature BLC Min Exposure Lines

tia nly

Limited by temperature
BLC_HT_TEMP_
0xC4FE – RW
MINEXP This register value must be initialized by user
and must not be removed from start up
lf

sequence. Default value is random.

High Temperature BLC Max Exposure Step

or

BLC_HT_
0xC4FF – RW This register value must be initialized by user
EXPMAXSTEP
and must not be removed from start up
sequence. Default value is random.

High Temperature BLC Temperature Threshold

Long 1
BLC_HT_TEMP_TH_
0xC500 – RW
1L This register value must be initialized by user
and must not be removed from start up
sequence. Default value is random.

High Temperature BLC Temperature Threshold

Short 1
BLC_HT_TEMP_TH_
0xC501 – RW
1S This register value must be initialized by user
and must not be removed from start up
sequence. Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-6 BLC function registers (sheet 9 of 11)

default
address register name value R/W description
High Temperature BLC Temperature Threshold
Long 2
BLC_HT_TEMP_TH_
0xC502 – RW
2L This register value must be initialized by user
and must not be removed from start up
sequence. Default value is random.

High Temperature BLC Temperature Threshold

Short 2
BLC_HT_TEMP_TH_
0xC503 – RW
2S This register value must be initialized by user
and must not be removed from start up
C

sequence. Default value is random.

on ac

Bit[7:0]: High temperature BLC exposure

threshold 1
0xC504 BLC_HT_EXP_TH_11 – RW
This register value must be initialized by user
and must not be removed from start up
W
fid in

sequence. Default value is random.

Bit[7:0]: High temperature BLC exposure

threshold 1
en g o

0xC505 BLC_HT_EXP_TH_12 – RW
This register value must be initialized by user
and must not be removed from start up
h

sequence. Default value is random.

tia nly

Bit[7:0]: High temperature BLC exposure

threshold 2
0xC506 BLC_HT_EXP_TH_21 – RW
lf

This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
or

Bit[7:0]: High temperature BLC exposure

threshold 2
0xC507 BLC_HT_EXP_TH_22 – RW
This register value must be initialized by user
and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: High temperature BLC threshold 1

0xC508 BLC_HT_SA1_TH_11 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-23

table 7-6 BLC function registers (sheet 10 of 11)

default
address register name value R/W description
Bit[7:0]: High temperature BLC threshold 1

0xC509 BLC_HT_SA1_TH_12 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: High temperature BLC threshold 2

0xC50A BLC_HT_SA1_TH_21 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
C

Bit[7:0]: High temperature BLC threshold 2

on ac

0xC50B BLC_HT_SA1_TH_22 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: High temperature BLC threshold 3

W
fid in

0xC50C BLC_HT_SA1_TH_31 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
en g o

Bit[7:0]: High temperature BLC threshold 3

h

0xC50D BLC_HT_SA1_TH_32 – RW This register value must be initialized by user

tia nly

and must not be removed from start up

sequence. Default value is random.

Bit[7:0]: High temperature BLC threshold 4

lf

0xC50E BLC_HT_SA1_TH_41 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
or

Bit[7:0]: High temperature BLC threshold 4

0xC50F BLC_HT_SA1_TH_42 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

0x5B1C~
BLC_R – R Debug Information for BLC
0x5B49

Bit[7:3]: Not used

0x5D1C BLC_RO01 – R
Bit[2:0]: long_offset_00[10:8]

0x5D1D BLC_RO02 0x00 RW Bit[7:0]: long_offset_00[7:0]

Bit[7:3]: Not used

0x5D1E BLC_RO03 0x00 RW
Bit[2:0]: long_offset_01[10:8]

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-6 BLC function registers (sheet 11 of 11)

default
address register name value R/W description
0x5D1F BLC_RO04 0x00 RW Bit[7:0]: long_offset_01[7:0]

Bit[7:3]: Not used

0x5D20 BLC_RO05 0x00 RW
Bit[2:0]: long_offset_10[10:8]

0x5D21 BLC_RO06 0x00 RW Bit[7:0]: long_offset_10[7:0]

Bit[7:3]: Not used

0x5D22 BLC_RO07 0x00 RW
Bit[2:0]: long_offset_11[10:8]

0x5D23 BLC_RO08 0x00 RW Bit[7:0]: long_offset_11[7:0]

Bit[7:3]: Not used

C

0x5D24 BLC_RO09 0x00 RW

Bit[2:0]: short_offset_00[10:8]

0x5D25 BLC_RO10 0x00 RW Bit[7:0]: short_offset_00[7:0]

on ac

Bit[7:3]: Not used

0x5D26 BLC_RO11 0x00 RW
Bit[2:0]: short_offset_01[10:8]
W
fid in

0x5D27 BLC_RO12 0x00 RW Bit[7:0]: short_offset_01[7:0]

Bit[7:3]: Not used

0x5D28 BLC_RO13 0x00 RW
Bit[2:0]: short_offset_10[10:8]
en g o

0x5D29 BLC_RO14 0x00 RW Bit[7:0]: short_offset_10[7:0]

Bit[7:3]: Not used

0x5D2A BLC_RO15 0x00 RW
h

Bit[2:0]: short_offset_11[10:8]
tia nly

0x5D2B BLC_RO16 0x00 RW Bit[7:0]: short_offset_11[7:0]

0x5D2C~ BLC_RW17~
– – Debug Information for BLC
0x5D2F BLC_RW20
lf

Bit[7]: short_ana_freeze
Bit[6]: long_ana_freeze
or

Bit[5]: short_tmp_chg
Bit[4]: long_tmp_chg
0x5D30 BLC_RW21 – R
Bit[3]: short_exp_chg
Bit[2]: long_exp_chg
Bit[1]: short_gain_chg
Bit[0]: long_gain_chg

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-25

7.7 AEC [0x3503, 0x3504, 0x5600 ~ 0x56EB, 0xC2ED ~ 0xC51B, 0x5A00 ~

0x5C17]

table 7-7 AEC control registers (sheet 1 of 26)

default
address register name value R/W description
Bit[7:6]: Not used
Bit[5]: Gain delay option
0: One frame latch
1: Delay one frame latch
0x3503 AEC_PK_MANUAL 0x00 RW
Bit[4]: Choose delay option
C

0: Delay disable
1: Delay enable
Bit[3:0]: Not used
on ac

Bit[7:1]: Not used

0x3504 AEC_PK_MAN_DONE 0x00 RW
Bit[0]: AEC manual done

Bit[7:2]: Not used

W
fid in

Bit[1:0]: Sampling
0x5600 AEC CTRL00 0x01 RW 0x: 2
10: 4
11: 8
en g o

Bit[7:3]: Not used

0x5601 AEC CTRL01 0x00 RW Bit[2:0]: Statwinleft[10:8]
h

Horizontal start point for statistic image

tia nly

Bit[7:0]: Statwinleft[7:0]
0x5602 AEC CTRL02 0x00 RW
Horizontal start point for statistic image

Bit[7:2]: Not used

lf

0x5603 AEC CTRL03 0x00 RW Bit[1:0]: Statwintop[9:8]

Vertical start point for statistic image
or

Bit[7:0]: Statwintop[7:0]
0x5604 AEC CTRL04 0x04 RW
Vertical start point for statistic image

Bit[7:3]: Not used

0x5605 AEC CTRL05 0x00 RW Bit[2:0]: Statwinright[10:8]
Horizontal end point for statistic image

Bit[7:0]: Statwinright[7:0]
0x5606 AEC CTRL06 0x00 RW
Horizontal end point for statistic image

Bit[7:2]: Not used

0x5607 AEC CTRL07 0x00 RW Bit[1:0]: Statwinbottom[9:8]
Vertical end point for statistic image

Bit[7:0]: Statwinbottom[7:0]
0x5608 AEC CTRL08 0x08 RW
Vertical end point for statistic image

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-7 AEC control registers (sheet 2 of 26)

default
address register name value R/W description
Bit[7:3]: Not used
Bit[2:0]: winleft_l[10:8]
0x5609 AEC CTRL09 0x00 RW
Horizontal start point to compute
weight for long exposure sub-pixel

Bit[7:0]: winleft_l[7:0]
0x560A AEC CTRL0A 0x64 RW Horizontal start point to calculate
weight for long exposure sub-pixel

Bit[7:3]: Not used

Bit[2:0]: winleft_s[10:8]
0x560B AEC CTRL0B 0x00 RW
Horizontal start point to calculate
C

weight for short exposure sub-pixel

Bit[7:0]: winleft_s[7:0]
on ac

0x560C AEC CTRL0C 0x64 RW Horizontal start point to calculate

weight for short exposure sub-pixel

Bit[7:2]: Not used

W
fid in

Bit[1:0]: wintop_l[9:8]
0x560D AEC CTRL0D 0x00 RW
Vertical start point to calculate weight
for long exposure sub-pixel

Bit[7:0]: wintop_l[7:0]
en g o

0x560E AEC CTRL0E 0x4B RW Vertical start point to calculate weight

for long exposure sub-pixel
h

Bit[7:2]: Not used

tia nly

Bit[1:0]: wintop_s[9:8]
0x560F AEC CTRL0F 0x00 RW
Vertical start point to calculate weight
for short exposure sub-pixel
lf

Bit[7:0]: wintop_s[7:0]
0x5610 AEC CTRL10 0x4B RW Vertical start point to calculate weight
for short exposure sub-pixel
or

Bit[7:3]: Not used

Bit[2:0]: winwidth_l[10:8]
0x5611 AEC CTRL11 0x00 RW
Horizontal width to calculate weight for
long exposure sub-pixel

Bit[7:0]: winwidth_l[7:0]
0x5612 AEC CTRL12 0xC8 RW Horizontal width to calculate weight for
long exposure sub-pixel

Bit[7:3]: Not used

Bit[2:0]: winwidth_s[10:8]
0x5613 AEC CTRL13 0x00 RW
Horizontal width to calculate weight for
short exposure sub-pixel

Bit[7:0]: winwidth_s[7:0]
0x5614 AEC CTRL14 0xC8 RW Horizontal width to calculate weight for
short exposure sub-pixel

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-27

table 7-7 AEC control registers (sheet 3 of 26)

default
address register name value R/W description
Bit[7:2]: Not used
Bit[1:0]: winheight_l[9:8]
0x5615 AEC CTRL15 0x00 RW
Vertical width to calculate weight for
long exposure sub-pixel

Bit[7:0]: winheight_l[7:0]
0x5616 AEC CTRL16 0x96 RW Vertical width to calculate weight for
long exposure sub-pixel

Bit[7:2]: Not used

Bit[1:0]: winheight_s[9:8]
0x5617 AEC CTRL17 0x00 RW
Vertical width to calculate weight for
C

long exposure sub-pixel

Bit[7:0]: winheight_s[7:0]
on ac

0x5618 AEC CTRL18 0x96 RW Vertical width to calculate weight for

long exposure sub-pixel

Bit[7:3]: Not used

W
fid in

Bit[2:0]: roileft_l[10:8]
0x5619 AEC CTRL19 0x00 RW
Horizontal start point for ROI for long
exposure sub-pixel

Bit[7:0]: roileft_l[7:0]
en g o

0x561A AEC CTRL1A 0x00 RW Horizontal start point for ROI for long
exposure sub-pixel
h

Bit[7:3]: Not used

tia nly

Bit[2:0]: roileft_s[10:8]
0x561B AEC CTRL1B 0x00 RW
Horizontal start point for ROI for short
exposure sub-pixel
lf

Bit[7:0]: roileft_s[7:0]
0x561C AEC CTRL1C 0x00 RW Horizontal start point for ROI for short
exposure sub-pixel
or

Bit[7:2]: Not used

Bit[1:0]: roitop_l[9:8]
0x561D AEC CTRL1D 0x00 RW
Vertical start point for ROI for long
exposure sub-pixel

Bit[7:0]: roitop_l[7:0]
0x561E AEC CTRL1E 0x00 RW Vertical start point for ROI for long
exposure sub-pixel

Bit[7:2]: Not used

Bit[1:0]: roitop_s[9:8]
0x561F AEC CTRL1F 0x00 RW
Vertical start point for ROI for short
exposure sub-pixel

Bit[7:0]: roitop_s[7:0]
0x5620 AEC CTRL20 0x00 RW Vertical start point for ROI for short
exposure sub-pixel

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-7 AEC control registers (sheet 4 of 26)

default
address register name value R/W description
Bit[7:3]: Not used
Bit[2:0]: roiright_l[10:8]
0x5621 AEC CTRL21 0x00 RW
Horizontal end point for ROI for long
exposure sub-pixel

Bit[7:0]: roiright_l[7:0]
0x5622 AEC CTRL22 0x00 RW Horizontal end point for ROI for long
exposure sub-pixel

Bit[7:3]: Not used

Bit[2:0]: roiright_s[10:8]
0x5623 AEC CTRL23 0x00 RW
Horizontal end point for ROI for short
C

exposure sub-pixel

Bit[7:0]: roiright_s[7:0]
on ac

0x5624 AEC CTRL24 0x00 RW Horizontal end point for ROI for short
exposure sub-pixel

Bit[7:2]: Not used

W
fid in

Bit[1:0]: roibottom_l[9:8]
0x5625 AEC CTRL25 0x00 RW
Vertical end point for ROI for long
exposure sub-pixel

Bit[7:0]: roibottom_l[7:0]
en g o

0x5626 AEC CTRL26 0x00 RW Vertical end point for ROI for long
exposure sub-pixel
h

Bit[7:2]: Not used

tia nly

Bit[1:0]: roibottom_s[9:8]
0x5627 AEC CTRL27 0x00 RW
Vertical end point for ROI for short
exposure sub-pixel
lf

Bit[7:0]: roibottom_s[7:0]
0x5628 AEC CTRL28 0x00 RW Vertical end point for ROI for short
exposure sub-pixel
or

Bit[7:6]: Not used

0x5629 AEC CTRL29 0x00 RW Bit[5:3]: r_roishift_l
Bit[2:0]: r_roishift_s

0x562A AEC CTRL2A 0x01 RW ROIweightl0 for Long Exposure Sub-pixel

0x562B AEC CTRL2B 0x01 RW ROIweightl1 for Long Exposure Sub-pixel

0x562C AEC CTRL2C 0x01 RW ROIweights0 for Short Exposure Sub-pixel

0x562D AEC CTRL2D 0x01 RW ROIweights1 for Short Exposure Sub-pixel

0x562E AEC CTRL2E 0x01 RW Weightl0 for Long Exposure Sub-pixel

0x562F AEC CTRL2F 0x01 RW Weightl1 for Long Exposure Sub-pixel

0x5630 AEC CTRL30 0x01 RW Weightl2 for Long Exposure Sub-pixel

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-29

table 7-7 AEC control registers (sheet 5 of 26)

default
address register name value R/W description
0x5631 AEC CTRL31 0x01 RW Weightl3 for Long Exposure Sub-pixel

0x5632 AEC CTRL32 0x01 RW Weightl4 for Long Exposure Sub-pixel

0x5633 AEC CTRL33 0x01 RW Weightl5 for Long Exposure Sub-pixel

0x5634 AEC CTRL34 0x01 RW Weightl6 for Long Exposure Sub-pixel

0x5635 AEC CTRL35 0x01 RW Weightl7 for Long Exposure Sub-pixel

0x5636 AEC CTRL36 0x01 RW Weightl8 for Long Exposure Sub-pixel

0x5637 AEC CTRL37 0x01 RW Weightl9 for Long Exposure Sub-pixel

C

0x5638 AEC CTRL38 0x01 RW Weightla for Long Exposure Sub-pixel

on ac

0x5639 AEC CTRL39 0x01 RW Weightlb for Long Exposure Sub-pixel

0x563A AEC CTRL3A 0x01 RW Weightlc for Long Exposure Sub-pixel

W
fid in

0x563B AEC CTRL3B 0x01 RW Weights0 for Short Exposure Sub-pixel

0x563C AEC CTRL3C 0x01 RW Weights1 for Short Exposure Sub-pixel

0x563D AEC CTRL3D 0x01 RW Weights2 for Short Exposure Sub-pixel

en g o

0x563E AEC CTRL3E 0x01 RW Weights3 for Short Exposure Sub-pixel

h

0x563F AEC CTRL3F 0x01 RW Weights4 for Short Exposure Sub-pixel

tia nly

0x5640 AEC CTRL40 0x01 RW Weights5 for Short Exposure Sub-pixel

0x5641 AEC CTRL41 0x01 RW Weights6 for Short Exposure Sub-pixel

lf

0x5642 AEC CTRL42 0x01 RW Weights7 for Short Exposure Sub-pixel

0x5643 AEC CTRL43 0x01 RW Weights8 for Short Exposure Sub-pixel

or

0x5644 AEC CTRL44 0x01 RW Weights9 for Short Exposure Sub-pixel

0x5645 AEC CTRL45 0x01 RW Weightsa for Short Exposure Sub-pixel

0x5646 AEC CTRL46 0x01 RW Weightsb for Short Exposure Sub-pixel

0x5647 AEC CTRL47 0x01 RW Weightsc for Short Exposure Sub-pixel

0x5648 AEC CTRL48 0x01 RW Minwl for Long Exposure Sub-pixel

0x5649 AEC CTRL49 0x01 RW Minws for Short Exposure Sub-pixel

Bit[7:2]: Not used

0x564A AEC CTRL4A 0x00 RW
Bit[1:0]: Maxwl[9:8] for long exposure sub-pixel

0x564B AEC CTRL4B 0x20 RW Bit[7:0]: Maxwl[7:0] for long exposure sub-pixel

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-7 AEC control registers (sheet 6 of 26)

default
address register name value R/W description
Bit[7:2]: Not used
0x564C AEC CTRL4C 0x01 RW Bit[1:0]: Maxws[9:8] for short exposure
sub-pixel

Bit[7:0]: Maxws[7:0] for short exposure

0x564D AEC CTRL4D 0x00 RW
sub-pixel

0x564E AEC CTRL4E 0x00 RW Poswshift

0x564F AEC CTRL4F 0x04 RW Lowlightthre

0x5650 AEC CTRL50 0xF0 RW Highlightthre

C

Bit[7]: Not used

0x5651 AEC CTRL51 0x04 RW
Bit[6:0]: Finalsaturatethre[14:8]
on ac

0x5652 AEC CTRL52 0x00 RW Bit[7:0]: Finalsaturatethre[7:0]

Bit[7:0]: r_blackthre1_l[15:8] for long exposure

0x5653 AEC CTRL53 0x04 RW
sub-pixel
W
fid in

Bit[7:0]: r_blackthre1_l[7:0] for long exposure

0x5654 AEC CTRL54 0x00 RW
sub-pixel
en g o

Bit[7:0]: r_blackthre1_s[15:8] for short

0x5655 AEC CTRL55 0x10 RW
exposure sub-pixel
h

Bit[7:0]: r_blackthre1_s[7:0] for short exposure

0x5656 AEC CTRL56 0x00 RW
sub-pixel
tia nly

Bit[7:0]: r_blackthre2_l[15:8] for long exposure

0x5657 AEC CTRL57 0x20 RW
sub-pixel
lf

Bit[7:0]: r_blackthre2_l[7:0] for long exposure

0x5658 AEC CTRL58 0x00 RW
sub-pixel

Bit[7:0]: r_blackthre2_s[15:8] for short

or

0x5659 AEC CTRL59 0x40 RW

exposure sub-pixel

Bit[7:0]: r_blackthre2_s[7:0] for short exposure

0x565A AEC CTRL5A 0x00 RW
sub-pixel

Bit[7]: Not used

0x565B AEC CTRL5B 0x10 RW Bit[6:0]: r_blackweight1_l[6:0] for long
exposure sub-pixel

Bit[7]: Not used

0x565C AEC CTRL5C 0x08 RW Bit[6:0]: r_blackweight1_s[6:0] for short
exposure sub-pixel

Bit[7]: Not used

0x565D AEC CTRL5D 0x14 RW Bit[6:0]: r_blackweight2_l[6:0] for long
exposure sub-pixel

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-31

table 7-7 AEC control registers (sheet 7 of 26)

default
address register name value R/W description
Bit[7]: Not used
0x565E AEC CTRL5E 0x12 RW Bit[6:0]: r_blackweight2_s[6:0] for short
exposure sub-pixel

Bit[7:0]: r_saturatethre1_l[15:8] for long

0x565F AEC CTRL5F 0x08 RW
exposure sub-pixel

Bit[7:0]: r_saturatethre1_l[7:0] for long

0x5660 AEC CTRL60 0x00 RW
exposure sub-pixel

Bit[7:0]: r_saturatethre1_s[15:8] for short

0x5661 AEC CTRL61 0x04 RW
exposure sub-pixel
C

Bit[7:0]: r_saturatethre1_s[7:0] for short

0x5662 AEC CTRL62 0x00 RW
exposure sub-pixel
on ac

Bit[7:0]: r_saturatethre2_l[15:8] for long

0x5663 AEC CTRL63 0x10 RW
exposure sub-pixel

Bit[7:0]: r_saturatethre2_l[7:0] for long

W
fid in

0x5664 AEC CTRL64 0x00 RW

exposure sub-pixel

Bit[7:0]: r_saturatethre2_s[15:8] for short

0x5665 AEC CTRL65 0x20 RW
exposure sub-pixel
en g o

Bit[7:0]: r_saturatethre2_s[7:0] for short

0x5666 AEC CTRL66 0x00 RW
exposure sub-pixel
h

Bit[7]: Not used

tia nly

0x5667 AEC CTRL67 0x10 RW Bit[6:0]: r_saturateweight1_l[6:0] for long

exposure sub-pixel

Bit[7]: Not used

lf

0x5668 AEC CTRL68 0x12 RW Bit[6:0]: r_saturateweight1_s[6:0] for short

exposure sub-pixel
or

Bit[7]: Not used

0x5669 AEC CTRL69 0x12 RW Bit[6:0]: r_saturateweight2_l[6:0] for long
exposure sub-pixel

Bit[7]: Not used

0x566A AEC CTRL6A 0x14 RW Bit[6:0]: r_saturateweight2_s[6:0] for short
exposure sub-pixel

Bit[7]: fix_whole
Bit[6]: fix_eof
Bit[5:4]: fix_select
0x566B AEC CTRL6B 0x00 RW 01: my_l
10: my_s
11: idat
Bit[3:0]: fix_value

Bit[7:1]: Not used

0x566C AEC CTRL6C 0x00 RW
Bit[0]: r_his_en

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-7 AEC control registers (sheet 8 of 26)

default
address register name value R/W description
0x566D AEC CTRL6D 0x00 RW Bit[7:0]: r_his_addr

Bit[7]: Not used

0x566E AEC CTRL6E – R
Bit[6:0]: r_his_data[14:8]

0x566F AEC CTRL6F – R Bit[7:0]: r_his_data[7:0]

0x5680~ AEC CTRL80~

– – Chip Debug
0x56C7 AEC CTRLC7

Bit[7:3]: Not used

Bit[2]: snrgain_sync_en
0x56D0 AEC CTRLD0 0x00 RW
C

Bit[1]: aecagc_debug
Bit[0]: aecagc_man_en
on ac

Bit[7:2]: Not used

0x56D1 AEC CTRLD1 0x00 RW
Bit[1:0]: r_cameragain_l_m[9:8]

0x56D2 AEC CTRLD2 0x10 RW Bit[7:0]: r_cameragain_l_m[7:0]

W
fid in

Bit[7:2]: Not used

0x56D3 AEC CTRLD3 0x00 RW
Bit[1:0]: r_cameragain_s_m[9:8]

0x56D4 AEC CTRLD4 0x10 RW Bit[7:0]: r_cameragain_s_m[7:0]

en g o

0x56D5 AEC CTRLD5 0x00 RW Bit[7:0]: r_exp_l_m[31:24]

h

0x56D6 AEC CTRLD6 0x00 RW Bit[7:0]: r_exp_l_m[23:16]

tia nly

0x56D7 AEC CTRLD7 0x00 RW Bit[7:0]: r_exp_l_m[15:8]

0x56D8 AEC CTRLD8 0x00 RW Bit[7:0]: r_exp_l_m[7:0]

lf

0x56D9 AEC CTRLD9 0x00 RW Bit[7:0]: r_exp_s_m[31:24]

0x56DA AEC CTRLDA 0x00 RW Bit[7:0]: r_exp_s_m[23:16]

or

0x56DB AEC CTRLDB 0x00 RW Bit[7:0]: r_exp_s_m[15:8]

0x56DC AEC CTRLDC 0x00 RW Bit[7:0]: r_exp_s_m[7:0]

Bit[7:3]: Not used

0x56DF AEC CTRLDF 0x02 RW
Bit[2:0]: r_digigain_l_m[10:8]

0x56E0 AEC CTRLE0 0x00 RW Bit[7:0]: r_digigain_l_m[7:0]

Bit[7:3]: Not used

0x56E1 AEC CTRLE1 0x02 RW
Bit[2:0]: r_digigain_s_m[10:8]

0x56E2 AEC CTRLE2 0x00 RW Bit[7:0]: r_digigain_s_m[7:0]

Bit[7:1]: Not used

0x56E3 AEC CTRLE3 0x00 RW
Bit[0]: r_exp_ctrl

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-33

table 7-7 AEC control registers (sheet 9 of 26)

default
address register name value R/W description
Bit[7:4]: Not used
0x56E4 AEC CTRLE4 0x00 RW
Bit[3:0]: r_exp_l_f[11:8]

0x56E5 AEC CTRLE5 0x00 RW Bit[7:0]: r_exp_l_f[7:0]

Bit[7:4]: Not used

0x56E6 AEC CTRLE6 0x00 RW
Bit[3:0]: r_exp_s_f[11:8]

0x56E7 AEC CTRLE7 0x00 RW Bit[7:0]: r_exp_s_f[7:0]

Bit[7:1]: Not used

0x56E8 AEC CTRLE8 0x00 RW
Bit[0]: r_snrgain_l_m[8]
C

0x56E9 AEC CTRLE9 0x00 RW Bit[7:0]: r_snrgain_l_m[7:0]

on ac

Bit[7:1]: Not used

0x56EA AEC CTRLEA 0x00 RW
Bit[0]: r_snrgain_s_m[8]

0x56EB AEC CTRLEB 0x00 RW Bit[7:0]: r_snrgain_s_m[7:0]

W
fid in

Bit[7:1]: Not used

Bit[0]: Non-HDR mode at high temperatures
Set to 0 if HDR mode is on. Set to 1 if
NON-HDR MODE AT
0xC2ED 0x00 RW non-HDR mode is on.
HIGH TEMPERATURES
en g o

This register value will be automatically initialized

by sensor after powering up.
h

tia nly

0xC2EE~
RSVD – – Reserved
0xC2EF

Bit[7:0]: manual_expo11[15:8]
lf

0xC2F0 S_MANUAL_EXP11 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.
or

Bit[7:0]: manual_expo11[7:0]

0xC2F1 S_MANUAL_EXP11 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

Bit[7:0]: manual_expo12[15:8]

0xC2F2 S_MANUAL_EXP12 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

Bit[7:0]: manual_expo12[7:0]

0xC2F3 S_MANUAL_EXP12 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-7 AEC control registers (sheet 10 of 26)

default
address register name value R/W description
Bit[7:0]: manual_expo21[15:8]

0xC2F4 S_MANUAL_EXP21 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

Bit[7:0]: manual_expo21[7:0]

0xC2F5 S_MANUAL_EXP21 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.
C

Bit[7:0]: manual_expo22[15:8]
on ac

0xC2F6 S_MANUAL_EXP22 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

Bit[7:0]: manual_expo22[7:0]
W
fid in

0xC2F7 S_MANUAL_EXP22 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.
en g o

Bit[7:0]: manual_expo31[15:8]
h

0xC2F8 S_MANUAL_EXP31 0x34 RW This register value will be automatically initialized

tia nly

by sensor after powering up. Default value is

random.

Bit[7:0]: manual_expo31[7:0]
lf

0xC2F9 S_MANUAL_EXP31 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.
or

Bit[7:0]: manual_expo32[15:0]

0xC2FA S_MANUAL_EXP32 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

Bit[7:0]: manual_expo32[7:0]

0xC2FB S_MANUAL_EXP22 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

Bit[7:0]: manual_gain11[15:8]

0xC2FC S_MANUAL_GAIN11 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-35

table 7-7 AEC control registers (sheet 11 of 26)

default
address register name value R/W description
Bit[7:0]: manual_gain11[7:0]

0xC2FD S_MANUAL_GAIN11 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

Bit[7:0]: manual_gain12[15:8]

0xC2FE S_MANUAL_GAIN12 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.
C

Bit[7:0]: manual_gain12[7:0]
on ac

0xC2FF S_MANUAL_GAIN12 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

Bit[7:0]: manual_gain21[15:8]
W
fid in

0xC300 S_MANUAL_GAIN21 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.
en g o

Bit[7:0]: manual_gain21[7:0]
h

0xC301 S_MANUAL_GAIN21 – RW This register value will be automatically initialized

tia nly

by sensor after powering up. Default value is

random.

Bit[7:0]: manual_gain22[15:8]
lf

0xC302 S_MANUAL_GAIN22 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.
or

Bit[7:0]: manual_gain22[7:0]

0xC303 S_MANUAL_GAIN22 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

Bit[7:0]: manual_gain31[15:8]

0xC304 S_MANUAL_GAIN31 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

Bit[7:0]: manual_gain31[7:0]

0xC305 S_MANUAL_GAIN31 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-7 AEC control registers (sheet 12 of 26)

default
address register name value R/W description
Bit[7:0]: manual_gain32[15:8]

0xC306 S_MANUAL_GAIN32 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

Bit[7:0]: manual_gain32[7:0]

0xC307 S_MANUAL_GAIN32 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.
C

Bit[7:1]: Not used

Bit[0]: manual_en
on ac

0: Disable
1: Enable
0xC308 S_MANUAL_EN – RW
When register value is 0x00, it means function is
disabled; all other values mean function is enabled.
W
fid in

This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
en g o

Bit[7:3]: Not used

Bit[2]: targetc_manual_en
0: Disable
h

1: Enable
tia nly

Bit[1]: targetb_manual_en
0: Disable
1: Enable
0xC309 S_MANUAL_MODE – RW
Bit[0]: targeta_manual_en
lf

0: Disable
1: Enable
or

This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:2]: Not used

Bit[1:0]: manual_done
00: Write protected
01: Write valid once
0xC30A S_MANUAL_DONE – RW 10: Write valid always

This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-37

table 7-7 AEC control registers (sheet 13 of 26)

default
address register name value R/W description
Bit[7:2]: Not used
Bit[1:0]: Target number
01: AA mode
10: AB mode
0xC450 TARGET_NUM – RW 11: ABC mode

This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

0xC451 HW_STOP_EN 0x00 RW Chip Debug

C

Bit[7:0]: L/S sensitivity ratio[15:8]

on ac

0xC452 LS_SENS_RATIO_1 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: L/S sensitivity ratio[7:0]

W
fid in

0xC453 LS_SENS_RATIO_2 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
en g o

Bit[7:1]: Not used

Bit[0]: Non-HDR mode
h

0: Disable
tia nly

1: Enable
0xC454 NONHDR_EN – RW
When register value is 0x00, it means function is
disabled; all other values mean function is enabled.
lf

This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
or

Bit[7:1]: Not used

Bit[0]: Single exposure mode enable
0: Disable
1: Enable
SINGLE_EXP_MODE_
0xC455 – RW
EN When register value is 0x00, it means function is
disabled; all other values mean function is enabled.
This register value must be initialized by user and
must not be removed from start up sequence.
Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-7 AEC control registers (sheet 14 of 26)

default
address register name value R/W description
Bit[7:1]: Not used
Bit[0]: Fixed ratio mode
0: Disable
1: Enable
0xC456 FIXED_RATIO_EN – RW
When register value is 0x00, it means function is
disabled; all other values mean function is enabled.
This register value must be initialized by user and
must not be removed from start up sequence.
Default value is random.

Bit[7:1]: Not used

C

Bit[0]: Geometric proportion mode

0: Disable
on ac

1: Enable
0xC457 GP_MODE_EN – RW
When register value is 0x00, it means function is
disabled; all other values mean function is enabled.
W
fid in

This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:1]: Not used

en g o

Bit[0]: Night mode

0: Disable
h

1: Enable
tia nly

0xC458 NIGHT_MODE_EN – RW
When register value is 0x00, it means function is
disabled; all other values mean function is enabled.
This register value must be initialized by user and
must not be removed from start up sequence.
lf

Default value is random.

Bit[7:1]: Not used

or

Bit[0]: Only insert frame when in night mode

0: Disable
1: Enable
0xC459 NIGHT_MODE_CTRL – RW
When register value is 0x00, it means function is
disabled; all other values mean function is enabled.
This register value must be initialized by user and
must not be removed from start up sequence.
Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-39

table 7-7 AEC control registers (sheet 15 of 26)

default
address register name value R/W description
Bit[7:1]: Not used
Bit[0]: Allow fractal exposure
0: Disable
1: Enable
0xC45A FRACTAL_EXP_EN – RW
When register value is 0x00, it means function is
disabled; all other values mean function is enabled.
This register value will be automatically initialized
by sensor after powering up. Default value is
random.

Chip Debug
C

0xC45B CHIP DEBUG – – This register value must be initialized by user and
on ac

must not be removed from start up sequence.

Default value is random.

Bit[7:1]: Not used

Bit[0]: Manual gamma mode
W
fid in

0: Disable
1: Enable
0xC45C MANU_GAMMA_EN – RW
When register value is 0x00, it means function is
en g o

disabled; all other values mean function is enabled.

This register value must be initialized by user and
h

must not be removed from start up sequence.

Default value is random.
tia nly

0xC45D CHIP DEBUG – – Chip Debug

Bit[7:2]: Not used

lf

Bit[1:0]: Light source type

00: Frequency is zero or very high
01: 60Hz
or

10: 50Hz
0xC45E BAND_FILTER_FLAG – RW
11: Not valid

This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:1]: Not used

Bit[0]: Banding filter
0: Disable
1: Enable
0xC45F BAND_FILTER_EN – RW
When register value is 0x00, it means function is
disabled; all other values mean function is enabled.
This register value must be initialized by user and
must not be removed from start up sequence.
Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-7 AEC control registers (sheet 16 of 26)

default
address register name value R/W description
Bit[7:1]: Not used
Bit[0]: Short banding filter
0: Disable
1: Enable
0xC460 BAND_FILTER_SHORT – RW
When register value is 0x00, it means function is
disabled; all other values mean function is enabled.
This register value must be initialized by user and
must not be removed from start up sequence.
Default value is random.

Bit[7:1]: Not used

C

Bit[0]: Less than one band exposure mode

0: Disable
on ac

1: Enable
0xC461 LESS_1BAND_EN – RW
When register value is 0x00, it means function is
disabled; all other values mean function is enabled.
W
fid in

This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:1]: Not used

en g o

Bit[0]: Less than one band exposure for short

0: Disable
h

1: Enable
tia nly

0xC462 LESS_1BAND_SHORT – RW
When register value is 0x00, it means function is
disabled; all other values mean function is enabled.
This register value must be initialized by user and
must not be removed from start up sequence.
lf

Default value is random.

0xC463 CHIP DEBUG – – Chip Debug

or

Bit[7:0]: Log target 1[15:8]

0xC464 LOG_TARGET_11 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Log target 1[7:0]

0xC465 LOG_TARGET_12 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Log target 2[15:8]

0xC466 LOG_TARGET_21 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-41

table 7-7 AEC control registers (sheet 17 of 26)

default
address register name value R/W description
Bit[7:0]: Log target 2[7:0]

0xC467 LOG_TARGET_22 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Log target 3[15:8]

0xC468 LOG_TARGET_31 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
C

Bit[7:0]: Log target 3[7:0]

on ac

0xC469 LOG_TARGET_32 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Target of Raw Data for Long 1

W
fid in

0xC46A TARGET_LONG_1 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
en g o

Target of Raw Data for Long 2

h

0xC46B TARGET_LONG_2 – RW This register value must be initialized by user and

tia nly

must not be removed from start up sequence.

Default value is random.

Target of Raw Data for Long 3

lf

0xC46C TARGET_LONG_3 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
or

Target of Raw Data for Short 1

0xC46D TARGET_SHORT_1 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Target of Raw Data for Short 2

0xC46E TARGET_SHORT _2 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Target of Raw Data for Short 3

0xC46F TARGET_SHORT _3 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-7 AEC control registers (sheet 18 of 26)

default
address register name value R/W description
Slow Range for Long Exposure

0xC470 SLOW_RANGE_LONG – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

Slow Range for Short Exposure

0xC471 SLOW_RANGE_SHORT – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.
C

Range Become Stable from Unstable

on ac

0xC472 STABLE_RANGE_IN – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

Range Become Unstable from Stable

W
fid in

0xC473 STABLE_RANGE_OUT – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.
en g o

Fast AEC Adjustment Step for Long Exposure

h

0xC474 FAST_STEP_LONG – RW This register value will be automatically initialized

tia nly

by sensor after powering up. Default value is

random.

Fast AEC Adjustment Step for Short Exposure

lf

0xC475 FAST_STEP_SHORT – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.
or

Slow AEC Adjustment Step for Long Exposure

0xC476 SLOW_STEP_LONG – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

Slow AEC Adjustment Step for Short Exposure

0xC477 SLOW_STEP_SHORT – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

Max Fast Adjustment Ratio

0xC478 MAX_FAST_RATIO – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-43

table 7-7 AEC control registers (sheet 19 of 26)

default
address register name value R/W description
Max Slow Adjustment Ratio

0xC479 MAX_SLOW_RATIO – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

0xC47A~
CHIP DEBUG – – Chip Debug
0xC47B

Bit[7:0]: Max short light exposure[31:24]

0xC47C MAX_SHORT_LE_1 – RW This register value must be initialized by user and

C

must not be removed from start up sequence.

Default value is random.
on ac

Bit[7:0]: Max short light exposure[23:16]

0xC47D MAX_SHORT_LE_2 – RW This register value must be initialized by user and

must not be removed from start up sequence.
W
fid in

Default value is random.

Bit[7:0]: Max short light exposure[15:8]

en g o

0xC47E MAX_SHORT_LE_3 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
h

Bit[7:0]: Max short light exposure[7:0]

tia nly

0xC47F MAX_SHORT_LE_4 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
lf

Bit[7:2]: Not used

Bit[1:0]: Max gain for long[9:8]
or

0xC480 MAX _GAIN_LONG_1 – RW

This register value must be initialized by user and
must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Max gain for long[7:0]

0xC481 MAX _GAIN_LONG_2 – RW This register value must be initialized by user and
must not be removed from start up sequence.
Default value is random.

Bit[7:2]: Not used

Bit[1:0]: Max gain for short[9:8]
0xC482 MAX_GAIN_SHORT_1 – RW
This register value must be initialized by user and
must not be removed from start up sequence.
Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-7 AEC control registers (sheet 20 of 26)

default
address register name value R/W description
Bit[7:0]: Max gain for short[7:0]

0xC483 MAX_GAIN_SHORT_1 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:2]: Not used

Bit[1:0]: Min gain for long[9:8]
0xC484 MIN_ GAIN_LONG_1 – RW
This register value must be initialized by user and
must not be removed from start up sequence.
Default value is random.
C

Bit[7:0]: Min gain for long[7:0]

on ac

0xC485 MIN_ GAIN_LONG_2 – RW This register value must be initialized by user and
must not be removed from start up sequence.
Default value is random.
W
fid in

Bit[7:2]: Not used

Bit[1:0]: Min gain for short[9:8]
0xC486 MIN_GAIN_SHORT_1 – RW
This register value must be initialized by user and
en g o

must not be removed from start up sequence.

Default value is random.
h

Bit[7:0]: Min gain for short[7:0]

tia nly

0xC487 MIN_GAIN_SHORT_2 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
lf

Bit[7:0]: Max exposure for long[15:8]

0xC488 MAX_EXP_LONG_1 – RW This register value must be initialized by user and

or

must not be removed from start up sequence.

Default value is random.

Bit[7:0]: Max exposure for long[7:0]

0xC489 MAX_EXP_LONG_2 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Max exposure for short[15:8]

0xC48A MAX_EXP_SHORT_1 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-45

table 7-7 AEC control registers (sheet 21 of 26)

default
address register name value R/W description
Bit[7:0]: Max exposure for short[7:0]

0xC48B MAX_EXP_SHORT_2 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Min exposure for long[15:8]

0xC48C MIN_EXP_LONG_1 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
C

Bit[7:0]: Min exposure for long[7:0]

on ac

0xC48D MIN_EXP_LONG_2 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Min exposure for short[15:8]

W
fid in

0xC48E MIN_EXP_SHORT_1 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
en g o

Bit[7:0]: Min exposure for short[7:0]

h

0xC48F MIN_EXP_ SHORT_2 – RW This register value must be initialized by user and
tia nly

must not be removed from start up sequence.

Default value is random.

Fixed Ratio, Value+1

lf

0xC490 FIXED_RATIO – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
or

0xC491 CHIP DEBUG – – Chip Debug

B/A Ratio in Gp Mode

0xC492 GP_MODE_RATIO_B2A – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

C/A Ratio in Gp Mode

0xC493 GP_MODE_RATIO_C2A – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

0xC494~
CHIP DEBUG – – Chip Debug
0xC497

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-7 AEC control registers (sheet 22 of 26)

default
address register name value R/W description
Bit[7:0]: Min gamma list 1[15:8]

0xC498 MIN_GAMMA_LIST_11 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Min gamma list 1[7:0]

0xC499 MIN_GAMMA_LIST_12 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
C

Bit[7:0]: Min gamma list 2[15:8]

on ac

0xC49A MIN_GAMMA_LIST_21 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Min gamma list 2[7:0]

W
fid in

0xC49B MIN_GAMMA_LIST_22 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
en g o

Bit[7:0]: Min gamma list 3[15:8]

h

0xC49C MIN_GAMMA_LIST_31 – RW This register value must be initialized by user and

tia nly

must not be removed from start up sequence.

Default value is random.

Bit[7:0]: Min gamma list 3[7:0]

lf

0xC49D MIN_GAMMA_LIST_32 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
or

Bit[7:0]: Max gamma list 1[15:8]

0xC49E MAX_GAMMA_LIST_11 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Max gamma list 1[7:0]

0xC49F MAX_GAMMA_LIST_12 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Max gamma list 2[15:8]

0xC4A0 MAX_GAMMA_LIST_21 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-47

table 7-7 AEC control registers (sheet 23 of 26)

default
address register name value R/W description
Bit[7:0]: Max gamma list 2[7:0]

0xC4A1 MAX_GAMMA_LIST_22 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Max gamma list 3[15:8]

0xC4A2 MAX_GAMMA_LIST_31 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
C

Bit[7:0]: Max gamma list 3[7:0]

on ac

0xC4A3 MAX_GAMMA_LIST_32 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Dynamic range list 1[15:8]

W
fid in

0xC4A4 DR_LIST_11 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
en g o

Bit[7:0]: Dynamic range list 1[7:0]

h

0xC4A5 DR_LIST_12 – RW This register value must be initialized by user and

tia nly

must not be removed from start up sequence.

Default value is random.

Bit[7:0]: Dynamic range list 2[15:8]

lf

0xC4A6 DR_LIST_21 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
or

Bit[7:0]: Dynamic range list 2[7:0]

0xC4A7 DR_LIST_22 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Dynamic range list 3[15:8]

0xC4A8 DR_LIST_31 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Dynamic range list 3[7:0]

0xC4A9 DR_LIST_32 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-7 AEC control registers (sheet 24 of 26)

default
address register name value R/W description
Bit[7:0]: Band filter value for 60Hz[15:8]

0xC4AA BAND_VALUE_60HZ_1 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Band filter value for 60Hz[7:0]

0xC4AB BAND_VALUE_60HZ_2 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
C

Bit[7:0]: Band filter value for 50Hz[15:8]

on ac

0xC4AC BAND_VALUE_50HZ_1 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Band filter value for 50Hz[7:0]

W
fid in

0xC4AD BAND_VALUE_50HZ_2 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
en g o

0xC4AE~
CHIP DEBUG – – Chip Debug
0xC4B0
h

Min Dynamic Ratio

tia nly

0xC4B1 MIN_DR_RATIO 0x02 RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.
lf

Bit[7:0]: Max dynamic ratio[15:8]

or

0xC4B2 MAX_DR_RATIO_1 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

Bit[7:0]: Max dynamic ratio[7:0]

0xC4B3 MAX_DR_RATIO_2 – RW This register value will be automatically initialized

by sensor after powering up. Default value is
random.

Bit[7:0]: Sensor clock ratio[15:8]

0xC514 SENSOR_CLK_RATIO_1 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-49

table 7-7 AEC control registers (sheet 25 of 26)

default
address register name value R/W description
Bit[7:0]: Sensor clock ratio[7:0]

0xC515 SENSOR_CLK_RATIO_2 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

0xC516 CHIP DEBUG – – Chip Debug

Bit[7:0]: VTS[15:8]

0xC518 VTS_ADDR_1 – RW This register value must be initialized by user and

must not be removed from start up sequence.
C

Default value is random.

Bit[7:0]: VTS[7:0]
on ac

0xC519 VTS_ADDR_2 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
W
fid in

0xC51A~
CHIP DEBUG – – Chip Debug
0xC51B

0x5A00~
en g o

AEC_R – R Debug Information for AEC Control

0x5A03
h

0x5C00 AEC_RW00 – R Bit[7:0]: Exposure long[31:24]

tia nly

0x5C01 AEC_RW01 – R Bit[7:0]: Exposure long[23:16]

0x5C02 AEC_RW02 – R Bit[7:0]: Exposure long[15:8]

lf

0x5C03 AEC_RW03 – R Bit[7:0]: Exposure long[7:0]

0x5C04 AEC_RW04 – R Bit[7:0]: Exposure short[31:24]

or

0x5C05 AEC_RW05 – R Bit[7:0]: Exposure short[23:16]

0x5C06 AEC_RW06 – R Bit[7:0]: Exposure short[15:8]

0x5C07 AEC_RW07 – R Bit[7:0]: Exposure short[7:0]

0x5C08 AEC_RW08 – R Bit[7:0]: add_vts[15:8]

0x5C09 AEC_RW09 – R Bit[7:0]: add_vts[7:0]

Bit[7:3]: Not used

0x5C0A AEC_RW0A – R Bit[2]: Evenframeflag
Bit[1:0]: Targettag[1:0]

Bit[7:1]: Not used

0x5C0C AEC_RW0C – R
Bit[0]: SNRgain long[8]

0x5C0D AEC_RW0D – R Bit[7:0]: SNRgain long[7:0]

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-7 AEC control registers (sheet 26 of 26)

default
address register name value R/W description
Bit[7:1]: Not used
0x5C0E AEC_RW0E – R
Bit[0]: SNRgain short[8]

0x5C0F AEC_RW0F – R Bit[7:0]: SNRgain short[7:0]

Bit[7:2]: Not used

0x5C10 AEC_RW10 – R
Bit[1:0]: PcameraGain long[9:8]

0x5C11 AEC_RW11 – R Bit[7:0]: PcameraGain long[7:0]

Bit[7:2]: Not used

0x5C12 AEC_RW12 – R
Bit[1:0]: PcameraGain short[9:8]
C

0x5C13 AEC_RW13 – R Bit[7:0]: PcameraGain short[7:0]

on ac

Bit[7:2]: Not used

0x5C14 AEC_RW14 – R
Bit[1:0]: PdigiGain long[9:8]

0x5C15 AEC_RW15 – R Bit[7:0]: PdigiGain long[7:0]

W
fid in

Bit[7:2]: Not used

0x5C16 AEC_RW16 – R
Bit[1:0]: PdigiGain short[9:8]

0x5C17 AEC_RW17 – R Bit[7:0]: PdigiGain short[7:0]

en g o

7.8 ISP control [0x5000 ~ 0x500E, 0x503B ~ 0x503E, 0x5040 ~ 0x5044]

h

tia nly

table 7-8 ISP control registers (sheet 1 of 4)

lf

default
address register name value R/W description
or

Bit[7]: Color matrix enable

Bit[6]: Color interpolation enable
Bit[5]: Denoise enable
Bit[4]: White defect pixel correction enable
0x5000 ISP RW00 0xFF RW
Bit[3]: Black defect pixel correction enable
Bit[2]: AWB statistic enable
Bit[1]: AWB gain enable
Bit[0]: Lens shading correction enable

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-51

table 7-8 ISP control registers (sheet 2 of 4)

default
address register name value R/W description
Bit[7]: Data and its weight synchronization
enable
Bit[6]: Black/white mode enable
Bit[5]: Dark level filter enable
0x5001 ISP RW01 0xBF RW Bit[4]: Buffer control enable
Bit[3]: AEC enable
Bit[2]: Tone mapping enable
Bit[1]: Normalize enable
Bit[0]: Long-short combination enable

Bit[7]: OTP manual offset enable

Bit[6]: OTP function enable
C

Bit[5]: ALU function enable

Bit[4]: CT AWB function enable
0x5002 ISP RW02 0x7E RW
on ac

Bit[3]: Digital gain enable

Bit[2]: Window border cut enable
Bit[1]: Dithering enable
Bit[0]: Chip debug
W
fid in

Bit[7:5]: Not used

Bit[4]: YUV444to422_drop
Bit[3]: Latch_sel
0: Pre_sof
en g o

1: VSYNC
Bit[2:0]: EOF_sel
h

000: AEC_done
0x5003 ISP RW03 0x04 RW
001: Simple_awb_done
tia nly

010: Tone_mapping_done
011: Combine_done
100: AEC_done and
simple_AWB_done and
lf

tone_mapping_done and
combine_done
or

Bit[7:5]: Not used

Bit[4]: Auto window enable
0: Manually set image window for
DSP blocks
0x5004 ISP RW04 0x14 RW
1: Automatically handle image
window
Bit3]: Not used
Bit[2:0]: Dummy line number for ISP

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-8 ISP control registers (sheet 3 of 4)

default
address register name value R/W description
Bit[7]: Vertical subsampling enable
0: Disable
1: Enable
Bit[6]: Lens shading correction center option
0: Manually set by register
1: Automatically set based on image
window
Bit[5]: Output row in drop mode of
subsampling
0: First row
1: Second row
C

Bit[4]: Output column in drop mode of

subsampling
0: First pair
on ac

0x5005 ISP RW05 0x08 RW

1: Second pair
Bit[3]: Average enable in non-drop mode of
subsampling
0: Sum
W
fid in

1: Average
Bit[2]: Green/Y channel subsampling mode
0: Non-drop
1: Drop
en g o

Bit[1]: RB/UV channel subsampling mode

0: Non-drop
1: Drop
h

Bit[0]: Subsampling mode enable

tia nly

0: Full resolution
1: Subsampling

Bit[7:6]: raw_mode_man
lf

Bit[5:4]: yuv_mode_man
Bit[3]: raw_mode_man_en
0x5006 ISP RW06 0x00 RW
Bit[2]: yuv_mode_man_en
or

Bit[1]: yuv_en_man
Bit[0]: yuv_en_man enable

Bit[7:3]: Not used

0x5007 ISP RW07 0x00 RW
Bit[2:0]: isp_x_offset[10:8]

0x5008 ISP RW08 0x00 RW Bit[7:0]: isp_x_offset[7:0]

Bit[7:2]: Not used

0x5009 ISP RW09 0x00 RW
Bit[1:0]: isp_y_offset[9:8]

0x500A ISP RW10 0x00 RW Bit[7:0]: isp_y_offset[7:0]

Bit[7:3]: Not used

0x500B ISP RW11 0x00 RW
Bit[2:0]: otp_x_offset[10:8]

0x500C ISP RW12 0x00 RW Bit[7:0]: otp_x_offset[7:0]

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-53

table 7-8 ISP control registers (sheet 4 of 4)

default
address register name value R/W description
Bit[7:2]: Not used
0x500D ISP RW13 0x00 RW
Bit[1:0]: otp_y_offset[9:8]

0x500E ISP RW14 0x00 RW Bit[7:0]: otp_y_offset[7:0]

Bit[7:2]: Not used

0x503B ISP RW59 0x00 RW
Bit[1:0]: line_int_vsize[9:8]

0x503C ISP RW60 0x02 RW Bit[7:0]: line_int_vsize[7:0]

Bit[7]: pre_isp_test_en_i
Bit[6]: Not used
C

Bit[5:4]: pre_isp_bar_style_i
0x503D ISP RW61 0x00 RW Bit[3]: Not used
Bit[2]: pre_isp_rolling_i
on ac

Bit[1]: pre_isp_isp_test_i
Bit[0]: pre_isp_rnd_same_i

Bit[7:4]: pre_isp_seed_i
W
fid in

Bit[3]: pre_isp_squ_bw_i
0x503E ISP RW62 0x00 RW
Bit[2]: pre_isp_trans_i
Bit[1:0]: pre_isp_test_sel_i

0x5040~
en g o

ISP RO – R Debug Information for ISP Control

0x5043

0x5044 ISP RW68 0x00 RW Bit[7:0]: isp_risc_debug[7:0]

h

tia nly

7.9 LENC control [0x5080 ~ 0x5098, 0x509C ~ 0x50B8]

lf

table 7-9 LENC control registers (sheet 1 of 4)

or

default
address register name value R/W description
Bit[7]: Not used
Bit[6]: Gain manual mode enable
0: Use auto gain
1: Use manual gain set by user
0x5080 LENC CTRL0 0x10 RW Bit[5]: Auto LENC switch enable
0: LENC gain is fixed
1: LENC gain adjusts according to
sensor gain
Bit[4:0]: Manual gain input

Bit[7:3]: Not used

0x5081 LENC CTRL1 0x00 RW
Bit[2:0]: long_red_x0[10:8]

0x5082 LENC CTRL2 0x00 RW Bit[7:0]: long_red_x0[7:0]

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-9 LENC control registers (sheet 2 of 4)

default
address register name value R/W description
Bit[7:2]: Not used
0x5083 LENC CTRL3 0x00 RW
Bit[1:0]: long_red_y0[9:8]

0x5084 LENC CTRL4 0x00 RW Bit[7:0]: long_red_y0[7:0]

Bit[7]: Not used

0x5085 LENC CTRL5 0x00 RW
Bit[6:0]: long_red_a1

Bit[7:4]: Not used

0x5086 LENC CTRL6 0x01 RW
Bit[3:0]: long_red_a2

Bit[7]: long_red_sign
0x5087 LENC CTRL7 0x00 RW
C

Bit[6:0]: long_red_b1

Bit[7:4]: Not used

0x5088 LENC CTRL8 0x01 RW
on ac

Bit[3:0]: long_red_b2

Bit[7:3]: Not used

0x5089 LENC CTRL9 0x00 RW
Bit[2:0]: long_grn_x0[10:8]
W
fid in

0x508A LENC CTRL10 0x00 RW Bit[7:0]: long_grn_x0[7:0]

Bit[7:2]: Not used

0x508B LENC CTRL11 0x00 RW
Bit[1:0]: long_grn_y0[9:8]
en g o

0x508C LENC CTRL12 0x00 RW Bit[7:0]: long_grn_y0[7:0]

Bit[7]: Not used

h

0x508D LENC CTRL13 0x00 RW

Bit[6:0]: long_grn_a1
tia nly

Bit[7:4]: Not used

0x508E LENC CTRL14 0x01 RW
Bit[3:0]: long_grn_a2
lf

Bit[7]: long_grn_sign
0x508F LENC CTRL15 0x00 RW
Bit[6:0]: long_grn_b1

Bit[7:4]: Not used

or

0x5090 LENC CTRL16 0x01 RW

Bit[3:0]: long_grn_b2

Bit[7:3]: Not used

0x5091 LENC CTRL17 0x00 RW
Bit[2:0]: long_blu_x0[10:8]

0x5092 LENC CTRL18 0x00 RW Bit[7:0]: long_blu_x0[7:0]

Bit[7:2]: Not used

0x5093 LENC CTRL19 0x00 RW
Bit[1:0]: long_blu_y0[9:8]

0x5094 LENC CTRL20 0x00 RW Bit[7:0]: long_blu_y0[7:0]

Bit[7]: Not used

0x5095 LENC CTRL21 0x00 RW
Bit[6:0]: long_blu_a1

Bit[7:4]: Not used

0x5096 LENC CTRL22 0x01 RW
Bit[3:0]: long_blu_a2

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-55

table 7-9 LENC control registers (sheet 3 of 4)

default
address register name value R/W description
Bit[7]: long_blu_sign
0x5097 LENC CTRL23 0x0 RW
Bit[6:0]: long_blu_b1

Bit[7:4]: Not used

0x5098 LENC CTRL24 0x01 RW
Bit[3:0]: long_blu_b2

Bit[7:5]: Not used

0x509C LENC CTRL28 0x00 RW
Bit[4:0]: Min LENC gain

Bit[7:2]: Not used

0x509D LENC CTRL29 0x00 RW Bit[1:0]: Sensor gain1[9:8] (must be less than
0x200)
C

0x509E LENC CTRL30 0x00 RW Bit[7:0]: Sensor gain1[7:0]

on ac

Bit[7:2]: Not used

0x509F LENC CTRL31 0x00 RW Bit[1:0]: Sensor gain2[9:8] (must be less than
0x200)

0x50A0 LENC CTRL32 0x00 RW Bit[7:0]: Sensor gain2[7:0]

W
fid in

Bit[7:3]: Not used

0x50A1 LENC CTRL33 0x00 RW
Bit[2:0]: short_red_x0[10:8]
en g o

0x50A2 LENC CTRL34 0x00 RW Bit[7:0]: short_red_x0[7:0]

Bit[7:2]: Not used

0x50A3 LENC CTRL35 0x00 RW
h

Bit[1:0]: short_red_y0[9:8]
tia nly

0x50A4 LENC CTRL36 0x00 RW Bit[7:0]: short_red_y0[7:0]

Bit[7]: Not used

0x50A5 LENC CTRL37 0x00 RW
Bit[6:0]: short_red_a1
lf

Bit[7:4]: Not used

0x50A6 LENC CTRL38 0x01 RW
Bit[3:0]: short_red_a2
or

Bit[7]: short_red_sign
0x50A7 LENC CTRL39 0x00 RW
Bit[6:0]: short_red_b1

Bit[7:4]: Not used

0x50A8 LENC CTRL40 0x01 RW
Bit[3:0]: short_red_b2

Bit[7:3]: Not used

0x50A9 LENC CTRL41 0x00 RW
Bit[2:0]: short_grn_x0[10:8]

0x50AA LENC CTRL42 0x00 RW Bit[7:0]: short_grn_x0[7:0]

Bit[7:2]: Not used

0x50AB LENC CTRL43 0x00 RW
Bit[1:0]: short_grn_y0[9:8]

0x50AC LENC CTRL44 0x00 RW Bit[7:0]: short_grn_y0[7:0]

Bit[7]: Not used

0x50AD LENC CTRL45 0x00 RW
Bit[6:0]: short_grn_a1

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-9 LENC control registers (sheet 4 of 4)

default
address register name value R/W description
Bit[7:4]: Not used
0x50AE LENC CTRL46 0x01 RW
Bit[3:0]: short_grn_a2

Bit[7]: short_grn_sign
0x50AF LENC CTRL47 0x00 RW
Bit[6:0]: short_grn_b1

Bit[7:4]: Not used

0x50B0 LENC CTRL48 0x01 RW
Bit[3:0]: short_grn_b2

Bit[7:3]: Not used

0x50B1 LENC CTRL49 0x00 RW
Bit[2:0]: short_blu_x0[10:8]

0x50B2 LENC CTRL50 0x00 RW Bit[7:0]: short_blu_x0[7:0]

C

Bit[7:2]: Not used

0x50B3 LENC CTRL51 0x00 RW
on ac

Bit[1:0]: short_blu_y0[9:8]

0x50B4 LENC CTRL52 0x00 RW Bit[7:0]: short_blu_y0[7:0]

Bit[7]: Not used

W
fid in

0x50B5 LENC CTRL53 0x00 RW

Bit[6:0]: short_blu_a1

Bit[7:4]: Not used

0x50B6 LENC CTRL54 0x01 RW
Bit[3:0]: short_blu_a2
en g o

Bit[7]: short_blu_sign
0x50B7 LENC CTRL55 0x00 RW
Bit[6:0]: short_blu_b1
h

Bit[7:4]: Not used

tia nly

0x50B8 LENC CTRL56 0x01 RW

Bit[3:0]: short_blu_b2

7.10 AWB [0x5100 ~ 0x5718, 0xC4B8 ~ 0xC4DF, 0x5AB0 ~ 0x5D1B]

lf
or

table 7-10 AWB control registers (sheet 1 of 15)

default
address register name value R/W description
Bit[7:2]: Not used
0x5100 GAIN AWB CTRL0 0x00 RW
Bit[1:0]: manual_gain_b_long[9:8]

0x5101 GAIN AWB CTRL1 0x80 RW Bit[7:0]: manual_gain_b_long[7:0]

Bit[7:2]: Not used

0x5102 GAIN AWB CTRL2 0x00 RW
Bit[1:0]: manual_gain_gb_long[9:8]

0x5103 GAIN AWB CTRL3 0x80 RW Bit[7:0]: manual_gain_gb_long[7:0]

Bit[7:2]: Not used

0x5104 GAIN AWB CTRL4 0x00 RW
Bit[1:0]: manual_gain_gr_long[9:8]

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-57

table 7-10 AWB control registers (sheet 2 of 15)

default
address register name value R/W description
0x5105 GAIN AWB CTRL5 0x80 RW Bit[7:0]: manual_gain_gr_long[7:0]

Bit[7:2]: Not used

0x5106 GAIN AWB CTRL6 0x00 RW
Bit[1:0]: manual_gain_r_long[9:8]

0x5107 GAIN AWB CTRL7 0x80 RW Bit[7:0]: manual_gain_r_long[7:0]

Bit[7:2]: Not used

0x5108 GAIN AWB CTRL8 0x00 RW
Bit[1:0]: manual_offset_b_long[9:8]

0x5109 GAIN AWB CTRL9 0x00 RW Bit[7:0]: manual_offset_b_long[7:0]

Bit[7:2]: Not used

C

0x510A GAIN AWB CTRL10 0x00 RW

Bit[1:0]: manual_offset_gb_long[9:8]
on ac

0x510B GAIN AWB CTRL11 0x00 RW Bit[7:0]: manual_offset_gb_long[7:0]

Bit[7:2]: Not used

0x510C GAIN AWB CTRL12 0x00 RW
Bit[1:0]: manual_offset_gr_long[9:8]
W
fid in

0x510D GAIN AWB CTRL13 0x00 RW Bit[7:0]: manual_offset_gr_long[7:0]

Bit[7:2]: Not used

0x510E GAIN AWB CTRL14 0x00 RW
Bit[1:0]: manual_offset_r_long[9:8]
en g o

0x510F GAIN AWB CTRL15 0x00 RW Bit[7:0]: manual_offset_r_long[7:0]

Bit[7:2]: Not used

h

0x5110 GAIN AWB CTRL16 0x00 RW

Bit[1:0]: manual_gain_b_short[9:8]
tia nly

0x5111 GAIN AWB CTRL17 0x80 RW Bit[7:0]: manual_gain_b_short[7:0]

Bit[7:2]: Not used

0x5112 GAIN AWB CTRL18 0x00 RW
lf

Bit[1:0]: manual_gain_gb_short[9:8]

0x5113 GAIN AWB CTRL19 0x80 RW Bit[7:0]: manual_gain_gb_short[7:0]

or

Bit[7:2]: Not used

0x5114 GAIN AWB CTRL20 0x00 RW
Bit[1:0]: manual_gain_gr_short[9:8]

0x5115 GAIN AWB CTRL21 0x80 RW Bit[7:0]: manual_gain_gr_short[7:0]

Bit[7:2]: Not used

0x5116 GAIN AWB CTRL22 0x00 RW
Bit[1:0]: manual_gain_r_short[9:8]

0x5117 GAIN AWB CTRL23 0x80 RW Bit[7:0]: manual_gain_r_short[7:0]

Bit[7:2]: Not used

0x5118 GAIN AWB CTRL24 0x00 RW
Bit[1:0]: manual_offset_b_short[9:8]

0x5119 GAIN AWB CTRL25 0x00 RW Bit[7:0]: manual_offset_b_short[7:0]

Bit[7:2]: Not used

0x511A GAIN AWB CTRL26 0x00 RW
Bit[1:0]: manual_offset_gb_short[9:8]

0x511B GAIN AWB CTRL27 0x00 RW Bit[7:0]: manual_offset_gb_short[7:0]

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-10 AWB control registers (sheet 3 of 15)

default
address register name value R/W description
Bit[7:2]: Not used
0x511C GAIN AWB CTRL28 0x00 RW
Bit[1:0]: manual_offset_gr_short[9:8]

0x511D GAIN AWB CTRL29 0x00 RW Bit[7:0]: manual_offset_gr_short[7:0]

Bit[7:2]: Not used

0x511E GAIN AWB CTRL30 0x00 RW
Bit[1:0]: manual_offset_r_short[9:8]

0x511F GAIN AWB CTRL31 0x00 RW Bit[7:0]: manual_offset_r_short[7:0]

Bit[7:1]: Not used

Bit[0]: White balance (WB) mode select
0x5120 GAIN AWB CTRL32 0x00 RW
C

0: Auto mode
1: Manual mode
on ac

0x5580 AWB CT CTRL0 0xFF RW Bit[7:0]: awb_b_block_l

Bit[7:6]: step_local
Bit[5:4]: step_fast
Bit[3]: slop_8x_l
W
fid in

0x5581 AWB CT CTRL1 0x5B RW

Bit[2]: slop_4x_l
Bit[1]: one_zone
Bit[0]: avg_all
en g o

0x5582 DEBUG MODE – – Debug Mode

Bit[7]: slop_8x_s
h

Bit[6]: slop_4x_s
tia nly

Bit[5]: Not used

0x5583 AWB CT CTRL3 0x10 RW
Bit[4]: awb_simf
Bit[3:2]: awb_win
Bit[1:0]: Not used
lf

0x5584~
DEBUG MODE – – Debug Mode
0x5585
or

Bit[7:0]: AWB_M_RNG[7:0]
Tolerance of AWB_M_X and AWB_M_Y
in middle color temperature range.
0x5586 AWB_M_RNG 0x10 RW
Too small of a tolerance results in
unstable AWB, while too great of a
tolerance results in inaccurate AWB.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-59

table 7-10 AWB control registers (sheet 4 of 15)

default
address register name value R/W description
Bit[7:0]: AWB_L_XRNG[7:0]
Tolerance of AWB_L_X in low color
temperature range, where AWB_L_X is X
characteristics of gray object in low color
temperature range.
0x5587 AWB_L_XRNG 0x10 RW
Too small of a tolerance results in
unstable AWB, while too great of a
tolerance results in inaccurate AWB.
Typical value ranges from 0x08~0x18.

Bit[7:0]: AWB_H_YRNG[7:0]
C

Tolerance of AWB_H_Y in low color

temperature range, where AWB_H_Y is Y
on ac

characteristics of gray object in high color

temperature range.
0x5588 AWB_H_YRNG 0x10 RW
Too small of a tolerance results in
W
fid in

unstable AWB, while too great of a

tolerance results in inaccurate white
balance. Typical value ranges from
0x08~0x10.
en g o

Bit[7:0]: AWB_M_X[7:0]
X characteristics of gray object in middle
h

color temperature range.

tia nly

When AWB_M_X increases, gray will

shift toward blue in low color temperature
light, or red in high color temperature
0x5589 AWB_M_X 0x40 RW
light. When AWB_M_X decreases, gray
lf

will shift toward yellow in low color

temperature light, or cyan in high color
temperature light. If AWB_M_X is too big
or

or too small, AWB algorithm may fail to

identify gray object and result is not stable
and unpredictable.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-10 AWB control registers (sheet 5 of 15)

default
address register name value R/W description
Bit[7:0]: AWB_M_Y[7:0]
Y characteristics of gray object in middle
color temperature range.

When AWB_M_Y increases, gray will

shift toward blue in low color temperature
light, or red in high color temperature
0x558A AWB_M_Y 0x40 RW
light. When AWB_M_Y decreases, gray
will shift toward yellow in low color
temperature light, or cyan in high color
temperature light. If AWB_M_Y is too big
C

or too small, AWB algorithm will fail to

identify gray object and result is not stable
and unpredictable
on ac

Bit[7:0]: AWB_L_K
K characteristics of gray object in low
color temperature range
W
fid in

When AWB_L_K increases/decreases,

0x558B AWB_L_K 0x00 RW
gray color will slightly shift toward
yellow/blue, respectively, in low color
en g o

temperature range.
In general, AWB_L_K should be no less
than 0x80
h

Bit[7:0]: AWB_H_K
tia nly

K characteristics of gray object in high

color temperature range
0x558C AWB_H_K 0x00 RW
When AWB_H_K increases/decreases,
lf

gray color will slightly shift toward

cyan/red, respectively, in high color
temperature range.
or

Bit[7:0]: AWB_H_LMT[7:0]
Lower limit of AWB_H_X, where
AWB_H_X is X characteristics of gray
object in high color temperature range.
0x558D AWB_H_LMT 0x00 RW
Smaller AWB_H_LMT covers greater
upper limit of color temperature; however,
it also results in less accurate white
balance

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-61

table 7-10 AWB control registers (sheet 6 of 15)

default
address register name value R/W description
Bit[7:0]: AWB_L_LMT[7:0]
Lower limit of AWB_L_Y, where
AWB_L_Y is Y characteristics of gray
object in low color temperature range.
0x558E AWB_L_LMT 0x00 RW
Smaller AWB_L_LMT covers smaller
lower limit of color temperature; however,
it also results in less accurate white
balance.

Bit[7:0]: AWB_DBG1
0x558F AWB_DBG1 0x20 RW Debug control register, not effective in
C

normal usage
on ac

Bit[7:0]: AWB_DBG2
0x5590 AWB_DBG2 0x20 RW Debug control register, not effective in
normal usage

Bit[7:0]: AWB_DATA_ULMT
W
fid in

Pixels with output value greater than

0x5591 AWB_DATA_ULMT 0xFF RW
AWB_DATA_ULMT are excluded in AWB
statistics
en g o

Bit[7:0]: AWB_DATA_LLMT
Pixels with output value smaller than
0x5592 AWB_DATA_LLMT 0x00 RW
AWB_DATA_LLMT are excluded in AWB
h

statistics
tia nly

Bit[7]: awb_gain_m
Bit[6]: Not used
Bit[5]: awb_freeze
Bit[4]: Not used
lf

Bit[3:2]: awb_sim_sel
0x5596 AWB CT CTRL22 0x03 RW 00: awb_simple from after awb_gain
01: awb_simple from after raw_gma
or

10: awb_simple from after HDR

11: awb_simple from after awb_gain
Bit[1]: fast_enable
Bit[0]: awb_bias_stat

0x5593~
DEBUG MODE – – Debug Registers
0x5595

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-10 AWB control registers (sheet 7 of 15)

default
address register name value R/W description
Bit[7]: awb_gain_m
Bit[6]: Not used
Bit[5]: awb_freeze
Bit[4]: Not used
Bit[3:2]: awb_sim_sel
0x5596 AWB CT CTRL22 0x03 RW 00: awb_simple from after awb_gain
01: awb_simple from after raw_gma
10: awb_simple from after HDR
11: awb_simple from after awb_gain
Bit[1]: fast_enable
Bit[0]: awb_bias_stat
C

0x5597 AWB CT CTRL23 0x02 RW Bit[7:0]: Local limit

on ac

0x559E AWB CT CTRL30 0xFF RW Bit[7:0]: awb_b_block_s

Bit[7:0]: AWB_M_RNG[7:0]
Tolerance of AWB_M_X and AWB_M_Y
in middle color temperature range
W
fid in

0x559F AWB_M_RNG 0x10 RW

Too small of a tolerance results in
unstable AWB, while too great of a
tolerance results in inaccurate AWB.
en g o

Bit[7]: bsum_l_fix
Bit[6]: gsum_l_fix
h

Bit[5]: rsum_l_fix
tia nly

Bit[4]: bsum_s_fix
0x55AF AWB CT CTRL41 0x00 RW
Bit[3]: gsum_s_fix
Bit[2]: rsum_s_fix
Bit[1]: allcnt_l_fix
lf

Bit[0]: allcnt_s_fix

Bit[7:0]: AWB_L_XRNG[7:0]
Tolerance of AWB_L_X in low color
or

temperature range, where AWB_L_X is X

characteristics of gray object in low color
temperature range.
0x55A0 AWB_L_XRNG 0x10 RW
Too small of a tolerance results in
unstable AWB, while too great of a
tolerance results in inaccurate AWB.
Typical value ranges from 0x08~0x18.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-63

table 7-10 AWB control registers (sheet 8 of 15)

default
address register name value R/W description
Bit[7:0]: AWB_H_YRNG[7:0]
Tolerance of AWB_H_Y in low color
temperature range, where AWB_H_Y is Y
characteristics of gray object in high color
temperature range.
0x55A1 AWB_H_YRNG 0x10 RW
Too small of a tolerance results in
unstable AWB, while too great of a
tolerance results in inaccurate white
balance. Typical value ranges from
0x08~0x10.
C

Bit[7:0]: AWB_M_X[7:0]
X characteristics of gray object in middle
on ac

color temperature range.

When AWB_M_X increases, gray will

shift toward blue in low color temperature
W
fid in

light, or red in high color temperature

0x55A2 AWB_M_X 0x40 RW
light. When AWB_M_X decreases, gray
will shift toward yellow in low color
temperature light, or cyan in high color
en g o

temperature light. If AWB_M_X is too big

or too small, AWB algorithm may fail to
identify gray object and result is not stable
h

and unpredictable.
tia nly

Bit[7:0]: AWB_M_Y[7:0]
Y characteristics of gray object in middle
color temperature range.
lf

When AWB_M_Y increases, gray will

shift toward blue in low color temperature
light, or red in high color temperature
or

0x55A3 AWB_M_Y 0x40 RW

light. When AWB_M_Y decreases, gray
will shift toward yellow in low color
temperature light, or cyan in high color
temperature light. If AWB_M_Y is too big
or too small, AWB algorithm will fail to
identify gray object and result is not stable
and unpredictable

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-10 AWB control registers (sheet 9 of 15)

default
address register name value R/W description
Bit[7:0]: AWB_L_K
K characteristics of gray object in low
color temperature range

When AWB_L_K increases/decreases,

0x55A4 AWB_L_K 0x00 RW
gray color will slightly shift toward
yellow/blue, respectively, in low color
temperature range.
In general, AWB_L_K should be no less
than 0x80

Bit[7:0]: AWB_H_K
C

K characteristics of gray object in high

color temperature range
on ac

0x55A5 AWB_H_K 0x00 RW

When AWB_H_K increases/decreases,
gray color will slightly shift toward
cyan/red, respectively, in high color
W
fid in

temperature range.

Bit[7:0]: AWB_H_LMT[7:0]
Lower limit of AWB_H_X, where
AWB_H_X is X characteristics of gray
en g o

object in high color temperature range.

0x55A6 AWB_H_LMT 0x00 RW
h

Smaller AWB_H_LMT covers greater

upper limit of color temperature; however,
tia nly

it also results in less accurate white

balance

Bit[7:0]: AWB_L_LMT[7:0]
lf

Lower limit of AWB_L_Y, where

AWB_L_Y is Y characteristics of gray
object in low color temperature range.
or

0x55A7 AWB_L_LMT 0x00 RW

Smaller AWB_L_LMT covers smaller
lower limit of color temperature; however,
it also results in less accurate white
balance.

Bit[7:0]: AWB_DBG1
0x55A8 AWB_DBG1 0x20 RW Debug control register, not effective in
normal usage

Bit[7:0]: AWB_DBG2
0x55A9 AWB_DBG2 0x20 RW Debug control register, not effective in
normal usage

Bit[7:0]: AWB_DATA_ULMT
Pixels with output value greater than
0x55AA AWB_DATA_ULMT 0xFF RW
AWB_DATA_ULMT are excluded in AWB
statistics

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-65

table 7-10 AWB control registers (sheet 10 of 15)

default
address register name value R/W description
Bit[7:0]: AWB_DATA_LLMT
Pixels with output value smaller than
0x55AB AWB_DATA_LLMT 0x00 RW
AWB_DATA_LLMT are excluded in AWB
statistics

0x55AC~
AWB CTRL – – Debug Registers
0x55AE

Bit[7]: bsum_l_fix
Bit[6]: gsum_l_fix
Bit[5]: rsum_l_fix
Bit[4]: bsum_s_fix
0x55AF AWB CT CTRL41
C

0x00 RW
Bit[3]: gsum_s_fix
Bit[2]: rsum_s_fix
on ac

Bit[1]: allcnt_l_fix
Bit[0]: allcnt_s_fix

Bit[7:6]: Not used

Bit[5]: fix_whole
W
fid in

0x55B0 AWB CT CTRL42 0x00 RW

Bit[4]: fix_eof
Bit[3:0]: fix_value

Bit[7:2]: Not used

0x5700 AWB CTRL0 0x00 RW
en g o

Bit[1:0]: midtone_ythre_l1[9:8]

Bit[7:0]: midtone_ythre_l1[7:0]
h

0x5701 AWB CTRL1 0x10 RW (midtone_ythre_l1+midtone_ythre_l2 ≤

0x3FF)
tia nly

Bit[7:2]: Not used

0x5702 AWB CTRL2 0x01 RW
Bit[1:0]: midtone_ythre_l2[9:8]
lf

Bit[7:0]: midtone_ythre_l2[7:0]
0x5703 AWB CTRL3 0x00 RW (midtone_ythre_l1+midtone_ythre_l2 ≤
0x3FF)
or

Bit[7:2]: Not used

0x5704 AWB CTRL4 0x03 RW
Bit[1:0]: midtone_ythre_h1[9:8]

Bit[7:0]: midtone_ythre_h1[7:0]
0x5705 AWB CTRL5 0x68 RW (midtone_ythre_h1+midtone_ythre_h2 ≤
0x3FF)

Bit[7:2]: Not used

0x5706 AWB CTRL6 0x00 RW
Bit[1:0]: midtone_ythre_h2[9:8]

Bit[7:0]: midtone_ythre_h2[7:0]
0x5707 AWB CTRL7 0x80 RW (midtone_ythre_h1+midtone_ythre_h2 ≤
0x3FF)

Bit[7:2]: Not used

0x5708 AWB CTRL8 0x00 RW
Bit[1:0]: gamma_ythre_l[9:8]

0x5709 AWB CTRL9 0x20 RW Bit[7:0]: gamma_ythre_l[7:0]

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-10 AWB control registers (sheet 11 of 15)

default
address register name value R/W description
Bit[7:2]: Not used
0x570A AWB CTRL10 0x00 RW
Bit[1:0]: gamma_ythre_h[9:8]

0x570B AWB CTRL11 0x10 RW Bit[7:0]: gamma_ythre_h[7:0]

Bit[7:2]: Not used

0x570C AWB CTRL12 0x00 RW
Bit[1:0]: gamma_uvthre1[9:8]

0x570D AWB CTRL13 0x40 RW Bit[7:0]: gamma_uvthre1[7:0]

Bit[7:2]: Not used

0x570E AWB CTRL14 0x00 RW
Bit[1:0]: gamma_uvthre2[9:8]
C

0x570F AWB CTRL15 0x40 RW Bit[7:0]: gamma_uvthre2[7:0]

on ac

Bit[7:2]: Not used

0x5710 AWB CTRL16 0x00 RW
Bit[1:0]: shadow_ythre1[9:8]

Bit[7:0]: shadow_ythre1[7:0]
0x5711 AWB CTRL17 0x40 RW (shadow_ythre1 + shadow_ythre2 ≤
W
fid in

0x3FF)

Bit[7:2]: Not used

0x5712 AWB CTRL18 0x00 RW
Bit[1:0]: shadow_ythre2[9:8]
en g o

Bit[7:0]: shadow_ythre2[7:0]
0x5713 AWB CTRL19 0x80 RW (shadow_ythre1 + shadow_ythre2 ≤
h

0x3FF)
tia nly

Bit[7:2]: Not used

0x5714 AWB CTRL20 0x00 RW
Bit[1:0]: shadow_uv_thre1[9:8]

Bit[7:0]: shadow_uv_thre1[7:0]
lf

0x5715 AWB CTRL21 0x10 RW (shadow_uv_thre1 + shadow_uv_thre2 ≤

0x3FF)
or

Bit[7:2]: Not used

0x5716 AWB CTRL22 0x00 RW
Bit[1:0]: shadow_uv_thre2[9:8]

Bit[7:0]: shadow_uv_thre2[7:0]
0x5717 AWB CTRL23 0x10 RW (shadow_uv_thre1 + shadow_uv_thre2 ≤
0x3FF)

Bit[7:6]: Not used

Bit[5:2]: Debug mode
0x5718 AWB CTRL24 0x3C RW Bit[1]: Debug mode 2 (EOF to VSYNC fixed
value, other than zero)
Bit[0]: Debug mode 1 (always fixed value)

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-67

table 7-10 AWB control registers (sheet 12 of 15)

default
address register name value R/W description
Bit[7:1]: Not used
Bit[0]: Color temperature based AWB
0: Disable
1: Enable
0xC4B8 CT_AWB_EN – RW
When register value is 0x00, it means function is
disabled; all other values mean function is enabled.
This register value must be initialized by user and
must not be removed from start up sequence. Default
value is random.

Bit[7:2]: Not used

C

Bit[1:0]: AWB work mode

00 Separate mode
on ac

01: Long
10: Short
0xC4B9 AWB_WORK_MODE – RW
11: Combine
W
fid in

This register value must be initialized by user and

must not be removed from start up sequence. Default
value is random.

Bit[7:1]: Not used

en g o

Bit[0]: Feedback for simple AWB

0: Disable
h

1: Enable
tia nly

0xC4BA AWB_FEEDBACK_EN – RW
When register value is 0x00, it means function is
disabled; all other values mean function is enabled.
This register value must be initialized by user and
must not be removed from start up sequence. Default
lf

value is random.

0xC4BB DEBUG MODE – – Debug Mode

or

Bit[7:0]: Min statistic num for simple AWB[15:8]

0xC4CC SIMPLE_MIN_NUM_1 – RW This register value must be initialized by user and

must not be removed from start up sequence. Default
value is random.

Bit[7:0]: Min statistic num for simple AWB[7:0]

0xC4CD SIMPLE_MIN_NUM_2 – RW This register value must be initialized by user and

must not be removed from start up sequence. Default
value is random.

Bit[7:0]: Min statistic num for CT AWB[15:8]

0xC4CE CT_MIN_NUM_1 – RW This register value must be initialized by user and

must not be removed from start up sequence. Default
value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-10 AWB control registers (sheet 13 of 15)

default
address register name value R/W description
Bit[7:0]: Min statistic num for CT AWB[7:0]

0xC4CF CT_MIN_NUM_2 – RW This register value must be initialized by user and

must not be removed from start up sequence. Default
value is random.

Relative AWB Adjustment Step

0xC4D0 AWB_STEP_1 – RW This register value must be initialized by user and

must not be removed from start up sequence. Default
value is random.
C

Absolute AWB Adjustment Step

on ac

0xC4D1 AWB_STEP_2 – RW This register value must be initialized by user and

must not be removed from start up sequence. Default
value is random.

0xC4D2~
W
fid in

DEBUG MODE – – Debug Registers

0xC4DF

0x5AB0~
AWB_R – R Debug Information for AWB Gain Control
0x5B1B
en g o

Bit[7:2]: Not used

0x5CFC WBG_R01 – R
Bit[1:0]: Long_AWB_gain_B[9:8]
h

0x5CFD WBG_R02 – R Bit[7:0]: Long_AWB_gain_B[7:0]

tia nly

Bit[7:2]: Not used

0x5CFE WBG_R03 – R
Bit[1:0]: Long_AWB_gain_Gb[9:8]
lf

0x5CFF WBG_R04 – R Bit[7:0]: Long_AWB_gain_Gb[7:0]

Bit[7:2]: Not used

0x5D00 WBG_R05 – R
Bit[1:0]: Long_AWB_gain_Gr[9:8]
or

0x5D01 WBG_R06 – R Bit[7:0]: Long_AWB_gain_Gr[7:0]

Bit[7:2]: Not used

0x5D02 WBG_R07 – R
Bit[1:0]: Long_AWB_gain_R[9:8]

0x5D03 WBG_R08 – R Bit[7:0]: Long_AWB_gain_R[7:0]

Bit[7:2]: Not used

0x5D04 WBG_R09 – R
Bit[1:0]: Short_AWB_gain_B[9:8]

0x5D05 WBG_R10 – R Bit[7:0]: Short_AWB_gain_B[7:0]

Bit[7:2]: Not used

0x5D06 WBG_R11 – R
Bit[1:0]: Short_AWB_gain_Gb[9:8]

0x5D07 WBG_R12 – R Bit[7:0]: Short_AWB_gain_Gb[7:0]

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-69

table 7-10 AWB control registers (sheet 14 of 15)

default
address register name value R/W description
Bit[7:2]: Not used
0x5D08 WBG_R13 – R
Bit[1:0]: Short_AWB_gain_Gr[9:8]

0x5D09 WBG_R14 – R Bit[7:0]: Short_AWB_gain_Gr[7:0]

Bit[7:2]: Not used

0x5D0A WBG_R15 – R
Bit[1:0]: Short_AWB_gain_R[9:8]

0x5D0B WBG_R16 – R Bit[7:0]: Short_AWB_gain_R[7:0]

Bit[7:2]: Not used

0x5D0C WBG_R17 – R Bit[1:0]: Long_AWBoffset_B[9:8]
C

Complementary code

Bit[7:0]: Long_AWBoffset_B[7:0]
0x5D0D WBG_R18 – R
on ac

Complementary code

Bit[7:2]: Not used

0x5D0E WBG_R19 – R Bit[1:0]: Long_AWBoffset_GB[9:8]
Complementary code
W
fid in

Bit[7:0]: Long_AWBoffset_GB[7:0]
0x5D0F WBG_R20 – R
Complementary code
en g o

Bit[7:2]: Not used

0x5D10 WBG_R21 – R Bit[1:0]: Long_AWBoffset_GR[9:8]
Complementary code
h

Bit[7:0]: Long_AWBoffset_GR[7:0]
tia nly

0x5D11 WBG_R22 – R
Complementary code

Bit[7:2]: Not used

0x5D12 WBG_R23 – R Bit[1:0]: Long_AWBoffset_R[9:8]
lf

Complementary code

Bit[7:0]: Long_AWBoffset_R[7:0]
0x5D13 WBG_R24 – R
or

Complementary code

Bit[7:2]: Not used

0x5D14 WBG_R25 – R Bit[1:0]: Short_AWBoffset_B[9:8]
Complementary code

Bit[7:0]: Short_AWBoffset_B[7:0]
0x5D15 WBG_R26 – R
Complementary code

Bit[7:2]: Not used

0x5D16 WBG_R27 – R Bit[1:0]: Short_AWBoffset_Gb[9:8]
Complementary code

Bit[7:0]: Short_AWBoffset_Gb[7:0]
0x5D17 WBG_R28 – R
Complementary code

Bit[7:2]: Not used

0x5D18 WBG_R29 – R Bit[1:0]: Short_AWBoffset_Gr[9:8]
Complementary code

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-10 AWB control registers (sheet 15 of 15)

default
address register name value R/W description
Bit[7:0]: Short_AWBoffset_Gr[7:0]
0x5D19 WBG_R30 – R
Complementary code

Bit[7:2]: Not used

0x5D1A WBG_R31 – R Bit[1:0]: Short_AWBoffset_R[9:8]
Complementary code

Bit[7:0]: Short_AWBoffset_R[7:0]
0x5D1B WBG_R32 – R
Complementary code

7.11 DNS control [0x5210 ~ 0x522F, 0x5238 ~ 0x5256]

C
on ac

table 7-11 DNS control registers (sheet 1 of 4)

default
W
fid in

address register name value R/W description

Bit[7:4]: Not used
0x5210 DNS CTRL10 0x04 RW
Bit[3:0]: noise_y_a for long exposure sub-pixel
en g o

Bit[7:5]: Not used

0x5211 DNS CTRL11 0x08 RW
Bit[4:0]: noise_uv_a for long exposure sub-pixel
h

Bit[7:1]: Not used

tia nly

0x5212 DNS CTRL12 0x00 RW

Bit[0]: dns_manual for long exposure sub-pixel

0x5213 DNS CTRL13 0x02 RW Bit[7:0]: noise_y for long exposure sub-pixel
lf

Bit[7:1]: Not used

0x5214 DNS CTRL14 0x00 RW
Bit[0]: noise_u[8] for long exposure sub-pixel
or

0x5215 DNS CTRL15 0x02 RW Bit[7:0]: noise_u[7:0] for long exposure sub-pixel

Bit[7:1]: Not used

0x5216 DNS CTRL16 0x00 RW
Bit[0]: noise_v[8] for long exposure sub-pixel

0x5217 DNS CTRL17 0x02 RW Bit[7:0]: noise_v[7:0] for long exposure sub-pixel

0x5218 DNS CTRL18 0x06 RW Bit[7:0]: dns_edgethre for long exposure sub-pixel

Bit[7:3]: Not used

0x5219 DNS CTRL19 0x04 RW
Bit[2:0]: dns_gbgr_extra[2:0] for long exposure sub-pixel

0x521A DNS CTRL20 0x02 RW Bit[7:0]: noise_y_list_0 for long exposure sub-pixel

0x521B DNS CTRL21 0x04 RW Bit[7:0]: noise_y_list_1 for long exposure sub-pixel

0x521C DNS CTRL22 0x08 RW Bit[7:0]: noise_y_list_2 for long exposure sub-pixel

0x521D DNS CTRL23 0x14 RW Bit[7:0]: noise_y_list_3 for long exposure sub-pixel

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-71

table 7-11 DNS control registers (sheet 2 of 4)

default
address register name value R/W description
0x521E DNS CTRL24 0x1E RW Bit[7:0]: noise_y_list_4 for long exposure sub-pixel

0x521F DNS CTRL25 0x28 RW Bit[7:0]: noise_y_list_5 for long exposure sub-pixel

0x5220 DNS CTRL26 0x32 RW Bit[7:0]: noise_y_list_6_l for long exposure sub-pixel

Bit[7:1]: Not used

0x5221 DNS CTRL27 0x00 RW
Bit[0]: dns_dummy[0] for long exposure sub-pixel

Bit[7:1]: Not used

0x5222 DNS CTRL28 0x00 RW
Bit[0]: noise_uv_list_0[8] for long exposure sub-pixel

0x5223 DNS CTRL29 0x02 RW Bit[7:0]: noise_uv_list_0[7:0] for long exposure sub-pixel
C

0x5224 DEBUG MODE – – Debug Mode

on ac

0x5225 DNS CTRL31 0x04 RW Bit[7:0]: noise_uv_list_1[7:0] for long exposure sub-pixel

Bit[7:1]: Not used

0x5226 DNS CTRL32 0x00 RW
Bit[0]: noise_uv_list_2[8] for long exposure sub-pixel
W
fid in

0x5227 DNS CTRL33 0x0C RW Bit[7:0]: noise_uv_list_2[7:0] for long exposure sub-pixel

Bit[7:1]: Not used

0x5228 DNS CTRL34 0x00 RW
en g o

Bit[0]: noise_uv_list_3[8] for long exposure sub-pixel

0x5229 DNS CTRL35 0x28 RW Bit[7:0]: noise_uv_list_3[7:0] for long exposure sub-pixel
h

Bit[7:1]: Not used

tia nly

0x522A DNS CTRL36 0x00 RW

Bit[0]: noise_uv_list_4[8] for long exposure sub-pixel

0x522B DNS CTRL37 0x32 RW Bit[7:0]: noise_uv_list_4[7:0] for long exposure sub-pixel
lf

Bit[7:1]: Not used

0x522C DNS CTRL38 0x00 RW
Bit[0]: noise_uv_list_5[8] for long exposure sub-pixel

0x522D DNS CTRL39 0x3C RW Bit[7:0]: noise_uv_list_5[7:0] for long exposure sub-pixel
or

Bit[7:1]: Not used

0x522E DNS CTRL40 0x00 RW
Bit[0]: noise_uv_list_6[8] for long exposure sub-pixel

0x522F DNS CTRL41 0x4C RW Bit[7:0]: noise_uv_list_6[7:0] for long exposure sub-pixel

Bit[7:4]: Not used

0x5238 DNS CTRL50 0x04 RW
Bit[3:0]: noise_y_a for short exposure sub-pixel

Bit[7:5]: Not used

0x5239 DNS CTRL51 0x08 RW
Bit[4:0]: noise_uv_a for short exposure sub-pixel

Bit[7:1]: Not used

0x523A DNS CTRL52 0x00 RW
Bit[0]: dns_manual for short exposure sub-pixel

0x523B DNS CTRL53 0x02 RW Bit[7:0]: noise_y for short exposure sub-pixel

Bit[7:1]: Not used

0x523C DNS CTRL54 0x00 RW
Bit[0]: noise_u[8] for short exposure sub-pixel

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-11 DNS control registers (sheet 3 of 4)

default
address register name value R/W description
0x523D DNS CTRL55 0x02 RW Bit[7:0]: noise_u[7:0] for short exposure sub-pixel

Bit[7:1]: Not used

0x523E DNS CTRL56 0x00 RW
Bit[0]: noise_v[8] for short exposure sub-pixel

0x523F DNS CTRL57 0x02 RW Bit[7:0]: noise_v[7:0] for short exposure sub-pixel

0x5240 DNS CTRL58 0x06 RW Bit[7:0]: dns_edgethre for short exposure sub-pixel

Bit[7:3]: Not used

0x5241 DNS CTRL59 0x04 RW Bit[2:0]: dns_gbgr_extra[2:0] for short exposure
sub-pixel
C

0x5242 DNS CTRL60 0x02 RW Bit[7:0]: noise_y_list_0 for short exposure sub-pixel
on ac

0x5243 DNS CTRL61 0x04 RW Bit[7:0]: noise_y_list_1 for short exposure sub-pixel

0x5244 DNS CTRL62 0x08 RW Bit[7:0]: noise_y_list_2 for short exposure sub-pixel

0x5245 DNS CTRL63 0x14 RW Bit[7:0]: noise_y_list_3 for short exposure sub-pixel
W
fid in

0x5246 DNS CTRL64 0x1E RW Bit[7:0]: noise_y_list_4 for short exposure sub-pixel

0x5247 DNS CTRL65 0x28 RW Bit[7:0]: noise_y_list_5 for short exposure sub-pixel
en g o

0x5248 DNS CTRL66 0x32 RW Bit[7:0]: noise_y_list_6 for short exposure sub-pixel
h

Bit[7:1]: Not used

0x5249 DNS CTRL67 0x00 RW
Bit[0]: noise_uv_list_0[8] for short exposure sub-pixel
tia nly

Bit[7:0]: noise_uv_list_0[7:0] for short exposure

0x524A DNS CTRL68 0x02 RW
sub-pixel
lf

Bit[7:1]: Not used

0x524B DNS CTRL69 0x00 RW
Bit[0]: noise_uv_list_1[8] for short exposure sub-pixel

Bit[7:0]: noise_uv_list_1[7:0] for short exposure

or

0x524C DNS CTRL70 0x04 RW

sub-pixel

Bit[7:1]: Not used

0x524D DNS CTRL71 0x00 RW
Bit[0]: noise_uv_list_2[8] for short exposure sub-pixel

Bit[7:0]: noise_uv_list_2[7:0] for short exposure

0x524E DNS CTRL72 0x0C RW
sub-pixel

Bit[7:1]: Not used

0x524F DNS CTRL73 0x00 RW
Bit[0]: noise_uv_list_3[8] for short exposure sub-pixel

Bit[7:0]: noise_uv_list_3[7:0] for short exposure

0x5250 DNS CTRL74 0x28 RW
sub-pixel

Bit[7:1]: Not used

0x5251 DNS CTRL75 0x00 RW
Bit[0]: noise_uv_list_4[8] for short exposure sub-pixel

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-73

table 7-11 DNS control registers (sheet 4 of 4)

default
address register name value R/W description
Bit[7:0]: noise_uv_list_4[7:0] for short exposure
0x5252 DNS CTRL76 0x32 RW
sub-pixel

Bit[7:1]: Not used

0x5253 DNS CTRL77 0x00 RW
Bit[0]: noise_uv_list_5[8] for short exposure sub-pixel

Bit[7:0]: noise_uv_list_5[7:0] for short exposure

0x5254 DNS CTRL78 0x3C RW
sub-pixel

Bit[7:1]: Not used

0x5255 DNS CTRLL79 0x00 RW
Bit[0]: noise_uv_list_6[8] for short exposure sub-pixel

Bit[7:0]: noise_uv_list_6[7:0] for short exposure

C

0x5256 DNS CTRLL80 0x4C RW

sub-pixel
on ac

7.12 CIP control [0x5280 ~ 0x52A1, 0x52C0 ~ 0x52E1]

W
fid in

table 7-12 CIP control registers (sheet 1 of 7)

en g o

default
address register name value R/W description
h

Bit[7:2]: Not used

Bit[1:0]: min_gain[9:8] for long exposure sub-pixel
tia nly

0x5280 CIP CTRL00 0x00 RW

Min_gain is used in CIP_start module to judge
in which range current sensor is in

Bit[7:0]: min_gain[7:0] for long exposure sub-pixel

lf

0x5281 CIP CTRL01 0x10 RW Min_gain is used in CIP_start module to judge

in which range current sensor is in
or

Bit[7:2]: Not used

Bit[1:0]: max_gain[9:8] for long exposure sub-pixel
0x5282 CIP CTRL02 0x00 RW
Max_gain is used in CIP_start module to judge
in which range current sensor is in

Bit[7:0]: max_gain[7:0] for long exposure sub-pixel

0x5283 CIP CTRL03 0x80 RW Max_gain is used in CIP_start module to judge
in which range current sensor is in

Bit[7:1]: Not used

Bit[0]: min_noise[8] for long exposure sub-pixel
0x5284 CIP CTRL04 0x00 RW
Min_noise is used for calculating int_noise in
auto mode

Bit[7:0]: min_noise[7:0] for long exposure sub-pixel

0x5285 CIP CTRL05 0x10 RW Min_noise is used for calculating int_noise in
auto mode

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-12 CIP control registers (sheet 2 of 7)

default
address register name value R/W description
Bit[7:2]: Not used
Bit[1:0]: noise_slope[9:8] for long exposure sub-pixel
0x5286 CIP CTRL06 0x01 RW
Slope value used for calculating int_noise in
auto mode

Bit[7:0]: noise_slope[7:0] for long exposure sub-pixel

0x5287 CIP CTRL07 0x00 RW Slope value used for calculating int_noise in
auto mode

Bit[7:0]: unsharpen_mask0 for long exposure sub-pixel

0x5288 CIP CTRL08 0x10 RW UnSharpenMask0 used in some filters as
multipliers
C

Bit[7:0]: unsharpen_mask1 for long exposure sub-pixel

0x5289 CIP CTRL09 0x30 RW UnSharpenMask0 used in some filters as
on ac

multipliers

Bit[7:2]: Not used

Bit[1]: man_en
W
fid in

Enable manual mode for long exposure

0x528A CIP CTRL0A 0x01 RW
sub-pixel
Bit[0]: anti_aliasing
Enable anti-aliasing for long exposure sub-pixel
en g o

Bit[7:4]: Not used

Bit[3:0]: combine_alpha[3:0] for long exposure sub-pixel
0x528B CIP CTRL0B 0x02 RW
h

Combine coefficients for U, V and H

components
tia nly

Bit[7:5]: Not used

Bit[4:0]: min_sharpen[4:0] for long exposure sub-pixel
0x528C CIP CTRL0C 0x00 RW
Min_sharpen is used for sharpen_p calculation
lf

in auto mode

Bit[7:6]: Not used

or

Bit[5:0]: max_sharpen[5:0] for long exposure sub-pixel

0x528D CIP CTRL0D 0x10 RW
Max_sharpen is used for sharpen_p calculation
in auto mode

Bit[7:6]: Not used

Bit[5:0]: min_sharpen_tp[5:0] for long exposure
0x528E CIP CTRL0E 0x10 RW sub-pixel
Min_sharpen_tp is used for sharpen_tp
computation in auto mode

Bit[7:0]: max_sharpen_tp[7:0] for long exposure

sub-pixel
0x528F CIP CTRL0F 0x60 RW
Max_sharpen_tp is used for sharpen_tp
computation in auto mode

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-75

table 7-12 CIP control registers (sheet 3 of 7)

default
address register name value R/W description
Bit[7:6]: Not used
Bit[5:0]: min_sharpen_tm[5:0] for long exposure
0x5290 CIP CTRL10 0x20 RW sub-pixel
Min_sharpen_tm is used for sharpen_tm
computation in auto mode

Bit[7:0]: max_sharpen_tm[7:0] for long exposure

sub-pixel
0x5291 CIP CTRL11 0x60 RW
Max_sharpen_tm is used for sharpen_tm
computation in auto mode

Bit[7:0]: sharpen_tya[7:0] for long exposure sub-pixel

0x5292 CIP CTRL12 0x40
C

RW
Threshold used for function of adaptive sharpen

Bit[7:5]: Not used

on ac

Bit[4:0]: sharpen_alpha[4:0] for long exposure sub-pixel

0x5293 CIP CTRL13 0x10 RW
Sharpen_alpha is used for calculating
sharpen_m after sharpen_p is obtained
W
fid in

Bit[7:6]: Not used

0x5294 CIP CTRL14 0x06 RW Bit[5:0]: mthre[5:0] for long exposure sub-pixel
Threshold for medium frequency signals

Bit[7:6]: Not used

en g o

0x5295 CIP CTRL15 0x08 RW Bit[5:0]: hthre[5:0] for long exposure sub-pixel
Threshold for high frequency signals
h

Bit[7:4]: Not used

tia nly

0x5297 CIP CTRL17 0x06 RW Bit[3:0]: hfreq_coef[3:0] for long exposure sub-pixel
Coefficients for high frequency signals

Bit[7:2]: Not used

lf

0x5298 CIP CTRL18 0x00 RW Bit[1:0]: efreq_coef[1:0] for long exposure sub-pixel
Coefficients for E frequency signals

Bit[7:6]: Not used

or

0x5299 CIP CTRL19 0x08 RW Bit[5:0]: lthre[5:0] for long exposure sub-pixel
Threshold for low frequency signals

Bit[7:2]: Not used

Bit[1:0]: man_int_noise[9:8] for long exposure sub-pixel
0x529A CIP CTRL1A 0x00 RW
Int_noise is input only in manual mode and is
used as threshold in some filters

Bit[7:0]: man_int_noise[7:0] for long exposure sub-pixel

0x529B CIP CTRL1B 0x30 RW Int_noise is input only in manual mode and is
used as threshold in some filters

Bit[7:1]: Not used

Bit[0]: man_inv_noise[8] for long exposure sub-pixel
0x529C CIP CTRL1C 0x00 RW
Inv_noise is input only in manual mode and is
used as threshold in some filters

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-12 CIP control registers (sheet 4 of 7)

default
address register name value R/W description
Bit[7:0]: man_inv_noise[7:0] for long exposure sub-pixel
0x529D CIP CTRL1D 0x55 RW Inv_noise is input only in manual mode and is
used as threshold in some filters

Bit[7:6]: Not used

Bit[5:0]: man_sharpen_p[5:0] for long exposure
0x529E CIP CTRL1E 0x08 RW sub-pixel
Sharpen_p is input only in manual mode and is
used for function of adaptive sharpen

Bit[7]: Not used

Bit[6:0]: man_sharpen_m[6:0] for long exposure
C

0x529F CIP CTRL1F 0x08 RW sub-pixel

Sharpen_m is input only in manual mode and is
on ac

used for function of adaptive sharpen

Bit[7:0]: man_sharpen_tp[7:0] for long exposure

sub-pixel
0x52A0 CIP CTRL20 0x06 RW
Sharpen_tp is input only in manual mode and is
W
fid in

used for function of adaptive sharpen

Bit[7:0]: man_sharpen_tm[7:0] for long exposure

sub-pixel
0x52A1 CIP CTRL21 0x08 RW
en g o

Sharpen_tm is input only in manual mode and

is used for function of adaptive sharpen
h

Bit[7:2]: Not used

Bit[1:0]: min_gain[9:8] for short exposure sub-pixel
tia nly

0x52C0 CIP CTRL40 0x00 RW

Min_gain is used in CIP_start module to judge
in which range current sensor is in

Bit[7:0]: min_gain[7:0] for short exposure sub-pixel

lf

0x52C1 CIP CTRL41 0x10 RW Min_gain is used in CIP_start module to judge

in which range current sensor is in
or

Bit[7:2]: Not used

Bit[1:0]: max_gain[9:8] for short exposure sub-pixel
0x52C2 CIP CTRL42 0x00 RW
Max_gain is used in CIP_start module to judge
in which range current sensor is in

Bit[7:0]: max_gain[7:0] for short exposure sub-pixel

0x52C3 CIP CTRL43 0x80 RW Max_gain is used in CIP_start module to judge
in which range current sensor is in

Bit[7:1]: Not used

Bit[0]: min_noise[8] for short exposure sub-pixel
0x52C4 CIP CTRL44 0x00 RW
Min_noise is used for calculating int_noise in
auto mode

Bit[7:0]: min_noise[7:0] for short exposure sub-pixel

0x52C5 CIP CTRL45 0x10 RW Min_noise is used for calculating int_noise in
auto mode

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-77

table 7-12 CIP control registers (sheet 5 of 7)

default
address register name value R/W description
Bit[7:2]: Not used
Bit[1:0]: noise_slope[9:8] for short exposure sub-pixel
0x52C6 CIP CTRL46 0x01 RW
Slope value used for calculating int_noise in
auto mode

Bit[7:0]: noise_slope[7:0] for short exposure sub-pixel

0x52C7 CIP CTRL47 0x00 RW Slope value used for calculating int_noise in
auto mode

Bit[7:0]: unsharpen_mask0 for short exposure sub-pixel

0x52C8 CIP CTRL48 0x10 RW UnSharpenMask0 used in some filters as
multipliers
C

Bit[7:0]: unsharpen_mask1 for short exposure sub-pixel

0x52C9 CIP CTRL49 0x30 RW UnSharpenMask0 used in some filters as
on ac

multipliers

Bit[7:2]: Not used

Bit[1]: man_en
W
fid in

Enable manual mode for short exposure

0x52CA CIP CTRL4A 0x01 RW
sub-pixel
Bit[0]: anti_aliasing for short exposure sub-pixel
Enable anti-aliasing
en g o

Bit[7:4]: Not used

Bit[3:0]: combine_alpha[3:0] for short exposure
h

0x52CB CIP CTRL4B 0x02 RW sub-pixel

Combine coefficients for U, V and H
tia nly

components

Bit[7:5]: Not used

Bit[4:0]: min_sharpen[4:0] for short exposure sub-pixel
lf

0x52CC CIP CTRL4C 0x00 RW

Min_sharpen is used for sharpen_p calculation
in auto mode
or

Bit[7:6]: Not used

Bit[5:0]: max_sharpen[5:0] for short exposure sub-pixel
0x52CD CIP CTRL4D 0x00 RW
Max_sharpen is used for sharpen_p calculation
in auto mode

Bit[7:6]: Not used

Bit[5:0]: min_sharpen_tp[5:0] for short exposure
0x52CE CIP CTRL4E 0x10 RW sub-pixel
Min_sharpen_tp is used for sharpen_tp
computation in auto mode

Bit[7:0]: max_sharpen_tp[7:0] for short exposure

sub-pixel
0x52CF CIP CTRL4F 0x60 RW
Max_sharpen_tp is used for sharpen_tp
computation in auto mode

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-12 CIP control registers (sheet 6 of 7)

default
address register name value R/W description
Bit[7:6]: Not used
Bit[5:0]: min_sharpen_tm[5:0] for short exposure
0x52D0 CIP CTRL50 0x20 RW sub-pixel
Min_sharpen_tm is used for sharpen_tm
computation in auto mode

Bit[7:0]: max_sharpen_tm[7:0] for short exposure

sub-pixel
0x52D1 CIP CTRL51 0x60 RW
Max_sharpen_tm is used for sharpen_tm
computation in auto mode

Bit[7:0]: sharpen_tya[7:0] for short exposure sub-pixel

0x52D2
C

CIP CTRL52 0x40 RW

Threshold used for function of adaptive sharpen

Bit[7:5]: Not used

on ac

Bit[4:0]: sharpen_alpha[4:0] for short exposure

0x52D3 CIP CTRL53 0x10 RW sub-pixel
Sharpen_alpha is used for calculating
sharpen_m after sharpen_p is obtained
W
fid in

Bit[7:6]: Not used

0x52D4 CIP CTRL54 0x06 RW Bit[5:0]: mthre[5:0] for short exposure sub-pixel
Threshold for medium frequency signals
en g o

Bit[7:6]: Not used

0x52D5 CIP CTRL55 0x08 RW Bit[5:0]: hthre[5:0] for short exposure sub-pixel
h

Threshold for high frequency signals

tia nly

Bit[7:4]: Not used

0x52D7 CIP CTRL57 0x06 RW Bit[3:0]: hfreq_coef[3:0] for short exposure sub-pixel
Coefficients for high frequency signals
lf

Bit[7:2]: Not used

0x52D8 CIP CTRL58 0x00 RW Bit[1:0]: efreq_coef[1:0] for short exposure sub-pixel
Coefficients for E frequency signals
or

Bit[7:6]: Not used

0x52D9 CIP CTRL59 0x08 RW Bit[5:0]: lthre[5:0] for short exposure sub-pixel:
Threshold for low frequency signals

Bit[7:2]: Not used

Bit[1:0]: man_int_noise[9:8] for short exposure sub-pixel
0x52DA CIP CTRL5A 0x00 RW
Int_noise is input only in manual mode and is
used as threshold in some filters

Bit[7:0]: man_int_noise[7:0] for short exposure sub-pixel

0x52DB CIP CTRL5B 0x30 RW Int_noise is input only in manual mode and is
used as threshold in some filters

Bit[7:1]: Not used

Bit[0]: man_inv_noise[8] for short exposure sub-pixel
0x52DC CIP CTRL5C 0x00 RW
In_noise is input only in manual mode and is
used as threshold in some filters

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-79

table 7-12 CIP control registers (sheet 7 of 7)

default
address register name value R/W description
Bit[7:0]: man_inv_noise[7:0] for short exposure
sub-pixel
0x52DD CIP CTRL5D 0x55 RW
In_noise is input only in manual mode and is
used as threshold in some filters

Bit[7:6]: Not used

Bit[5:0]: man_sharpen_p[5:0] for short exposure
0x52DE CIP CTRL5E 0x08 RW sub-pixel
Sharpen_p is input only in manual mode and is
used for function of adaptive sharpen

Bit[7]: Not used

C

Bit[6:0]: man_sharpen_m[6:0] for short exposure

0x52DF CIP CTRL5F 0x08 RW sub-pixel
on ac

Sharpen_m is input only in manual mode and is

used for function of adaptive sharpen

Bit[7:0]: man_sharpen_tp[7:0] for short exposure

sub-pixel
W
fid in

0x52E0 CIP CTRL60 0x06 RW

Sharpen_tp is input only in manual mode and is
used for function of adaptive sharpen

Bit[7:0]: man_sharpen_tm[7:0] for short exposure

en g o

sub-pixel:
0x52E1 CIP CTRL61 0x08 RW
Sharpen_tm is input only in manual mode and
is used for function of adaptive sharpen
h

tia nly

7.13 CMX control [0xC318 ~ 0xC347]

lf

table 7-13 CMX control registers (sheet 1 of 7)

or

default
address register name value R/W description
Bit[7:0]: Long color matrix 1[15:8]

0xC318 COLOR_MATRIX_L_1_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Long color matrix 1[7:0]

0xC319 COLOR_MATRIX_L_1_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-13 CMX control registers (sheet 2 of 7)

default
address register name value R/W description
Bit[7:0]: Long color matrix 2[15:8]

0xC31A COLOR_MATRIX_L_2_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Long color matrix 2[7:0]

0xC31B COLOR_MATRIX_L_2_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.
C

Bit[7:0]: Long color matrix 3[15:8]

on ac

0xC31C COLOR_MATRIX_L_3_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Long color matrix 3[7:0]

W
fid in

0xC31D COLOR_MATRIX_L_3_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.
en g o

Bit[7:0]: Long color matrix 4[15:8]

h

0xC31E COLOR_MATRIX_L_4_1 – RW This register value must be initialized by

tia nly

user and must not be removed from start up

sequence. Default value is random.

Bit[7:0]: Long color matrix 4[7:0]

lf

0xC31F COLOR_MATRIX_L_4_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.
or

Bit[7:0]: Long color matrix 5[15:8]

0xC320 COLOR_MATRIX_L_5_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Long color matrix 5[7:0]

0xC321 COLOR_MATRIX_L_5_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Long color matrix 6[15:8]

0xC322 COLOR_MATRIX_L_6_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-81

table 7-13 CMX control registers (sheet 3 of 7)

default
address register name value R/W description
Bit[7:0]: Long color matrix 6[7:0]

0xC323 COLOR_MATRIX_L_6_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Long color matrix 7[15:8]

0xC324 COLOR_MATRIX_L_7_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.
C

Bit[7:0]: Long color matrix 7[7:0]

on ac

0xC325 COLOR_MATRIX_L_7_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Long color matrix 8[15:8]

W
fid in

0xC326 COLOR_MATRIX_L_8_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.
en g o

Bit[7:0]: Long color matrix 8[7:0]

h

0xC327 COLOR_MATRIX_L_8_2 – RW This register value must be initialized by

tia nly

user and must not be removed from start up

sequence. Default value is random.

Bit[7:0]: Long color matrix 9[15:8]

lf

0xC328 COLOR_MATRIX_L_9_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.
or

Bit[7:0]: Long color matrix 9[7:0]

0xC329 COLOR_MATRIX_L_9_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Long color matrix 10[15:8]

0xC32A COLOR_MATRIX_L_10_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Long color matrix 10[7:0]

0xC32B COLOR_MATRIX_L_10_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-13 CMX control registers (sheet 4 of 7)

default
address register name value R/W description
Bit[7:0]: Long color matrix 11[15:8]

0xC32C COLOR_MATRIX_L_11_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Long color matrix 11[7:0]

0xC32D COLOR_MATRIX_L_11_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.
C

Bit[7:0]: Long color matrix 12[15:8]

on ac

0xC32E COLOR_MATRIX_L_12_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Long color matrix 12[7:0]

W
fid in

0xC32F COLOR_MATRIX_L_12_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.
en g o

Bit[7:0]: Short color matrix 1[15:8]

h

0xC330 COLOR_MATRIX_S_1_1 – RW This register value must be initialized by

tia nly

user and must not be removed from start up

sequence. Default value is random.

Bit[7:0]: Short color matrix 1[7:0]

lf

0xC331 COLOR_MATRIX_S_1_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.
or

Bit[7:0]: Short color matrix 2[15:8]

0xC332 COLOR_MATRIX_S_2_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Short color matrix 2[7:0]

0xC333 COLOR_MATRIX_S_2_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Short color matrix 3[15:8]

0xC334 COLOR_MATRIX_S_3_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-83

table 7-13 CMX control registers (sheet 5 of 7)

default
address register name value R/W description
Bit[7:0]: Short color matrix 3[7:0]

0xC335 COLOR_MATRIX_S_3_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Short color matrix 4[15:8]

0xC336 COLOR_MATRIX_S_4_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.
C

Bit[7:0]: Short color matrix 4[7:0]

on ac

0xC337 COLOR_MATRIX_S_4_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Short color matrix 5[15:8]

W
fid in

0xC338 COLOR_MATRIX_S_5_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.
en g o

Bit[7:0]: Short color matrix 5[7:0]

h

0xC339 COLOR_MATRIX_S_5_2 – RW This register value must be initialized by

tia nly

user and must not be removed from start up

sequence. Default value is random.

Bit[7:0]: Short color matrix 6[15:8]

lf

0xC33A COLOR_MATRIX_S_6_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.
or

Bit[7:0]: Short color matrix 6[7:0]

0xC33B COLOR_MATRIX_S_6_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Short color matrix 7[15:8]

0xC33C COLOR_MATRIX_S_7_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Short color matrix 7[7:0]

0xC33D COLOR_MATRIX_S_7_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-13 CMX control registers (sheet 6 of 7)

default
address register name value R/W description
Bit[7:0]: Short color matrix 8[15:8]

0xC33E COLOR_MATRIX_S_8_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Short color matrix 8[7:0]

0xC33F COLOR_MATRIX_S_8_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.
C

Bit[7:0]: Short color matrix 9[15:8]

on ac

0xC340 COLOR_MATRIX_S_9_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Short color matrix 9[7:0]

W
fid in

0xC341 COLOR_MATRIX_S_9_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.
en g o

Bit[7:0]: Short color matrix 10[15:8]

h

0xC342 COLOR_MATRIX_S_10_1 – RW This register value must be initialized by

tia nly

user and must not be removed from start up

sequence. Default value is random.

Bit[7:0]: Short color matrix 10[7:0]

lf

0xC343 COLOR_MATRIX_S_10_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.
or

Bit[7:0]: Short color matrix 11[15:8]

0xC344 COLOR_MATRIX_S_11_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Short color matrix 11[7:0]

0xC345 COLOR_MATRIX_S_11_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Short color matrix 12[15:8]

0xC346 COLOR_MATRIX_S_12_1 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-85

table 7-13 CMX control registers (sheet 7 of 7)

default
address register name value R/W description
Bit[7:0]: Short color matrix 12[7:0]

0xC347 COLOR_MATRIX_S_12_2 – RW This register value must be initialized by

user and must not be removed from start up
sequence. Default value is random.

7.14 low level filter (LLF) control [0x5380 ~ 0x538A]

Changing these register values is not recommended.

C
on ac

table 7-14 LLF control registers

default
address register name value R/W description
W
fid in

Bit[7:5]: Not used

0x5380 LLF RW00 0x10 RW
Bit[4:0]: Step

Bit[7:2]: Not used

en g o

0x5381 LLF RW01 0x02 RW

Bit[1:0]: max_low_level[9:8]

0x5382 LLF RW02 0x00 RW Bit[7:0]: max_low_level[7:0]

h

tia nly

Bit[7:6]: Not used

0x5383 LLF RW03 0x04 RW
Bit[5:0]: ps_thres[13:8]

0x5384 LLF RO04 0x00 RW Bit[7:0]: ps_thres[7:0]

lf

Bit[7:5]: Not used

0x5385 LLF RO05 – R
Bit[4:0]: low_pre_sum[20:16]
or

0x5386 LLF RO06 – R Bit[7:0]: low_pre_sum[15:8]

0x5387 LLF RO07 – R Bit[7:0]: low_pre_sum[7:0]

Bit[7:5]: Not used

0x5388 LLF RO08 – R
Bit[4:0]: low_next_sum[20:16]

0x5389 LLF RO09 – R Bit[7:0]: low_next_sum[15:8]

0x538A LLF RO10 – R Bit[7:0]: low_next_sum[7:0]

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

7.15 combine [0x5400 ~ 0x542D, 0xC30C ~ 0xC4CB, 0x5A08 ~ 0x5A97,

0x5C18 ~ 0x5C6F]

table 7-15 combine control registers (sheet 1 of 10)

default
address register name value R/W description
Bit[7:4]: Not used
Bit[3]: Dark boost enable
0: Dark boost disable
1: Dark boost enable
Bit[2]: combine_uv_weight enable
C

0: Combine without UV weight

0x5400 COMB CTRL0 0x0F RW 1: Combine with UV weight
Bit[1]: color_diff_compensate enable
on ac

0: Compensate disable
1: Compensate enable
Bit[0]: Compensate error enable
0: Compensate error disable
W
fid in

1: Compensate error enable

Bit[7:4]: Not used

0x5401 COMB CTRL1 0x05 RW Bit[3:0]: comb_thre_s0
en g o

Threshold1 of short channel

Bit[7:4]: Not used

h

0x5402 COMB CTRL2 0x08 RW Bit[3:0]: comb_thre_s1

Threshold2 of short channel
tia nly

Bit[7:4]: Not used

0x5403 COMB CTRL3 0x0A RW Bit[3:0]: comb_thre_s2
Threshold3 of short channel
lf

Bit[7:4]: Not used

0x5404 COMB CTRL4 0x09 RW Bit[3:0]: comb_thre_l0
or

Threshold1 of long channel

Bit[7:4]: Not used

0x5405 COMB CTRL5 0x0A RW Bit[3:0]: comb_thre_l1
Threshold2 of long channel

Bit[7:4]: Not used

0x5406 COMB CTRL6 0x0A RW Bit[3:0]: comb_thre_l2
Threshold3 of long channel

Bit[7:4]: Not used

0x5407 COMB CTRL7 0x05 RW Bit[3:0]: comb_uv_thre_s0
UV threshold1 of short channel

Bit[7:4]: Not used

0x5408 COMB CTRL8 0x08 RW Bit[3:0]: comb_uv_thre_s1
UV threshold2 of short channel

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-87

table 7-15 combine control registers (sheet 2 of 10)

default
address register name value R/W description
Bit[7:4]: Not used
0x5409 COMB CTRL9 0x0A RW Bit[3:0]: comb_uv_thre_s2
UV threshold3 of short channel

Bit[7:4]: Not used

0x540A COMB CTRL10 0x09 RW Bit[3:0]: comb_uv_thre_l0
UV threshold1 of long channel

Bit[7:4]: Not used

0x540B COMB CTRL11 0x0A RW Bit[3:0]: comb_uv_thre_l1
UV threshold2 of long channel
C

Bit[7:4]: Not used

0x540C COMB CTRL12 0x0A RW Bit[3:0]: comb_uv_thre_l2
UV threshold3 of long channel
on ac

0x540D COMB CTRL13 0x80 RW Bit[7:0]: comb_weight00

0x540E COMB CTRL14 0x80 RW Bit[7:0]: comb_weight01

W
fid in

0x540F COMB CTRL15 0x60 RW Bit[7:0]: comb_weight02

0x5410 COMB CTRL16 0x40 RW Bit[7:0]: comb_weight03

en g o

0x5411 COMB CTRL17 0x80 RW Bit[7:0]: comb_weight10

0x5412 COMB CTRL18 0x80 RW Bit[7:0]: comb_weight11

h

tia nly

0x5413 COMB CTRL19 0x20 RW Bit[7:0]: comb_weight12

0x5414 COMB CTRL20 0x10 RW Bit[7:0]: comb_weight13

0x5415 COMB CTRL21 0x80 RW Bit[7:0]: comb_weight20

lf

0x5416 COMB CTRL22 0x80 RW Bit[7:0]: comb_weight21

or

0x5417 COMB CTRL23 0x00 RW Bit[7:0]: comb_weight22

0x5418 COMB CTRL24 0x00 RW Bit[7:0]: comb_weight23

0x5419 COMB CTRL25 0x80 RW Bit[7:0]: comb_weight30

0x541A COMB CTRL26 0x80 RW Bit[7:0]: comb_weight31

0x541B COMB CTRL27 0x00 RW Bit[7:0]: comb_weight32

0x541C COMB CTRL28 0x00 RW Bit[7:0]: comb_weight33

0x541D COMB CTRL29 0x80 RW Bit[7:0]: comb_uv_weight00

0x541E COMB CTRL30 0x80 RW Bit[7:0]: comb_uv_weight01

0x541F COMB CTRL31 0x80 RW Bit[7:0]: comb_uv_weight02

0x5420 COMB CTRL32 0x80 RW Bit[7:0]: comb_uv_weight03

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-15 combine control registers (sheet 3 of 10)

default
address register name value R/W description
0x5421 COMB CTRL33 0x80 RW Bit[7:0]: comb_uv_weight10

0x5422 COMB CTRL34 0x80 RW Bit[7:0]: comb_uv_weight11

0x5423 COMB CTRL35 0x60 RW Bit[7:0]: comb_uv_weight12

0x5424 COMB CTRL36 0x40 RW Bit[7:0]: comb_uv_weight13

0x5425 COMB CTRL37 0x80 RW Bit[7:0]: comb_uv_weight20

0x5426 COMB CTRL38 0x80 RW Bit[7:0]: comb_uv_weight21

0x5427 COMB CTRL39 0x00 RW Bit[7:0]: comb_uv_weight22

C

0x5428 COMB CTRL40 0x00 RW Bit[7:0]: comb_uv_weight23

on ac

0x5429 COMB CTRL41 0x80 RW Bit[7:0]: comb_uv_weight30

0x542A COMB CTRL42 0x80 RW Bit[7:0]: comb_uv_weight31

W
fid in

0x542B COMB CTRL43 0x00 RW Bit[7:0]: comb_uv_weight32

0x542C COMB CTRL44 0x00 RW Bit[7:0]: comb_uv_weight33

Debug Mode for Combine

en g o

Bit[7:6]: Not used

Bit[5:2]: Fixed value for read only register
0x542D COMB CTRL45 0x3C RW
h

Bit[1]: Debug mode 2 (EOF to VSYNC fixed

value, other than zero)
tia nly

Bit[0]: Debug mode 1 (always fixed value)

Bit[7:0]: Combine control point number 1

lf

0xC30C COMB_CTRL_PT1 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
or

Bit[7:0]: Combine control point number 2

0xC30D COMB_CTRL_PT2 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Combine control point number 3

0xC30E COMB_CTRL_PT3 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Combine control point number 4

0xC30F COMB_CTRL_PT4 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-89

table 7-15 combine control registers (sheet 4 of 10)

default
address register name value R/W description
Bit[7:1]: Not used
Bit[0]: Cut black level
0: Disable
1: Enable
0xC4B4 CUT_BL_EN – RW
When register value is 0x00, it means function is
disabled; all other values mean function is enabled.
This register value must be initialized by user and
must not be removed from start up sequence.
Default value is random.

Bit[7:1]: Not used

C

Bit[0]: Dark boost auto switch

0: Disable
on ac

1: Enable
DARKBOOST_AUTO_
0xC4B5 – RW
EN When register value is 0x00, it means function is
disabled; all other values mean function is enabled.
W
fid in

This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:1]: Not used

en g o

Bit[0]: Auto low level

0: Disable
h

1: Enable
AUTO_LOW_LEVEL_
tia nly

0xC4B6 – RW
EN When register value is 0x00, it means function is
disabled; all other values mean function is enabled.
This register value must be initialized by user and
must not be removed from start up sequence.
lf

Default value is random.

Bit[7:0]: Max curve gain[15:8]

or

When register value is 0x00, it means function is

0xC4BC MAX_CURVE_GAIN_1 – RW disabled; all other values mean function is enabled.
This register value must be initialized by user and
must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Max curve gain[7:0]

0xC4BD MAX_CURVE_GAIN_2 – RW
This register value will be automatically initialized by
sensor after powering up. Default value is random.

Bit[7:0]: Manual gamma[15:8]

0xC4BE MANUAL_GAMMA_1 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-15 combine control registers (sheet 5 of 10)

default
address register name value R/W description
Bit[7:0]: Manual gamma[7:0]

0xC4BF MANUAL_GAMMA_2 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Dark boost gain threshold 1[15:8]

0xC4C0 DB_GAIN_THRE_11 – RW
This register value will be automatically initialized by
sensor after powering up. Default value is random.

Bit[7:0]: Dark boost gain threshold 1[7:0]

C

0xC4C1 DB_GAIN_THRE_12 – RW
This register value will be automatically initialized by
on ac

sensor after powering up. Default value is random.

Bit[7:0]: Dark boost gain threshold 2[15:8]

0xC4C2 DB_GAIN_THRE_21 – RW
This register value will be automatically initialized by
W
fid in

sensor after powering up. Default value is random.

Bit[7:0]: Dark boost gain threshold 2[7:0]

0xC4C3 DB_GAIN_THRE_22 – RW
en g o

This register value will be automatically initialized by

sensor after powering up. Default value is random.
h

Dark Boost Amount

tia nly

0xC4C4 DB_AMT – RW
This register value will be automatically initialized by
sensor after powering up. Default value is random.

Min Dark Boost Amount

lf

0xC4C5 DB_AMT_MIN – RW
This register value will be automatically initialized by
sensor after powering up. Default value is random.
or

Max Dark Boost Amount

0xC4C6 DB_AMT_MAX – RW
This register value will be automatically initialized by
sensor after powering up. Default value is random.

Combine Error Compensation Step

0xC4C7 ERROR_STEP – RW
This register value will be automatically initialized by
sensor after powering up. Default value is random.

Bit[7:0]: Max dark boost gamma[15:8]

0xC4C8 DB_MAX_GAMMA_1 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-91

table 7-15 combine control registers (sheet 6 of 10)

default
address register name value R/W description
Bit[7:0]: Max dark boost gamma[7:0]

0xC4C9 DB_MAX_GAMMA_2 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.

Bit[7:0]: Dark boost tone width[15:8]

0xC4CA DARK_TONE_WIDTH_1 – RW This register value must be initialized by user and

must not be removed from start up sequence.
Default value is random.
C

0xC4CB DEBUG MODE – – Debug Mode

0x5A08~
on ac

COMB_RO – R Debug Information for Combine Control Registers

0x5A97

Bit[7:3]: Not used

0x5C18 COMB_RO01 – R
Bit[2:0]: pLocalGainBuf0[10:8]
W
fid in

0x5C19 COMB_RO02 – R Bit[7:0]: pLocalGainBuf0[7:0]

Bit[7:3]: Not used

0x5C1A COMB_RO03 – R
Bit[2:0]: pLocalGainBuf1[10:8]
en g o

0x5C1B COMB_RO04 – R Bit[7:0]: pLocalGainBuf1[7:0]

h

Bit[7:3]: Not used

0x5C1C COMB_RO05 – R
tia nly

Bit[2:0]: pLocalGainBuf2[10:8]

0x5C1D COMB_RO06 – R Bit[7:0]: pLocalGainBuf2[7:0]

Bit[7:3]: Not used

lf

0x5C1E COMB_RO07 – R
Bit[2:0]: pLocalGainBuf3[10:8]

0x5C1F COMB_RO08 – R Bit[7:0]: pLocalGainBuf3[7:0]

or

Bit[7:3]: Not used

0x5C20 COMB_RO09 – R
Bit[2:0]: pLocalGainBuf4[10:8]

0x5C21 COMB_RO10 – R Bit[7:0]: pLocalGainBuf4[7:0]

Bit[7:3]: Not used

0x5C22 COMB_RO11 – R
Bit[2:0]: pLocalGainBuf5[10:8]

0x5C23 COMB_RO12 – R Bit[7:0]: pLocalGainBuf5[7:0]

Bit[7:3]: Not used

0x5C24 COMB_RO13 – R
Bit[2:0]: pLocalGainBuf6[10:8]

0x5C25 COMB_RO14 – R Bit[7:0]: pLocalGainBuf6[7:0]

Bit[7:3]: Not used

0x5C26 COMB_RO15 – R
Bit[2:0]: pLocalGainBuf7[10:8]

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-15 combine control registers (sheet 7 of 10)

default
address register name value R/W description
0x5C27 COMB_RO16 – R Bit[7:0]: pLocalGainBuf7[7:0]

Bit[7:3]: Not used

0x5C28 COMB_RO17 – R
Bit[2:0]: pLocalGainBuf8[10:8]

0x5C29 COMB_RO18 – R Bit[7:0]: pLocalGainBuf8[7:0]

Bit[7:3]: Not used

0x5C2A COMB_RO19 – R
Bit[2:0]: pLocalGainBuf9[10:8]

0x5C2B COMB_RO20 – R Bit[7:0]: pLocalGainBuf9[7:0]

Bit[7:3]: Not used

C

0x5C2C COMB_RO21 – R
Bit[2:0]: pLocalGainBuf10[10:8]
on ac

0x5C2D COMB_RO22 – R Bit[7:0]: pLocalGainBuf10[7:0]

Bit[7:3]: Not used

0x5C2E COMB_RO23 – R
Bit[2:0]: pLocalGainBuf11[10:8]
W
fid in

0x5C2F COMB_RO24 – R Bit[7:0]: pLocalGainBuf11[7:0]

Bit[7:3]: Not used

0x5C30 COMB_RO25 – R
Bit[2:0]: pLocalGainBuf12[10:8]
en g o

0x5C31 COMB_RO26 – R Bit[7:0]: pLocalGainBuf12[7:0]

Bit[7:3]: Not used

h

0x5C32 COMB_RO27 – R
Bit[2:0]: pLocalGainBuf13[10:8]
tia nly

0x5C33 COMB_RO28 – R Bit[7:0]: pLocalGainBuf13[7:0]

Bit[7:3]: Not used

0x5C34 COMB_RO29 – R
lf

Bit[2:0]: pLocalGainBuf14[10:8]

0x5C35 COMB_RO30 – R Bit[7:0]: pLocalGainBuf14[7:0]

or

Bit[7:3]: Not used

0x5C36 COMB_RO31 – R
Bit[2:0]: pLocalGainBuf15[10:8]

0x5C37 COMB_RO32 – R Bit[7:0]: pLocalGainBuf15[7:0]

Bit[7:3]: Not used

0x5C38 COMB_RO33 – R
Bit[2:0]: pLocalGainBuf16[10:8]

0x5C39 COMB_RO34 – R Bit[7:0]: pLocalGainBuf16[7:0]

Bit[7:3]: Not used

0x5C3A COMB_RO35 – R
Bit[2:0]: pLocalGainBuf17[10:8]

0x5C3B COMB_RO36 – R Bit[7:0]: pLocalGainBuf17[7:0]

Bit[7:3]: Not used

0x5C3C COMB_RO37 – R
Bit[2:0]: pLocalGainBuf18[10:8]

0x5C3D COMB_RO38 – R Bit[7:0]: pLocalGainBuf18[7:0]

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-93

table 7-15 combine control registers (sheet 8 of 10)

default
address register name value R/W description
Bit[7:3]: Not used
0x5C3E COMB_RO39 – R
Bit[2:0]: pLocalGainBuf19[10:8]

0x5C3F COMB_RO40 – R Bit[7:0]: pLocalGainBuf19[7:0]

Bit[7:3]: Not used

0x5C40 COMB_RO41 – R
Bit[2:0]: pLocalGainBuf20[10:8]

0x5C41 COMB_RO42 – R Bit[7:0]: pLocalGainBuf20[7:0]

Bit[7:3]: Not used

0x5C42 COMB_RO43 – R
Bit[2:0]: pLocalGainBuf21[10:8]
C

0x5C43 COMB_RO44 – R Bit[7:0]: pLocalGainBuf21[7:0]

on ac

Bit[7:3]: Not used

0x5C44 COMB_RO45 – R
Bit[2:0]: pLocalGainBuf22[10:8]

0x5C45 COMB_RO46 – R Bit[7:0]: pLocalGainBuf22[7:0]

W
fid in

Bit[7:3]: Not used

0x5C46 COMB_RO47 – R
Bit[2:0]: pLocalGainBuf23[10:8]

0x5C47 COMB_RO48 – R Bit[7:0]: pLocalGainBuf23[7:0]

en g o

Bit[7:3]: Not used

0x5C48 COMB_RO49 – R
Bit[2:0]: pLocalGainBuf24[10:8]
h

0x5C49 COMB_RO50 – R Bit[7:0]: pLocalGainBuf24[7:0]

tia nly

Bit[7:6]: Not used

0x5C4A COMB_RO51 – R Bit[5:0]: AWBLogRatio_R[13:8]
Two’s complement
lf

Bit[7:0]: AWBLogRatio_R[7:0]
0x5C4B COMB_RO52 – R
Two’s complement
or

Bit[7:6]: Not used

0x5C4C COMB_RO53 – R Bit[5:0]: AWBLogRatio_G[13:8]
Two’s complement

Bit[7:0]: AWBLogRatio_G[7:0]
0x5C4D COMB_RO54 – R
Two’s complement

Bit[7:6]: Not used

0x5C4E COMB_RO55 – R Bit[5:0]: AWBLogRatio_B[13:8]
Two’s complement

Bit[7:0]: AWBLogRatio_B[7:0]
0x5C4F COMB_RO56 – R
Two’s complement

0x5C50 NOT USED – – Not Used

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-15 combine control registers (sheet 9 of 10)

default
address register name value R/W description
Bit[7:1]: Not used
0x5C51 COMB_RO58 – R Bit[0]: LogBlackX[16]
Two’s complement

Bit[7:0]: LogBlackX[15:8]
0x5C52 COMB_RO59 – R
Two’s complement

Bit[7:0]: LogBlackX[7:0]
0x5C53 COMB_RO60 – R
Two’s complement

0x5C54 NOT USED – – Not Used

C

Bit[7:1]: Not used

0x5C55 COMB_RO62 – R Bit[0]: LogBlackY[16]
Two’s complement
on ac

Bit[7:0]: LogBlackY[15:8]
0x5C56 COMB_RO63 – R
Two’s complement

Bit[7:0]: LogBlackY[7:0]
W
fid in

0x5C57 COMB_RO64 – R
Two’s complement

0x5C58 COMB_RO65 – R Bit[7:0]: LogYMax[15:8]

en g o

0x5C59 COMB_RO66 – R Bit[7:0]: LogYMax[7:0]

0x5C5A COMB_RO67 – R Bit[7:0]: LogXMax[15:8]

h

0x5C5B COMB_RO68 – R Bit[7:0]: LogXMax[7:0]

tia nly

Bit[7]: Not used

0x5C5C COMB_RO69 – R
Bit[6:0]: GlobalLogRatio[14:8]
lf

0x5C5D COMB_RO70 – R Bit[7:0]: GlobalLogRatio[7:0]

Bit[7]: Not used

0x5C5E COMB_RO71 – R
or

Bit[6:0]: GlobalLogHDRGain[14:8]

0x5C5F COMB_RO72 – R Bit[7:0]: GlobalLogHDRGain[7:0]

Bit[7:2]: Not used

0x5C60 COMB_RO73 – R
Bit[1:0]: GlobalLogHDRGamma[9:8]

0x5C61 COMB_RO74 – R Bit[7:0]: GlobalLogHDRGamma[7:0]

Bit[7:2]: Not used

0x5C62 COMB_RO75 – R
Bit[1:0]: nCutBlackLevel[9:8]

0x5C63 COMB_RO76 – R Bit[7:0]: nCutBlackLevel[7:0]

0x5C64 COMB_RO77 – R Bit[7:0]: nDarkBoostYThre1[15:8]

0x5C65 COMB_RO78 – R Bit[7:0]: nDarkBoostYThre1[7:0]

0x5C66 COMB_RO79 – R Bit[7:0]: nDarkBoostYThre2[15:8]

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-95

table 7-15 combine control registers (sheet 10 of 10)

default
address register name value R/W description
0x5C67 COMB_RO80 – R Bit[7:0]: nDarkBoostYThre2[7:0]

0x5C68~
NOT USED – – Not Used
0x5C69

Bit[7:0]: nLogE[15:8]
0x5C6A COMB_RO83 – R
Two’s complement

Bit[7:0]: nLogE[7:0]
0x5C6B COMB_RO84 – R
Two’s complement

0x5C6C COMB_RO85 – – Not Used

C

Bit[7:2]: Not used

0x5C6D COMB_RO86 – R
Bit[1:0]: OutputRange[17:16]
on ac

0x5C6E COMB_RO87 – R Bit[7:0]: OutputRange[15:8]

0x5C6F COMB_RO88 – R Bit[7:0]: OutputRange[7:0]

W
fid in

7.16 normalize (NMLZ) control [0x5480 ~ 0x5A98, 0x5C71 ~ 0x5C78]

en g o

table 7-16 NMLZ control registers (sheet 1 of 2)

h

tia nly

default
address register name value R/W description
Bit[7:6]: Not used
lf

0x5480 NORM RW00 0x01 RW Bit[5]: Chip debug

Bit[4:0]: Step
or

Bit[7]: Not used

0x5481 NORM RW01 0x10 RW Bit[6:0]: max_low_level
16 ~ 127

Bit[7:0]: min_low_level
0x5482 NORM RW02 0xF8 RW
-128 to -16, complementary code

Bit[7]: Not used

0x5483 NORM RW03 0x04 RW
Bit[6:0]: ps_thres[14:8]

0x5484 NORM RW04 0x00 RW Bit[7:0]: ps_thres[7:0]

0x5485~
NORM RO – R Debug Information for NMLZ Control
0x5A98

Bit[7:6]: Not used

0x5C71 NML_RW02 – R
Bit[5:0]: nNormalizeGain[21:16]

0x5C72 NML_RW03 – R Bit[7:0]: nNormalizeGain[15:8]

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-16 NMLZ control registers (sheet 2 of 2)

default
address register name value R/W description
0x5C73 NML_RW04 – R Bit[7:0]: nNormalizeGain[7:0]

0x5C74 NOT USED – R Not Used

Bit[7:2]: Not used

0x5C75 NML_RW06 – R
Bit[1:0]: nHDROffset[17:16]

0x5C76 NML_RW07 – R Bit[7:0]: nHDROffset[15:8]

0x5C77 NML_RW08 – R Bit[7:0]: nHDROffset[7:0]

Bit[7:0]: RW_CurLowLevel[7:0]
0x5C78 NML_RW09 – R
C

Signed complementary code

on ac

7.17 tone mapping (TMAP) [0x5500 ~ 0x5511, 0xC4E4 ~ 0xC4F9, 0x5A9C ~

0x5CFB]
W
fid in

table 7-17 TMAP control registers (sheet 1 of 10)

en g o

default
address register name value R/W description
h

Bit[7:3]: Not used

tia nly

Bit[2:0]: edge_thre
000: 16
001: 32
0x5500 TOMP RW00 0x03 RW
010: 64
lf

011: 128
100: 256
101: 512
or

Bit[7:6]: Not used

Bit[5]: h_dark_en
Bit[4]: uv_dark_en
Bit[3:2]: h_dark_thre
00: 16
01: 32
0x5501 TOMP RW01 0x3A RW 10: 48
11: 64
Bit[1:0]: uv_dark_thre
00: 16
01: 32
10: 48
11: 64

Bit[7:1]: Not used

0x5502 TOMP RW02 0x00 RW
Bit[0]: Chip debug

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-97

table 7-17 TMAP control registers (sheet 2 of 10)

default
address register name value R/W description
0x5503 TOMP RW03 0x40 RW Bit[7:0]: Chip debug

0x5504 TOMP RW04 0xC6 RW Chip Debug

Bit[7:4]: Not used

0x5505 TOMP RW05 0x00 RW
Bit[3:0]: Chip debug

Bit[7]: Not used

0x5506 TOMP RW06 0x00 RW
Bit[6:0]: Chip debug

0x5507 TOMP RW07 0x40 RW Bit[7:0]: Chip debug

Bit[7]: Not used

C

0x5508 TOMP RW08 0x04 RW

Bit[6:0]: Chip debug
on ac

0x5509 TOMP RW09 0x00 RW Bit[7:0]: Chip debug

Bit[7]: Not used

0x550A TOMP RW10 0x00 RW
Bit[6:0]: Debug mode
W
fid in

0x550B TOMP RW11 0x00 RW Bit[7:0]: Debug mode

0x550C TOMP RW12 0x00 RW Bit[7:0]: Debug mode

Bit[7:1]: Not used

en g o

0x550D TOMP RW13 0x00 RW

Bit[0]: dbg_sram_freeze
h

0x550E TOMP RW14 0x00 RW Bit[7:0]: dbg_addr

tia nly

0x550F~
TOMP RO – R Debug Information for TMAP Control
0x5511

Contrast Curve 1
lf

0xC4E4 CONTRAST_CURVE_1 – RW This register value must be initialized by user

and must not be removed from start up
or

sequence. Default value is random.

Contrast Curve 2

0xC4E5 CONTRAST_CURVE_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Contrast Curve 3

0xC4E6 CONTRAST_CURVE_3 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-17 TMAP control registers (sheet 3 of 10)

default
address register name value R/W description
Contrast Curve 4

0xC4E7 CONTRAST_CURVE_4 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Contrast Curve 5

0xC4E8 CONTRAST_CURVE_5 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
C

Contrast Curve 6
on ac

0xC4E9 CONTRAST_CURVE_6 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Contrast Curve 7
W
fid in

0xC4EA CONTRAST_CURVE_7 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
en g o

Contrast Curve 8
h

0xC4EB CONTRAST_CURVE_8 – RW This register value must be initialized by user

tia nly

and must not be removed from start up

sequence. Default value is random.

Contrast Curve 9
lf

0xC4EC CONTRAST_CURVE_9 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
or

Contrast Curve 10

0xC4ED CONTRAST_CURVE_10 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Contrast Curve 11

0xC4EE CONTRAST_CURVE_11 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Contrast Curve 12

0xC4EF CONTRAST_CURVE_12 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-99

table 7-17 TMAP control registers (sheet 4 of 10)

default
address register name value R/W description
Contrast Curve 13

0xC4F0 CONTRAST_CURVE_13 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Contrast Curve 14

0xC4F1 CONTRAST_CURVE_14 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
C

Contrast Curve 15
on ac

0xC4F2 CONTRAST_CURVE_15 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Curve Adjustment Step

W
fid in

0xC4F3 CURVE_STEP – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
en g o

Bit[7:0]: Curve min dynamic range[15:8]

h

0xC4F4 CURVE_MIN_DR_1 – RW This register value must be initialized by user

tia nly

and must not be removed from start up

sequence. Default value is random.

Bit[7:0]: Curve min dynamic range[7:0]

lf

0xC4F5 CURVE_MIN_DR_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.
or

Bit[7:0]: Curve max dynamic range[15:8]

0xC4F6 CURVE_MAX_DR_1 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Bit[7:0]: Curve max dynamic range[7:0]

0xC4F7 CURVE_MAX_DR_2 – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

Min Curve Alpha

0xC4F8 CURVE_MIN_ALPHA – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-17 TMAP control registers (sheet 5 of 10)

default
address register name value R/W description
Max Curve Alpha

0xC4F9 CURVE_MAX_ALPHA – RW This register value must be initialized by user

and must not be removed from start up
sequence. Default value is random.

0x5A9C~
TMP_R – R Debug Information for TMAP Control
0x5AAD

Bit[7:2]: Not used

0x5C7D TMP_RO02 – R
Bit[1:0]: pCurveList0[17:16]
C

0x5C7E TMP_RO03 – R Bit[7:0]: pCurveList0[15:8]

0x5C7F TMP_RO04 – R Bit[7:0]: pCurveList0[7:0]

on ac

0x5C80 NOT USED – – Not Used

Bit[7:2]: Not used

0x5C81 TMP_RO06 – R
Bit[1:0]: pCurveList1[17:16]
W
fid in

0x5C82 TMP_RO07 – R Bit[7:0]: pCurveList1[15:8]

0x5C83 TMP_RO08 – R Bit[7:0]: pCurveList1[7:0]

en g o

0x5C84 NOT USED – – Not Used

h

Bit[7:2]: Not used

0x5C85 TMP_RO10 – R
Bit[1:0]: pCurveList2[17:16]
tia nly

0x5C86 TMP_RO11 – R Bit[7:0]: pCurveList2[15:8]

0x5C87 TMP_RO12 – R Bit[7:0]: pCurveList2[7:0]

lf

0x5C88 NOT USED – – Not Used

or

Bit[7:2]: Not used

0x5C89 TMP_RO14 – R
Bit[1:0]: pCurveList3[17:16]

0x5C8A TMP_RO15 – R Bit[7:0]: pCurveList3[15:8]

0x5C8B TMP_RO16 – R Bit[7:0]: pCurveList3[7:0]

0x5C8C NOT USED – – Not Used

Bit[7:2]: Not used

0x5C8D TMP_RO18 – R
Bit[1:0]: pCurveList4[17:16]

0x5C8E TMP_RO19 – R Bit[7:0]: pCurveList4[15:8]

0x5C8F TMP_RO20 – R Bit[7:0]: pCurveList4[7:0]

0x5C90 NOT USED – – Not Used

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-101

table 7-17 TMAP control registers (sheet 6 of 10)

default
address register name value R/W description
Bit[7:2]: Not used
0x5C91 TMP_RO22 – R
Bit[1:0]: pCurveList5[17:16]

0x5C92 TMP_RO23 – R Bit[7:0]: pCurveList5[15:8]

0x5C93 TMP_RO24 – R Bit[7:0]: pCurveList5[7:0]

0x5C94 NOT USED – – Not Used

Bit[7:2]: Not used

0x5C95 TMP_RO26 – R
Bit[1:0]: pCurveList6[17:16]

0x5C96 TMP_RO27 – R Bit[7:0]: pCurveList6[15:8]

C

0x5C97 TMP_RO28 – R Bit[7:0]: pCurveList6[7:0]

on ac

0x5C98 NOT USED – – Not Used

Bit[7:2]: Not used

0x5C99 TMP_RO30 – R
Bit[1:0]: pCurveList7[17:16]
W
fid in

0x5C9A TMP_RO31 – R Bit[7:0]: pCurveList7[15:8]

0x5C9B TMP_RO32 – R Bit[7:0]: pCurveList7[7:0]

en g o

0x5C9C NOT USED – – Not Used

Bit[7:2]: Not used

h

0x5C9D TMP_RO34 – R
Bit[1:0]: pCurveList8[17:16]
tia nly

0x5C9E TMP_RO35 – R Bit[7:0]: pCurveList8[15:8]

0x5C9F TMP_RO36 – R Bit[7:0]: pCurveList8[7:0]

lf

0x5CA0 NOT USED – – Not Used

Bit[7:2]: Not used

or

0x5CA1 TMP_RO38 – R
Bit[1:0]: pCurveList9[17:16]

0x5CA2 TMP_RO39 – R Bit[7:0]: pCurveList9[15:8]

0x5CA3 TMP_RO40 – R Bit[7:0]: pCurveList9[7:0]

0x5CA4 NOT USED – – Not Used

Bit[7:2]: Not used

0x5CA5 TMP_RO42 – R
Bit[1:0]: pCurveList10[17:16]

0x5CA6 TMP_RO43 – R Bit[7:0]: pCurveList10[15:8]

0x5CA7 TMP_RO44 – R Bit[7:0]: pCurveList10[7:0]

0x5CA8 NOT USED – – Not Used

Bit[7:2]: Not used

0x5CA9 TMP_RO46 – R
Bit[1:0]: pCurveList11[17:16]

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-17 TMAP control registers (sheet 7 of 10)

default
address register name value R/W description
0x5CAA TMP_RO47 – R Bit[7:0]: pCurveList11[15:8]

0x5CAB TMP_RO48 – R Bit[7:0]: pCurveList11[7:0]

0x5CAC NOT USED – – Not Used

Bit[7:2]: Not used

0x5CAD TMP_RO50 – R
Bit[1:0]: pCurveList12[17:16]

0x5CAE TMP_RO51 – R Bit[7:0]: pCurveList12[15:8]

0x5CAF TMP_RO52 – R Bit[7:0]: pCurveList12[7:0]

C

0x5CB0 NOT USED – – Not Used

on ac

Bit[7:2]: Not used

0x5CB1 TMP_RO54 – R
Bit[1:0]: pCurveList13[17:16]

0x5CB2 TMP_RO55 – R Bit[7:0]: pCurveList13[15:8]

W
fid in

0x5CB3 TMP_RO56 – R Bit[7:0]: pCurveList13[7:0]

0x5CB4 NOT USED – – Not Used

Bit[7:2]: Not used

en g o

0x5CB5 TMP_RO58 – R
Bit[1:0]: pCurveList14[17:16]
h

0x5CB6 TMP_RO59 – R Bit[7:0]: pCurveList14[15:8]

tia nly

0x5CB7 TMP_RO60 – R Bit[7:0]: pCurveList14[7:0]

0x5CB8 NOT USED – – Not Used

lf

Bit[7:2]: Not used

0x5CB9 TMP_RO62 – R
Bit[1:0]: pCurveList15[17:16]

0x5CBA TMP_RO63 – R Bit[7:0]: pCurveList15[15:8]

or

0x5CBB TMP_RO64 – R Bit[7:0]: pCurveList15[7:0]

Bit[7:2]: Not used

0x5CBC TMP_RO65 – R
Bit[1:0]: pCurveGainList0[9:8]

0x5CBD TMP_RO66 – R Bit[7:0]: pCurveGainList0[7:0]

Bit[7:2]: Not used

0x5CBE TMP_RO67 – R
Bit[1:0]: pCurveGainList1[9:8]

0x5CBF TMP_RO68 – R Bit[7:0]: pCurveGainList1[7:0]

Bit[7:2]: Not used

0x5CC0 TMP_RO69 – R
Bit[1:0]: pCurveGainList2[9:8]

0x5CC1 TMP_RO70 – R Bit[7:0]: pCurveGainList2[7:0]

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-103

table 7-17 TMAP control registers (sheet 8 of 10)

default
address register name value R/W description
Bit[7:2]: Not used
0x5CC2 TMP_RO71 – R
Bit[1:0]: pCurveGainList3[9:8]

0x5CC3 TMP_RO72 – R Bit[7:0]: pCurveGainList3[7:0]

Bit[7:2]: Not used

0x5CC4 TMP_RO73 – R
Bit[1:0]: pCurveGainList4[9:8]

0x5CC5 TMP_RO74 – R Bit[7:0]: pCurveGainList4[7:0]

Bit[7:2]: Not used

0x5CC6 TMP_RO75 – R
Bit[1:0]: pCurveGainList5[9:8]
C

0x5CC7 TMP_RO76 – R Bit[7:0]: pCurveGainList5[7:0]

on ac

Bit[7:2]: Not used

0x5CC8 TMP_RO77 – R
Bit[1:0]: pCurveGainList6[9:8]

0x5CC9 TMP_RO78 – R Bit[7:0]: pCurveGainList6[7:0]

W
fid in

Bit[7:2]: Not used

0x5CCA TMP_RO79 – R
Bit[1:0]: pCurveGainList7[9:8]

0x5CCB TMP_RO80 – R Bit[7:0]: pCurveGainList7[7:0]

en g o

Bit[7:2]: Not used

0x5CCC TMP_RO81 – R
Bit[1:0]: pCurveGainList8[9:8]
h

0x5CCD TMP_RO82 – R Bit[7:0]: pCurveGainList8[7:0]

tia nly

Bit[7:2]: Not used

0x5CCE TMP_RO83 – R
Bit[1:0]: pCurveGainList9[9:8]
lf

0x5CCF TMP_RO84 – R Bit[7:0]: pCurveGainList9[7:0]

Bit[7:2]: Not used

0x5CD0 TMP_RO85 – R
Bit[1:0]: pCurveGainList10[9:8]
or

0x5CD1 TMP_RO86 – R Bit[7:0]: pCurveGainList10[7:0]

Bit[7:2]: Not used

0x5CD2 TMP_RO87 – R
Bit[1:0]: pCurveGainList11[9:8]

0x5CD3 TMP_RO88 – R Bit[7:0]: pCurveGainList11[7:0]

Bit[7:2]: Not used

0x5CD4 TMP_RO89 – R
Bit[1:0]: pCurveGainList12[9:8]

0x5CD5 TMP_RO90 – R Bit[7:0]: pCurveGainList12[7:0]

Bit[7:2]: Not used

0x5CD6 TMP_RO91 – R
Bit[1:0]: pCurveGainList13[9:8]

0x5CD7 TMP_RO92 – R Bit[7:0]: pCurveGainList13[7:0]

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-17 TMAP control registers (sheet 9 of 10)

default
address register name value R/W description
Bit[7:2]: Not used
0x5CD8 TMP_RO93 – R
Bit[1:0]: pCurveGainList14[9:8]

0x5CD9 TMP_RO94 – R Bit[7:0]: pCurveGainList14[7:0]

Bit[7:2]: Not used

0x5CDA TMP_RO95 – R
Bit[1:0]: pCurveGainList15[9:8]

0x5CDB TMP_RO96 – R Bit[7:0]: pCurveGainList15[7:0]

0x5CDC TMP_RO97 – R Bit[7:0]: pCurveSegAList0[7:0]

0x5CDD TMP_RO98 – R Bit[7:0]: pCurveSegAList1[7:0]

C

0x5CDE TMP_RO99 – R Bit[7:0]: pCurveSegAList2[7:0]

on ac

0x5CDF TMP_RO100 – R Bit[7:0]: pCurveSegAList3[7:0]

0x5CE0 TMP_RO101 – R Bit[7:0]: pCurveSegAList4[7:0]

W
fid in

0x5CE1 TMP_RO102 – R Bit[7:0]: pCurveSegAList5[7:0]

0x5CE2 TMP_RO103 – R Bit[7:0]: pCurveSegAList6[7:0]

0x5CE3 TMP_RO104 – R Bit[7:0]: pCurveSegAList7[7:0]

en g o

0x5CE4 TMP_RO105 – R Bit[7:0]: pCurveSegAList8[7:0]

h

0x5CE5 TMP_RO106 – R Bit[7:0]: pCurveSegAList9[7:0]

tia nly

0x5CE6 TMP_RO107 – R Bit[7:0]: pCurveSegAList10[7:0]

0x5CE7 TMP_RO108 – R Bit[7:0]: pCurveSegAList11[7:0]

lf

0x5CE8 TMP_RO109 – R Bit[7:0]: pCurveSegAList12[7:0]

0x5CE9 TMP_RO110 – R Bit[7:0]: pCurveSegAList13[7:0]

or

0x5CEA TMP_RO111 – R Bit[7:0]: pCurveSegAList14[7:0]

0x5CEB TMP_RO112 – R Bit[7:0]: pCurveSegAList15[7:0]

Bit[7:5]: Not used

0x5CEC TMP_RO113 – R
Bit[4:0]: pCurveSegBList0[4:0]

Bit[7:5]: Not used

0x5CED TMP_RO114 – R
Bit[4:0]: pCurveSegBList1[4:0]

Bit[7:5]: Not used

0x5CEE TMP_RO115 – R
Bit[4:0]: pCurveSegBList2[4:0]

Bit[7:5]: Not used

0x5CEF TMP_RO116 – R
Bit[4:0]: pCurveSegBList3[4:0]

Bit[7:5]: Not used

0x5CF0 TMP_RO117 – R
Bit[4:0]: pCurveSegBList4[4:0]

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-105

table 7-17 TMAP control registers (sheet 10 of 10)

default
address register name value R/W description
Bit[7:5]: Not used
0x5CF1 TMP_RO118 – R
Bit[4:0]: pCurveSegBList5[4:0]

Bit[7:5]: Not used

0x5CF2 TMP_RO119 – R
Bit[4:0]: pCurveSegBList6[4:0]

Bit[7:5]: Not used

0x5CF3 TMP_RO120 – R
Bit[4:0]: pCurveSegBList7[4:0]

Bit[7:5]: Not used

0x5CF4 TMP_RO121 – R
Bit[4:0]: pCurveSegBList8[4:0]

Bit[7:5]: Not used

C

0x5CF5 TMP_RO122 – R
Bit[4:0]: pCurveSegBList9[4:0]
on ac

Bit[7:5]: Not used

0x5CF6 TMP_RO123 – R
Bit[4:0]: pCurveSegBList10[4:0]

Bit[7:5]: Not used

0x5CF7 TMP_RO124 – R
Bit[4:0]: pCurveSegBList11[4:0]
W
fid in

Bit[7:5]: Not used

0x5CF8 TMP_RO125 – R
Bit[4:0]: pCurveSegBList12[4:0]

Bit[7:5]: Not used

en g o

0x5CF9 TMP_RO126 – R
Bit[4:0]: pCurveSegBList13[4:0]

Bit[7:5]: Not used

h

0x5CFA TMP_RO127 – R
Bit[4:0]: pCurveSegBList14[4:0]
tia nly

Bit[7:5]: Not used

0x5CFB TMP_RO128 – R
Bit[4:0]: pCurveSegBList15[4:0]
lf

7.18 frame counter (FC) control [0x4200 ~ 0x4203]

or

table 7-18 FC control registers (sheet 1 of 2)

default
address register name value R/W description
Bit[7:3]: Not used
Bit[2]: fcnt_eof_sel
0x4200 FC_R0 0x00 RW
Bit[1]: fcnt_mask_dis
Bit[0]: fcnt_reset

Bit[7:4]: Not used

0x4201 FC_R1 0x00 RW
Bit[3:0]: frame_on_number

Bit[7:4]: Not used

0x4202 FC_R2 0x00 RW
Bit[3:0]: frame_off_number

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-18 FC control registers (sheet 2 of 2)

default
address register name value R/W description
Bit[7]: Not used
Bit[6]: rblue_mask_dis
Bit[5]: data_mask_dis
Bit[4]: valid_mask_dis
0x4203 FC_R3 0x00 RW
Bit[3]: href_mask_dis
Bit[2]: eof_mask_dis
Bit[1]: sof_mask_dis
Bit[0]: all_mask_dis

7.19 format control [0x4300, 0x4302 ~ 0x4309]

C
on ac

table 7-19 format control registers

default
W
fid in

address register name value R/W description

Bit[7:4]: Output format select
0x3: YUV mode
en g o

0xF: RAW mode

Others: Not allowed
0x4300 FORMAT_CTRL00 0xF8 RW Bit[3:0]: pix_order_ctrl
h

1000: YUYV
tia nly

1001: YVYU
1010: UYVY
1011: VYUY

Bit[7:2]: Not used

lf

0x4302 FORMAT_YMAX 0x03 RW

Bit[1:0]: Ymax[9:8]

0x4303 FORMAT_YMAX 0xFF RW Bit[7:0]: Ymax[7:0]

or

Bit[7:2]: Not used

0x4304 FORMAT_YMIN 0x00 RW
Bit[1:0]: Ymin[9:8]

0x4305 FORMAT_YMIN 0x00 RW Bit[7:0]: Ymin[7:0]

Bit[7:2]: Not used

0x4306 FORMAT_UMAX 0x03 RW
Bit[1:0]: Umax[9:8]

0x4307 FORMAT_UMAX 0xFF RW Bit[7:0]: Umax[7:0]

Bit[7:2]: Not used

0x4308 FORMAT_UMIN 0x00 RW
Bit[1:0]: Umin[9:8]

0x4309 FORMAT_UMIN 0x00 RW Bit[7:0]: Umin[7:0]

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-107

7.20 VFIFO control [0x4600 ~ 0x4603, 0x4605 ~ 0x4613, 0x4620 ~ 0x4639]

table 7-20 VFIFO control registers (sheet 1 of 3)

default
address register name value R/W description
Bit[7:4]: Not used
Bit[3]: r_fi_pt
VFIFO bypass
VFIFO_AFIFO_SRAM
0x4600 0x04 RW Bit[2]: r_16bitin
_CTRL
16-bit data into AFIFO
Bit[1]: r_sram_pt
Bit[0]: r_sram_nofrst
C

0x4601 DEBUG MODE – – Debug Mode

on ac

VFIFO_FIRST1_
0x4602 0x00 RW Bit[7:0]: r_first_pos_high
POSITION

VFIFO_FIRST1_
0x4603 0x00 RW Bit[7:0]: r_first_pos_low
POSITION
W
fid in

Bit[7:4]: Not used

Bit[3]: r_8b_yuv422
0: 10-bit YUV422 mode
en g o

VFIFO_LLEN_FIRS1_ 1: 8-bit YUV422 mode

0x4605 0x08 RW
SEL Bit[2]: Line length select
0: Auto mode
h

1: From registers 0x4606, 0x4607

tia nly

Bit[1:0]: r_first_sel in readout module

VFIFO_LINE_LENGTH
0x4606 0x00 RW Bit[7:0]: Manual set line length[15:8]
_MAN
lf

VFIFO_LINE_LENGTH
0x4607 0x00 RW Bit[7:0]: Manual set line length[7:0]
_MAN
or

0x4608 VFIFO_READ_START 0x00 RW Bit[7:0]: Read start[15:8]

0x4609 VFIFO_READ_START 0x08 RW Bit[7:0]: Read start[7:0]

VFIFO_HSYNC_
0x460A 0x00 RW Bit[7:0]: r_hsync_st[15:8]
START_POSITION

VFIFO_HSYNC_
0x460B 0xBF RW Bit[7:0]: r_hsync_st[7:0]
START_POSITION

Bit[7:4]: HSYNC header width

0x460C VFIFO_HSYNC_CTRL 0x00 RW
Bit[3:0]: HSYNC trail width

0x460D DEBUG MODE – – Debug Mode

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-20 VFIFO control registers (sheet 2 of 3)

default
address register name value R/W description
Bit[7:4]: Not used
Bit[3]: r_sof_clr_ram default 1
Bit[2]: r_st_mod
VFIFO_EMBD_LINE_ 0: PCLK cycles trigger (default)
0x460E 0x08 RW
CTRL 1: Byte size trigger
Bit[1]: Debug mode
Bit[0]: r_embd_en
Embedded line mode enable

VFIFO_EMBD_LINE_
0x460F 0x01 RW Bit[7:0]: Embedded line amount
NUM
C

0x4610 EMB_ST_PCNT_H 0x00 RW High Byte of Embedded Line Pcnt Start Point

0x4611 EMB_ST_PCNT_L 0x01 RW Low Byte of Embedded Line Pcnt Start Point
on ac

0x4612 EMB_ST_LCNT_H 0x00 RW High Byte of Embedded Line Lcnt Start Point

0x4613 EMB_ST_LCNT_L 0x01 RW Low Byte of Embedded Line Lcnt Start Point
W
fid in

Bit[7]: r_roi_sync_byp
Bit[6]: r_fr_comp
ROI output 8-bit data
Front comp 2-bit 0 or back
en g o

Bit[5]: r_full_dat_mod
0x4620 ROI_CTRL0 0x0E RW
Bit[4]: Not used
h

Bit[3]: r_roi_en_3
Bit[2]: r_roi_en_2
tia nly

Bit[1]: r_roi_en_1
Bit[0]: r_roi_func_e

Bit[7]: Not used

lf

Bit[6:4]: r_sc_fsz_delay
0x4621 ROI_CTRL1 0x31 RW
Bit[3:0]: roi_sync_cod_stv
Sync code start
or

0x4622 ROI_XOFFS_1 0x00 RW Window 1 Xoffset High Byte

0x4623 ROI_XOFFS_1 0x00 RW Window 1 Xoffset Low Byte

0x4624 ROI_YOFFS_1 0x00 RW Window 1 Yoffset High Byte

0x4625 ROI_YOFFS_1 0x00 RW Window 1 Yoffset Low Byte

0x4626 ROI_XOFFS_2 0x02 RW Window 2 Xoffset High Byte

0x4627 ROI_XOFFS_2 0x4E RW Window 2 Xoffset Low Byte

0x4628 ROI_YOFFS_2 0x01 RW Window 2 Yoffset High Byte

0x4629 ROI_YOFFS_2 0x5E RW Window 2 Yoffset Low Byte

0x462A ROI_XOFFS_3 0x04 RW Window 3 Xoffset High Byte

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-109

table 7-20 VFIFO control registers (sheet 3 of 3)

default
address register name value R/W description
0x462B ROI_XOFFS_3 0x9C RW Window 3 Xoffset Low Byte

0x462C ROI_YOFFS_3 0x02 RW Window 3 Yoffset High Byte

0x462D ROI_YOFFS_3 0xBC RW Window 3 Yoffset Low Byte

Bit[7:1]: Not used

0x462E ROI_HSIZE1_H 0x00 RW
Bit[0]: Window 1 hsize[8]

0x462F ROI_HSIZE1_L 0x64 RW Bit[7:0]: Window 1 hsize[7:0]

Bit[7:2]: Not used

0x4630 ROI_VSIZE1_H 0x00 RW
C

Bit[1:0]: roi_vsize1[9:8]

0x4631 ROI_VSIZE1_L 0x64 RW Bit[7:0]: roi_vsize1[7:0]

on ac

Bit[7:1]: Not used

0x4632 ROI_HSIZE2_H 0x00 RW
Bit[0]: roi_hsize2[8]

0x4633 ROI_HSIZE2_L 0x64 RW Bit[7:0]: roi_hsize2[7:0]

W
fid in

Bit[7:2]: Not used

0x4634 ROI_VSIZE2_H 0x00 RW
Bit[1:0]: roi_vsize2[9:8]

0x4635 ROI_VSIZE2_L 0x64 RW Bit[7:0]: roi_vsize2[7:0]

en g o

Bit[7:1]: Not used

0x4636 ROI_HSIZE3_H 0x00 RW
h

Bit[0]: roi_hsize3[8]
tia nly

0x4637 ROI_HSIZE3_L 0x64 RW Bit[7:0]: roi_hsize3[7:0]

Bit[7:2]: Not used

0x4638 ROI_VSIZE3_H 0x00 RW
Bit[1:0]: roi_vsize3[9:8]
lf

0x4639 ROI_VSIZE3_L 0x64 RW Bit[7:0]: roi_vsize3[7:0]

or

7.21 digital video port (DVP) control [0x4700 ~ 0x470D]

table 7-21 DVP control registers (sheet 1 of 4)

default
address register name value R/W description
Bit[7:4]: Not used
Bit[3]: CCIR v select
0x4700 DVP_MOD_SEL 0x04 RW Bit[2]: CCIR f value
Bit[1]: CCIR656 mode enable
Bit[0]: HSYNC mode enable

0x4701 DVP_VSYNC_WIDTH 0x01 RW VSYNC Length, Line Count

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-21 DVP control registers (sheet 2 of 4)

default
address register name value R/W description
0x4702 DVP_HSYVSY_NEG_WIDTH 0x00 RW VSYNC Length, Pixel Count High Byte

0x4703 DVP_HSYVSY_NEG_WIDTH 0x01 RW VSYNC Length, Pixel Count Low Byte

Bit[7:4]: Not used

Bit[3:2]: r_vsyncout_sel
0x4704 DVP_VSYNC_MODE 0x00 RW
Bit[1]: r_vsync3_mod
Bit[0]: r_vsync2_mod

SOF/EOF Negative Edge to VSYNC

0x4705 DVP_EOF_VSYNC_DELAY 0x00 RW
Positive Edge High Byte
C

SOF/EOF Negative Edge to VSYNC

0x4706 DVP_EOF_VSYNC_DELAY 0x00 RW
Positive Edge Middle Byte
on ac

SOF/EOF Negative Edge to VSYNC

0x4707 DVP_EOF_VSYNC_DELAY 0x00 RW
Positive Edge Low Byte

Bit[7]: Debug mode

Bit[6]: Not used
W
fid in

Bit[5]: VSYNC gate clock enable

Bit[4]: HREF gate clock enable
0x4708 DVP_POL_CTRL 0x01 RW Bit[3]: No first for FIFO
Bit[2]: HREF polarity
en g o

Bit[1]: VSYNC polarity

Bit[0]: PCLK polarity / PCLK gate
h

low enable
tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-111

table 7-21 DVP control registers (sheet 3 of 4)

default
address register name value R/W description
Bit[7]: Debug control
Bit[6:4]: Data bit swap
000: Data[9:0] outputs
through pin D[9:0]
001: Data[0:9] outputs
through pin D[9:0]
010: {Data[2:9], Data[1:0]}
outputs through pin
D[9:0]
011: {Data[7:0], Data[9:8]}
outputs through pin
C

D[9:0]
100: {Data[9:8], Data[0:7]}
outputs through pin
on ac

D[9:0]
101: {Data[9], Data[0:8]}
outputs through pin
D[9:0]
W
fid in

110: {Data[1:9], Data[0]}

outputs through pin
D[9:0]
111: {Data[8:0], Data[9]}
en g o

outputs through pin

0x4709 DVP_MOTO_ORDER 0x00 RW D[9:0]
Bit[3]: Walking one pattern option
h

0: Normal working one

tia nly

pattern
1: Repeat each data one
time in walking one
pattern. e.g., 8-bit
lf

pattern changes to
0x00 -> 0x00 -> 0x01 ->
0x01 -> 0x02-> 0x02 ->
or

0x04-> 0x04 -> 0x08 ->

0x08 -> 0x10 -> 0x10 ->
0x20 -> 0x20 -> 0x40 ->
0x40 -> 0x80 -> 0x80 ->
0xFF -> 0xFF
Bit[2:1]: Walking one pattern
selection
00: Debug option
01: 8-bit walking one
pattern for 8 most
significant pins: 0x00 ->
0x01 -> 0x02-> 0x04->
0x08 -> 0x10 -> 0x20 ->
0x40 -> 0x80 -> 0xFF

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-21 DVP control registers (sheet 4 of 4)

default
address register name value R/W description
10: 10-bit walking one
pattern for 10 data pins
0x000 -> 0x001 ->
0x002-> 0x004->
0x008 -> 0x010 ->
0x020 -> 0x040 ->
0x080 -> 0x100 ->
0x200 -> 0x3FF
11: Debug option
Bit[0]: Walking one test pattern
enable
C

0: Disable
1: Enable
on ac

0x470A DVP_BYP_SEL 0x00 RW Bypass Enable High Byte

0x470B DVP_BYP_SEL 0x00 RW Bypass Enable Low Byte

Bit[7:5]: Not used

W
fid in

0x470C DVP_ BYPASS 0x00 RW Bit[4]: Debug mode

Bit[3:0]: bypass_sel

Bit[7:3]: Not used

en g o

Bit[2:0]: ROI HREF output select

000: Combine HREF out via
dvp_href_o
h

001: 1/2 sc HREF out via

tia nly

dvp_href_o
0x470D DVP_ROI_HREF_SEL 0x00 RW
010: ROI window 1 out via
dvp_href_o
011: ROI window 2 out via
lf

dvp_href_o
100: ROI window 3 out via
dvp_href_o
or

7.22 embedded line control [0x6800 ~ 0x6807]

table 7-22 embedded line control (EMB) registers (sheet 1 of 2)

default
address register name value R/W description
Bit[7:1]: Not used
0x6800 EMB_LINE_EN 0x00 RW
Bit[0]: emb_line enable

0x6801 EMB_LINE_TAG 0xDA RW Bit[7:0]: emb_line tag[9:2]

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 7-113

table 7-22 embedded line control (EMB) registers (sheet 2 of 2)

default
address register name value R/W description
Bit[7:2]: Not used
0x6802 EMB_LINE_TAG 0x01 RW
Bit[1:0]: emb_line tag[1:0]

Bit[7:4]: s2h_width
0x6803 EMB_LINE_SOF_CTRL 0x11 RW
Bit[3:0]: sof_width

Bit[7:1]: Not used

0x6804 EMB_SIZE_MANU_EN 0x00 RW
Bit[0]: emb_size manual enable

Bit[7:4]: Not used

0x6805 EMB_SIZE_MANU 0x04 RW
Bit[3:0]: emb_size[11:8]

0x6806 EMB_SIZE_MANU 0x00 RW Bit[7:0]: emb_size[7:0]

C

Bit[7:1]: Not used

0x6807 EMB_MASK_EN 0x01 RW
on ac

Bit[0]: emb_line mask enable

7.23 group writer [0x6F00, 0x6F04 ~ 0x6F1F]

W
fid in

table 7-23 group writer registers (sheet 1 of 2)

en g o

default
h

address register name value R/W description

tia nly

Bit[7:6]: Operation code

00: Group record end
01: Group launch (only
once)
lf

10: Group launch (ABC

mode)
11: Group record start
or

In ABC mode, group0 is for

0x6F00 GROUP WRITER COMMAND 0x00 RW
frame A, group1 is for frame
B and group2 is for frame C.
Three groups launch
periodically.
Bit[5:4]: Group ID
Bit[3:2]: Chip debug
Bit[1:0]: Group write function enable,
must be 2'b11

0x6F04 PARI_ADDR_MIN 0x00 RW Debug Control

0x6F05 PARI_ADDR_MIN 0x06 RW Debug Control

Group Write Command Register

0x6F06 PARI_ADDR_MIN 0x00 RW
Address, Must Be 0x6F

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 7-23 group writer registers (sheet 2 of 2)

default
address register name value R/W description
Group Write Command Register
0x6F07 PARI_ADDR_MIN 0x00 RW
Address, Must Be 0x00

0x6F08 PARI_ADDR_MAX 0x00 RW Debug Control

0x6F09 PARI_ADDR_MAX 0x06 RW Debug Control

Group Write Command Register

0x6F0A PARI_ADDR_MAX 0x6D RW
Address, Must Be 0x6F

Group Write Command Register

0x6F0B PARI_ADDR_MAX 0xFF RW
Address, Must Be 0x00
C

0x6F0C~
PARI_MASTER_SEL – RW Debug Control
0x6F1F
on ac

7.24 macro-code [0xD000 ~ 0xDFFF]

W
fid in

table 7-24 macro-code registers

en g o

default
address register name value R/W description
h

Macro-code Registers
tia nly

0xD000~
MACRO-CODE REGISTERS – – Can not be deleted. Sensor functions are
0xDFFF
combined with such settings
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 8-1

8 operating specifications
8.1 absolute maximum ratings

table 8-1 absolute maximum ratings

parameter absolute maximum ratinga

ambient storage temperature -50°C to +125°C

VDD-A 4.5V
supply voltage (with respect to ground)
VDD-IO 4.5V
C

all input/output voltages (with respect to ground) -0.3V to VDD-IO + 1V

I/O current on any input or output pin ± 200 mA

on ac

peak solder temperature (10 second dwell time) 245°C

a. exceeding the absolute maximum ratings shown above invalidates all AC and DC electrical specifications and may
result in permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods
W
fid in

may affect device reliability.

en g o

8.2 functional temperature

h

tia nly

table 8-2 functional temperature

parameter range
lf

operating temperaturea -30°C to +85°C junction temperature

stable image temperature 0°C to +50°C junction temperature

or

a. sensor functions in the operating range; however, some image quality changes may be noticed at the temperature
extremes

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

8.3 DC characteristics

table 8-3 DC characteristics (-30°C < TJ < +85°C)

symbol parameter min typ max unit

supply
VDD-A supply voltage (analog) 3.14 3.3 3.47 V

VDD-IO supply voltage (digital I/O) 1.7 1.8 3.47 V

IDD-A 60 85 mA

IDD-D active (operating) current 170 240 mA

C

a
IDD-IO 30 mA
on ac

IDDS-PWDN-A 5 µA

IDDS-PWDN-D standby currentb 270 µA

IDDS-PWDN-IO 10 µA
W
fid in

digital inputs (typical conditions: AVDD = 3.3V, DOVDD = 1.8V)

VIL input voltage LOW 0.54 V
en g o

VIH input voltage HIGH 1.26 V

CIN input capacitor 10 pF

h

digital outputs (standard loading 25 pF)

tia nly

VOH output voltage HIGH 1.62 V

VOL output voltage LOW 0.18 V

lf

serial interface inputs

VILc SIOC and SIOD -0.5 0.0 0.54 V
or

c
VIH SIOC and SIOD 1.26 1.8 2.3 V

a. varies with loading

b. standby current based on room temperature
c. based on DOVDD = 1.8V; minimum input voltage high = 0.7 × DOVDD; maximum input voltage low = 0.3 × DOVDD;
output voltage high = 0.9 × DOVDD; output voltage low = 0.1 × DOVDD

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 8-3

8.4 AC characteristics

table 8-4 AC characteristics (TA = 25°C, VDD-A = 3.3V, VDD-IO = 1.8V)

symbol parameter min typ max unit

ADC parameters
B analog bandwidth 48 MHz

DLE DC differential linearity error <0.5 LSB

ILE DC integral linearity error <0.5 LSB

settling time for software reset <1 ms

C

settling time for resolution mode change <1 ms

on ac

settling time for register setting <300 ms

W
fid in

table 8-5 timing characteristics

symbol parameter min typ max unit

en g o

oscillator and clock input

fOSC frequency (XVCLK) 24 MHz
h

tia nly

tr, tf clock input rise/fall time 5 (10a) ns

a. if using the internal PLL

lf
or

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

C
on ac
W
fid in
en g o
h

tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 9-1

9 mechanical specifications
9.1 physical specifications

figure 9-1 package specifications

L1
S2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 14 13 12 11 10 9 8 7 6 5 4 3 2 1

L2 A A
B B
C J2 C
D D
E E center of BGA (die) =
F F center of the package
B G
WX Y Z G
C

H ABCD H
J J
K K
on ac

L L
M M
N N
D
J1
W
fid in

A
S1
top view bottom view
(bumps down) (bumps up)
C2 glass die C4 note mark code:
W - OVT product version
X - year the part is assembled
en g o

Y - month the part is assembled

Z - wafer number
C1 C3 C ABCD - last four digits of lot number
side view
h

tia nly

table 9-1 package dimensions (sheet 1 of 2)

lf

parameter symbol min typ max unit

package body dimension x A 7770 7795 7820 µm
or

package body dimension y B 7120 7145 7170 µm

package height C 690 750 810 µm

ball height C1 100 130 160 µm

package body thickness C2 575 620 665 µm

thickness of glass surface to wafer C3 425 445 465 µm

image plane height C4 250 305 360 µm

ball diameter D 220 250 280 µm

total pin count N 129

pin count x-axis N1 14

pin count y-axis N2 13

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

table 9-1 package dimensions (sheet 2 of 2)

parameter symbol min typ max unit

pins pitch x-axis J1 510 µm

pins pitch y-axis J2 500 µm

first pixel to package edge dimension A L1 6667.7 6702.7 6737.7 µm

first pixel to package edge dimension B L2 1068.1 1103.1 1138.1 µm

edge-to-pin center distance along x S1 553 583 613 µm

edge-to-pin center distance along y S2 543 573 603 µm

air gap between die and glass 40 45 50 µm

tilt between die and glass 0.2 degree

C

die rotation 0.1 degree

on ac
W
fid in
en g o
h

tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 9-3

9.2 IR reflow specifications

figure 9-2 IR reflow ramp rate requirements

260.0 Tp

240.0
tL TL
220.0
note
Tmax
200.0 reflow
180.0 The OV9623 uses a
temperature (°C)

160.0 Tmin lead free package.

cooling
140.0 soaking

120.0
100.0
80.0
C

ramp up
60.0
40.0
on ac

20.0 T0 Tf
0.0
0

20

40

60

80

100

120

140

160

180

200

220

240

260

280

300

320

340

360

380

400

420

440

460

480

500

520

540
W
fid in

time (sec)

table 9-2 reflow conditionsab

note
en g o

zone description exposure

OmniVision
ramp up A (T0 to Tmin) heating from room temperature to 150°C temperature slope ≤ 3°C per second recommends CSP
h

soaking heating from 150°C to 200°C 90 ~ 150 seconds packages use underfill
tia nly

as part of camera
ramp up B (tL to TP) heating from 217°C to 245°C temperature slope ≤ 3°C per second assembly process.

peak temperature maximum temperature in SMT 245°C +0/-5°C (duration max 30 sec)
lf

reflow (tL to TL) temperature higher than 217°C 30 ~ 120 seconds

ramp down A (TP to TL) cooling from 245°C to 217°C temperature slope ≤ 3°C per second
or

ramp down B (TL to Tf) cooling from 217°C to room temperature temperature slope ≤ 2°C per second

T0 to TP room temperature to peak temperature ≤ 8 minutes

a. maximum number of reflow cycles = 3

b. N2 gas reflow or control O2 gas PPM<500 as recommendation

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

C
on ac
W
fid in
en g o
h

tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 10-1

10 optical specifications
10.1 sensor array center

figure 10-1 sensor array center

5510.4 µm

A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13

first pixel readout
(2805.2 µm, 2469.4 µm)
C

array center
on ac

3418.8 µm (50 µm, 760 µm)

package center
W
fid in

sensor array (0 µm, 0 µm)

en g o
h

OV9623
tia nly

top view
lf

note 1 this drawing is not to scale and is for reference only.

or

note 2 as most optical assemblies invert and mirror the image, the chip is
typically mounted with pin A2 to A13 oriented down on the PCB.

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

10.2 lens chief ray angle (CRA)

figure 10-2 chief ray angle (CRA)

10

8
CRA (degrees)

6
C

4
on ac

2
W
fid in

CRA
0
en g o
0.00

0.50

1.00

1.50

2.00

2.50

3.00

3.50
h

image height (mm)

tia nly

table 10-1 CRA versus image height plot (sheet 1 of 2)

lf

field (%) image height (mm) CRA (degrees)

or

0.00 0.000 0.0

0.05 0.158 0.5

0.10 0.317 1.0

0.15 0.475 1.5

0.20 0.634 2.0

0.25 0.792 2.5

0.30 0.951 3.0

0.35 1.109 3.4

0.40 1.268 3.9

0.45 1.426 4.4

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 10-3

table 10-1 CRA versus image height plot (sheet 2 of 2)

field (%) image height (mm) CRA (degrees)

0.50 1.585 4.9

0.55 1.743 5.3

0.60 1.902 5.8

0.65 2.060 6.2

0.70 2.219 6.6

0.75 2.377 7.1

0.80 2.536 7.5

0.85 2.694 7.9

C

0.90 2.853 8.2

on ac

0.95 3.011 8.6

1.00 3.170 9.0

W
fid in
en g o
h

tia nly
lf
or

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

10.3 spectrum response curve

Stray infrared light can affect image quality in various ways, from color crosstalk to internal reflections from metal
surfaces. To reduce these artifacts, OmniVision recommends an IR-cut filter that maintains near 0% transmission from
700nm to 1200nm. The camera application, acceptable artifacts, and packaging type will dictate the exact IR-cut
specifications. For further assistance, contact your regional OmniVision FAE.

figure 10-3 spectrum response curve diagram

R
Gr
Gb
B
C
on ac
QE
W
fid in
en g o
h

tia nly

300 400 500 600 700 800 900 1000 1100

wavelength (nm)
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 rev-1

revision history

version 1.0 10.14.2015

• initial release

version 1.01 10.28.2015

• in key specifications, added stable image temperature range

• in table 9-2, added stable image temperature range
C

version 1.1 11.06.2015

• in section 4.3, added "VTS is adjusted by registers (0x6E42[7:0], 0x6E43[7:0]). The reference
on ac

initialization settings must be used for these two registers to be valid." to end of section
• in table 4-6, added register 0xC2ED
• in table 7-7, added register 0xC2ED
W
fid in

version 1.11 01.21.2016

en g o

• in key specifications, changed operating temperature range to "-40°C to +105°C sensor ambient
temperature (operating sensor ambient temperatures above 60°C may result in degraded image
h

quality)"
tia nly

• in table 8-2, changed operating temperature range to "-40°C to +105°C sensor ambient
temperature"
lf

version 1.12 03.24.2016

• in key specifications, changed operating temperature range to "-30°C to +85°C junction

or

temperature"
• in table 8-2, changed operating temperature range to "-30°C to +85°C junction temperature"

version 1.2 08.04.2017

• in chapter 6, removed section 6.1

• in table 7-4, changed name, default value, R/W, and description of register 0x3827 to RSVD, –, –,
and Reserved, respectively
• in chapter 7, removed section 7.23

version 1.21 09.12.2017

• in key specifications, removed dark current

12.17.2019 PRELIMINARY SPECIFICATION proprietary to OmniVision Technologies

Powered by TCPDF (www.tcpdf.org)

 OV9623 color CMOS WXGA (1280x800) high dynamic range (HDR) high definition (HD) image sensor

version 1.22 06.22.2018

• in chapter 5, updated section 5.12 completely with new content and removed section 5.14
• in chapter 7, removed table 7-10

version 1.23 12.17.2019

• changed references of mCSP to CSP throughout entire document

• in ordering information, changed ordering part number to "OV09623-N29A..."
C
on ac
W
fid in
en g o
h

tia nly
lf
or

proprietary to OmniVision Technologies PRELIMINARY SPECIFICATION version 1.23

Powered by TCPDF (www.tcpdf.org)

 Future in Sight® C
on ac
W
fid in
en g o
h

tia nly
lf

OmniVision Technologies, Inc.

or

UNITED STATES CHINA JAPAN

4275 Burton Drive Shanghai + 86 21 6175 9888 Yokohama +81 45 478 7977
Santa Clara, CA 95054 +86 21 6154 8000 Kyoto +81 75 708 5352
tel: +1 408 567 3000 Beijing + 86 10 8642 4200
Shenzhen + 86 755 8435 9733 NORWAY
Chicago +1 847 508 0217
Detroit +1 248 919 6900 Wuhan +86 27 5975 7800 Oslo +47 2295 8100

Optics Division +1 303 449 5593 Xian +86 29 8885 2537

SINGAPORE +65 6933 1933
INDIA
UNITED KINGDOM TAIWAN
Bangalore +91 80 4112 8966
Hants +44 1252 761601
Taipei +886 2 2657 9800
KOREA Hsin-chu +886 3 5656688
GERMANY
Seoul + 82 2 3472 3769
Munich +49 89 6381 9988

website: www.ovt.com
Powered by TCPDF (www.tcpdf.org)