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What Is Packaging P1

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21 views12 pages

What Is Packaging P1

Uploaded by

Thu Mai
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Introduction to Semiconductor Packaging and Design

What is Packaging?
Terry Alford
9/4/24 5:30 p.m. - 9 p.m.
Introduction to Semiconductor Packaging and Design

• What is Semiconductor Packaging?


• Silicon to Semiconductor Package
• Packing Evolves as scaling creates
Session Topics new markets
• Moore’s Law
• Summary
Introduction to Semiconductor Packaging and Design

What is Semiconductor Packaging?


• All integrated circuits (ICs) are packaged at the IC-level to form IC
packages, and at the system level to form system boards.
Introduction to Semiconductor Packaging and Design

Why package
semiconductor die?
• All circuitry is made on a silicon die
• Semiconductor packaging connects the circuitry to
• the rest of the system
• Dimensional hierarchy: need to go from nm to mm
• Electrical: Circuits need power to operate. Circuits
• have signals that communicate to the system
• or other die on the package
• Mechanical: circuits are fragile and susceptible to
• environmental stresses
• Thermal: circuits can overheat quickly
• Heterogeneous Integration: optimize functionality
Introduction to Semiconductor Packaging and Design

Dimensional Hierarchy
Introduction to Semiconductor Packaging and Design

Why not directly attach the Die?

• All Requires advanced Printed Circuit Board (PCB) feature sizes (cost!)
• Drives advanced board assembly processes & materials technology (cost!)
Introduction to Semiconductor Packaging and Design

Silicon to Semiconductor Package


Introduction to Semiconductor Packaging and Design

Packaging Evolves As Scaling Creates New


Markets 1970’s
Wirebond
Leadframe
Plastic & Ceramic
Low Pincount DIPs

1990’s
Wirebond & Flipchip
Laminate
Ceramic & Organic
High Pincount PGA
Thermally Enhanced

2000’s
Pb-Free Flipchip
Very Thin Laminate
Organic
High Pincount LGA &
BGA
Ultra-Small Form Factors
Introduction to Semiconductor Packaging and Design

New Markets Demand New and


Greater Capabilities

2010’s & 2020’s Embedded Silicon


Silicon Interposer
Heterogeneous Integration
High Bandwidth Memory
Silicon Photonics
Introduction to Semiconductor Packaging and Design

Moore’s Law

Deliver lower cost


@ iso-features
OR
Higher compute
@ iso-die size
Introduction to Semiconductor Packaging and Design

Next Generation Packaging Trends


1. Adapting packaging capabilities to match Moore’s Law's pace
2. Providing a reduced package size for streamlined systems
3. Enabling diverse integration for enhanced functionality
Introduction to Semiconductor Packaging and Design

Summary
• Semiconductor packaging is the vital link between the silicon
circuitry facilitating power and signal management, safeguarding the
silicon circuitry, efficient cooling, and enabling scalability across
various length scales.
• Emphasizing the necessity of heterogeneous integration to unlock
enhanced functionalities.

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