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Semiconductor Die Processing and Packaging

Article in International Journal of Information and Electronics Engineering · April 2012

DOI: 10.7763/IJIEE.2012.V2.116

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Satya Sai Srikant Rajendra PRASAD Mahapatra

SRM University Modinagar SRM Institute of Science and Technology
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 International Journal of Information and Electronics Engineering, Vol. 2, No. 3, May 2012

Semiconductor Die: Processing and Packaging

Satya Sai Srikant and Rajendra Prasad Mahapatra

prior allocating to Manufacturing Unit.

Abstract—This paper presents the processes, steps and
inspections, various testing stages involved starting from
procurement of wafer onwards to individual Die form. Any III. WAFER’S INSPECTION
semiconductor die or integrated circuit must performed all the
processes of inspection and testing once it receives from any A. Wafer Inspections
manufacturer and then it has to be procured to any
The Semiconductor Die from Manufacturer comes in a
Manufacturing Line for further process as a part of any
Manufacturing products. This paper is also an attempt to Wafer package of size with minimum 6 inch Diameter with
isolate the entire good and bad Semiconductor Dies received thickness 15-20 mils. It is as shown in Fig. 1. This Wafer
from some Semiconductor Manufacturer at one place with package has to be done a Visual Inspection (VI) with
complete package before going to Manufacturing Unit. It not magnifying microscope with a magnification of 60 X – 100 X.
only yields the efficiency of the Product in that Manufacturing It has to be checked whether there is any glassivation or
line but also it saves a lot of manpower given for Failure
passivation or metallization shown in Fig. 2. Also Die has to
Analysis, rework, retesting, etc and also it increases the Product
reliability be inspected constantly whether there is any presence of
Voids Fig. 3 corrosion in Bond Pad Fig. 4 or any Die crack
Index Terms—Resonance, wafer, die, lapping, voids Fig. 5 or any contamination [2],[3] on Die Surfaces. The VI
Reports should be recorded and submitted along with the
wafers.
I. INTRODUCTION
Any small change in the product which may be either due
to process improvement or due to application requirements or
due to material changes had a direct impact on device
reliability. The device reliability depends upon avoiding any
small and minute changes from the original one. For example
any changes in die size which occurred due to scratch, die
track cut, chips out, cracks, voids, corrosion on bond pads, Fig. 1. Semiconductor die in wafer
glassivation, metallization, passivation, leads to decrement of
Product performance.
For an instant, the capacitor of cracked Die [1] becomes
either half for parallel circuited or get doubled for series
circuited. In both the cases, the resonance for the Product
affects and hence the performance degrades. If there are any
voids or corrosion on bond pads, the series inductance
increases which again degrades. Hence for successful
Product launching; the associated items should be understood
about their functionality, performance and also to be Fig. 2. Passivations, glassivations and metallization
prevented to avoid any type of changes in size and shape.

II. BASICS
The Semiconductor Die or chip is the heart of any
electronic products. This small Die contains a lot of
integrated circuits and full of intelligence associated with it.
Fig. 3. Voids in glassivation
The Die may be designed according to a design methodology
that includes the step of concurrently designing circuitry and
a product circuitry in a unified design. This Paper will discuss
complete processes for Die processing and packaging much

Manuscript received on January 30, 2011; revised April 25,2012. This

work is based on the Die and ICs received by different semiconductor
manufacturers. These Dies and ICs should be done proper processed and
packaging before going to production unit.
The authors are with the SRM University, Modinagar, Delhi-NCR
Campus (email: satya.srikant@gmail.com, mahapatra.rp@gmail.com) Fig. 4. Corrosion in bond pads

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 International Journal of Information and Electronics Engineering, Vol. 2, No. 3, May 2012

Fig. 8. Probe impression and scratches on die

Fig. 5. Cracks in die D. Packing the Good Wafers

B. Electrical Testings After the Visual Inspection process, all the Good Wafers [5]
should pack in free contamination Wafer Casing, shown in
The next process for all the Bare Die in Wafer is Electrical Fig. 9.
testing i.e. DC – probe Testing [3], [4]. In this testing, a single
Bare Die is placed on the Probe Card. The automatic tester
shown in Fig. 6 will give the proper signal if it gives desired
signal indication for Bare Die connected via Probe needles [4]
to tester. This test can also be performed directly on wafer
also for each Die.
Fig. 9. Casing with single wafer and multiple wafers

IV. LAPPING AND POLISHING

A. Lapping and Polishing
The procedure for Lapping process shall be compatible
Fig. 6. DC – probe testing set with Semiconductor wafers [5].
a) Wafer must be reduced to 175mm ± 5mm thickness
If the tester does not give any signal or less than the desired b) After lapping process, it should be cleaned by
signal then the Bare Die is inked as shown in Fig. 7 indicating suitable solvent.
as a Bad Die. No signal for a Bare Die clearly indicates that c) Measure and record thickness of Lapping (as per
there must be track cut or corrosion on Die. Also low signal desired specifications only) at 4-5 places for the
indicates that there must be some crack or voids or wafer. The thickness should be constant and it
metallization on Bare Die due to which the Capacitive value always be as per specifications.
either decreases or increases which affects the resonant factor B. Visual Inspection
directly.
A process of Visual Inspection is again there soon after
Lapping / polishing process. The VI with high magnifying
Microscope (60 X – 100 X) is required for VI for any voids
and scratches; VI for damaging to glassivations. It is shown
in Fig. 10 which occurs during Lapping / polishing process.
The yield or efficiency for good Lapped Die should be
Fig. 7. Bad dies inked
calculated and recorded.

Once the process of Bad Dies Inked for the Wafer

completed with Electrical Testing, then the yield or
efficiency for good Die should be calculated. The standard
for Wafer acceptance and rejection criteria should always be
Fig. 10. Voids and scratches after lapping process
followed as testing standard.
C. Mounting the Wafer
C. Visual Inspections
There should be a process of Visual Inspection again, soon
after Electrical Testing process. Under this process, VI with
high magnifying Microscope (60 X – 100 X) is required for
excessive probe impression and scratches. Fig. 8 shows a Die
with excessive probe impression and scratches during
electrical testing. The Die with such impression and scratches
Fig. 11. Glue tapping
must keep in separate Wafer even though functionality wise
is good. The yield or efficiency for good Die in original The next process is to mount the Wafer with Glue Tape
Wafer and also the yield to be calculated for good Die with and Bracket as shown in Fig. 11. It should be always crossed
excessive probe impression which with in separate Wafer. check that there should not be any voids on Glue Tape. A
The VI report for both Good and probe impression Bare Die process of thorough VI to be performed with high microscope
should be recorded in a detailed way. (60X – 100X) to check whether the proper mounting of wafer

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 International Journal of Information and Electronics Engineering, Vol. 2, No. 3, May 2012

has been performed and also to avoid any voids on Glue tapes VI. CONCLUSION
and Brackets. This paper presents a competitive process of testing and
D. Dicing and Cleaning inspection, involved from procurement of wafer to diced
After all the above processes, the most important step is to individual Die. On adopting the above process, the selection
dice the wafer as per the drawing provided from the Design of any semiconductor ICs for any manufacturing the product
Department. The diced wafer is shown in Figure (12). The shows excellent success rate with almost zero failure result.
The integrated circuit T 5557e from ATMEL with above
cleaning process of wafer should be performed after dicing
and then observe the VI for defects if any. process has been experimented for the production of Smart
Card and Smart Card Reader. The integrated circuit is used in
the Die form and is lapped and polished to a thickness of 175
mm.

ACKNOWLEDGMENT
There are far too many people to try to thank them all many
Fig. 12. Diced wafer
people have contributed to the development of this paper. We
owe our deep regards and honor to express our gratitude to Dr.
TABLE I PROCESS FLOW DIAGRAM Manoj Kumar Pandey, Director, SRM-Institute of
Management & Technology, Modinagar and all the faculty
members for providing me invaluable support, guidance, help
and inspiration all through this paper.

REFERENCES
[1] B. Gillette “Inductive Operating Life Stress Metal Breakdown
Mechanism,” Fairchild Semiconductor, Proceeding of 32nd Symposium
for Testing and Failure Analysis, pp. 125–130, 2006.
[2] J. M. Leas, R. W. Koss, J. J. V. Horn, G. F. Walker, C. H. Perry, D. L.
Gardell, S. L. Dingle, and R, Prilik, “Semiconductor wafer test and
burn-in,” 2002.
[3] B. Eldridge, I. Khandros, D. Pedersen, and W. Ralph “Test Assembly
including a Test Die for testing a semiconductor product die,” US
Patent US007557596B2, 2009.
[4] W. Kreiger and D. Wilder “Probe for wafer burn-in test system,” US
1993.
[5] O. k. Kwon, M. Hashimoto, S. Malhi, and Born “Full wafer integrated
circuit testing device” US Patent 5070297, 1991.
[6] T 5557 Mature Manual, Atmel Corporation.
[7] K. Finkenzeller “RFID Handbook"

Satya Sai Srikant M.Tech (Microwave Electronics)

presently working as an Assistant Professor (ECE) at
Modinagar Campus of SRM University; contributing
his enormous research works in the area of RF and
RFID Technology, Simulations, Microstrip Antenna.
He recently awarded ‘IEI Award-Gold medal’ at
53RD Annual Technical Session held on 5TH
February, 2012 at IEI Bhubaneswar, Odisha in the
field of Microwave Technology
V. PROCESS FLOW DIAGRAM
Rajendra Prasad Mahapatra PhD (CSE) presently
The process flow diagram of entire processes from working as Associate Dean at Modinagar Campus of
procurement of wafer to individual diced Die is shown in SRM University; contributing his enormous research
works in the area contributing his enormous research
Table 1. The experiment is performed for the IC named works in the field of Computer Science, Simulations,
T-5557e from ATMEL [6]. Network Security and Artificial Intelligence and RF
Technology.

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