LABORATORY MANUAL

Digital Logic & Computer Organization and

Architecture Lab

SE(SEM-III)
(A.Y. 2024-25)

DEPARTMENT OF COMPUTER
ENGINEERING

Xavier Institute of Engineering

(Affiliated to Mumbai University)
 Institute Vision and Mission
Vision of Institute
To nurture the joy of excellence in a world of high technology.

Mission of Institute
To strive to match Global Standards in Technical Education by Interaction with Industry,
Continuous Staff Training and Development of Quality of Life.

Department Vision and Mission

Vision of Computer Department

To nurture the joy of excellence in the world of Computer Engineering.

Mission of Computer Department

M1: To provide students the knowledge of computer engineering with related technical skills
to solve various computer engineering problems
and to have industry interaction.
M2: To motivate the students to acquire additional soft skills to sharpen their technical and
professional skills that make them employable.
M3: To nurture social and professional ethics in our undergraduates and encourage them to
have lifelong learning.
 Program Specific Objectives (PSO)

The ability to understand, analyze and apply knowledge to address

PSO1
computing problems.

The ability to design and implement software solutions to meet the end
PSO2
users requirements.

Program Educational Objectives (PEOs)

Graduates will have the required knowledge of computer engineering,

PEO1 to design and develop systems that can cater to a multi-disciplinary
environment.

Graduates will be able to apply the art of self-learning to use the

PEO2
modern tools in solving computer engineering problems.

Graduates will be prepared in the field of computer engineering to have

PEO3
lifelong-learning in the global and ethic context.

Graduates will be able to inculcate professional and ethical attitude

PEO4 with good leadership qualities and have commitment to social
responsibilities in their thought process.
 PROGRAMOUTCOMES (POs)

Engineering knowledge: To apply the knowledge of mathematics and engineering

1.
fundamentals along with Computer science and physical sciences for the solution of
complex engineering problems.
Problem analysis: To identify, formulate, and analyze complex engineering
2.
problems to provide suitable solutions by applying knowledge acquired in computer
engineering.
3. Design/development of solutions: To design cost effective software or hardware
solutions to meet the needs of customers.
Conduct investigations of complex problems: To use research-based knowledge
4. and research methods including design of experiments, analysis and interpretation of
data, and synthesis of the information to provide valid conclusions in the field of
computer engineering.
Modern tool usage: To create, select, and apply appropriate techniques, resources,
5.
and modern computer science and engineering tools, including prediction and
modeling to complex engineering activities, with an understanding of the limitations.
The engineer and society: Apply reasoning informed by the contextual knowledge
6.
to assess societal, health, safety, legal, and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.
7. Environment and sustainability: To understand the impact of the professional
engineering solutions to preserve the environment and the concern of sustainability.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member
or leader in diverse teams, and in multidisciplinary settings.
Communication: Communicate effectively on complex engineering activities with
10. the engineering community and with t h e society at large, such as, being able to
comprehend and write effective reports and design documentation, make effective
presentations, and give and receive clear instructions.
Project management and finance: Demonstrate knowledge and understanding of
11. the engineering and management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in multidisciplinary
environments.
Life-long learning: Recognize the need for, and have the preparation and ability to
12.
engage in independent and life-long learning in the broadest context of technological
change.
 Lab Rules
DO’S

• Without prior permission do not enter into the Laboratory.

• While entering into the LAB students should wear their ID cards.
• The students should come with proper uniform.
• Students should come with observation and record note book to the laboratory.
• Students should maintain silence inside the laboratory.
• After completing the laboratory exercise, make sure to shut down the system properly.

DONT’S

• Students bringing the bags inside the laboratory.

• Students using the computers in an improper way.
• Students scribbling on the desk and mishandling the chairs.
• Students using mobile phones inside the laboratory.
• Students making noise inside the laboratory.
COURSE NAME: DIGITAL LOGIC & COMPUTER ORGANIZATION AND ARCHITECTURE
LAB

COURSE CODE: CSL302

H/w Requirements: IC chip, microcontrollers and above
S/w Requirements: Virtual labs

Useful links: http://cse10-iitkgp.virtual-labs.ac.in/

LAB OBJECTIVES:
1To implement operations of the arithmetic unit using algorithms.
2 Design and simulate different digital circuits.
3 To design memory subsystem including cache memory.
4 To demonstrate CPU and ALU design.

LAB OUTCOMES:
Course Name Digital Logic & Computer Organization and Architecture Lab

Course Code CSL302

Faculty Name Beatrice Samuel, Kavita Jain

Class SE SEMESTER 3

CO Number Course Outcome (Students will be able to:)

CSL302.1 Demonstrate the use of basic digital components.

Design the basic building blocks of a computer: ALU,
CSL302.2
registers, CPU and memory
Interpret the importance of digital systems in computer
CSL302.3
architecture
CSL302.4 Implement various algorithms for arithmetic operations.
MAPPING OF LAB OUTCOMES WITH PROGRAM OUTCOMES:

PO PO PO
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PSO1 PSO2
10 11 12
LO1
LO2
LO3
LO4
 DIGITAL LOGIC & COMPUTER ORGANIZATION AND ARCHITECTURE LAB

Exp.
Title of the Experiment BLs LOs PO, PSOs
No.
To verify the truth table of various logic PO1, PO2, PO3, PO8, PO9,
1. BL3 LO1
gates. PO10, PSO1, PSO2
To implement half adder using basic digital PO1, PO2, PO8, PO9, PO10
2. BL3 LO1
components. PSO1, PSO2
To implement full adder using basic digital PO1, PO2, PO8, PO9, PO10
3. BL3 LO1
components. PSO1, PSO2
To implement binary to gray code converter PO1, PO2, PO8, PO9, PO10,
4. BL3 LO1
using basic digital components. PSO1, PSO2
To simulate MUX & DEMUX using basic LO1, PO1, PO2, PO3, PO9, PO10
5. BL3
gates LO2 PSO1, PSO2
PO1, PO2, PO3, PO9, PO10
6. To simulate Ripple carry adder. BL3 LO1
PSO1, PSO2
LO2, PO1, PO2, PO8, PO9, PO10
7. To simulate ALU design. BL3
LO4 PSO1, PSO2
PO1, PO2, PO3, PO9, PO10
8. To simulate CPU design. BL3 LO2
PSO1, PSO2
LO2 PO1, PO2, PO3, PO9, PO10
9. To simulate memory design. BL3
PSO1, PSO2
To simulate Flip-flop and verify their truth LO2 PO1, PO2, PO3, PO9, PO10
10. BL3
table. PSO1, PSO2
PO1, PO2, PO9, PO10 PSO1,
11. To implement Booth’s algorithm. BL3 LO4
PSO2
PO1, PO2, PO9, PO10,
12. To implement restoring division algorithm. BL3 LO4
PSO1, PSO2

Advanced Experiments:
1. Examining behaviour of Wallace tree adder for the working module.
2. Examining behaviour of carry lookahead adder for the working module.

Design Experiments:
1. Design a Direct Mapped Cache to assess its performance and cache hit/miss behaviour.
2. Design a CPU to evaluate its performance by analyzing processing speed, efficiency, and resource
utilization.
Open ended Experiments:
1. Implement a Combinational Multiplier.
2. Implement a Ripple Carry Adder.
3. Implement Registers and Counters.
 EXPERIMENT 1

AIM: To verify the truth table of various logic gates.

THEORY:

Logic gates are the basic building blocks of any digital system. Logic gates are electronic circuits having one
or more than one input and only one output. The relationship between the input and the output is based on a
certain logic. Based on this, logic gates are named as

1. AND gate
2. OR gate
3. NOT gate
4. NAND gate
5. NOR gate
6. Ex-OR gate

1) AND gate

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot (.) is
used to show the AND operation i.e. A.B or can be written as AB

Y= A.B

Logic Symbol of AND Gate Truth Table of AND Gate

2) OR gate

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high. A plus
(+) is used to show the OR operation.

Y= A+B

Logic Symbol of OR Gate Truth Table of OR Gate

3) NOT gate

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also
known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is also shown as
A' or A with a bar over the top, as shown at the outputs.

Y= A'

Logic Symbol of NOT Gate Truth Table of NOT Gate

4) NAND gate

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all NAND
gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The
small circle represents inversion.

Y= AB

Logic Symbol of NAND Gate Truth Table of NAND Gate

5) NOR gate

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates
are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output. The small
circle represents inversion.

Y= A+B

Logic Symbol of NOR gate Truth Table of NOR gate

6) Ex-OR gate

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both of its two inputs are
high. An encircled plus sign (⊕) is used to show the Ex-OR operation.

Y= A⊕B

Logic Symbol of Ex-OR gate Truth Table of Ex-OR gate

PROCEDURE:
1. Make the Vcc and Ground connections referring the pin configuration of IC.
2. Make connections for inputs through the switches provided on kit.
3. Connect a LED on output pin.
4. For all possible combinations of inputs verify the outputs using the LED.

CONCLUSION: Hence we have successfully built and verified the truth table of various logic gates.
LO achieved: LO1
PO achieved: PO1, PO2, PO3, PO8, PO9, PO10
PSO achieved: PSO1, PSO2
 EXPERIMENT 2

AIM: To implement half adder using basic components.

THEORY:

There are two inputs and two outputs in a Half Adder. Inputs are named as A and B, and the outputs are
named as Sum (S) and Carry (C). The Sum is X-OR of the input A and B. Carry is AND of the input A and B.
With the help of half adder, one can design a circuit that is capable of performing simple addition with the
help of logic gates. Let us first take a look at the addition of single bits.

0+0=0
0+1=1
1+0=1
1 + 1 = 10

These are the least possible single bit combinations. But the result for 1 + 1 =10. This problem can be solved
with the help of an EX – OR gate. The sum results can be re-written as a 2-bit output. Thus, the above
combination can be written as

0 + 0 = 00
0 + 1 = 01
1 + 0 = 01
1 + 1 = 10

Here the output “1” of “10” becomes the carry-out. SUM is the normal output and the CARRY is the carry-out.
From the truth table of the half adder we can see that the SUM (S) output is the result of the Exclusive-OR gate
and the Carry-out (Cout) is the result of the AND gate. Then the Boolean expression for a half adder is as
follows.

For the SUM bit: SUM = A XOR B = A ⊕ B

For the CARRY bit: CARRY = A AND B = A.B

The main disadvantage of this circuit is that it can only add two inputs and if there is any carry it is neglected.
Thus, the process is incomplete. To overcome this difficulty Full Adder is designed.

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PROCEDURE:
1. Connect the circuit of half adder as shown in figure.

2. Make connections for inputs through the switches provided on kit.

3. Connect a LED on output pin.
4. For all possible combinations of inputs verify the outputs.

RESULT:
Truth Table for Half Adder:

CONCLUSION: Half adder have been implemented successfully using basic components.

LO achieved: LO1
PO achieved: PO1, PO2, PO8, PO9, PO10
PSO achieved: PSO1, PSO2

12
 EXPERIMENT 3

AIM: To implement full adder using basic components.

THEORY:
Full Adder is the adder that adds three inputs and produces two outputs. The first two inputs are A and B and
the third input is an input carry as C-IN. The output carry is designated as C-OUT and the normal output is
designated as S which is SUM. The C-OUT is also known as the majority 1’s detector, whose output goes high
when more than one input is high. A full adder logic is designed in such a manner that can take eight inputs
together to create a byte-wide adder and cascade the carry bit from one adder to another. we use a full adder
because when a carry-in bit is available, another 1-bit adder must be used since a 1-bit half-adder does not take
a carry-in bit. A 1-bit full adder adds three operands and generates 2-bit results.

For the SUM (S) bit: SUM = (A XOR B) XOR Cin = (A ⊕ B) ⊕Cin

For the CARRY-OUT (Cout) bit: CARRY-OUT = A AND B OR Cin(A XOR B) = A.B + Cin(A ⊕ B)

PROCEDURE:
1. Connect the circuit of Full adder as shown in figure.

2. Make connections for inputs through the switches provided on kit.

3. Connect a LED on output pin.
4. For all possible combinations of inputs verify the outputs.

13
RESULT:

Truth Table for Full Adder:

CONCLUSION: Full adder have been implemented successfully using basic components.

LO achieved: LO1
PO achieved: PO1, PO2, PO8, PO9, PO10
PSO achieved: PSO1, PSO2

14
 EXPERIMENT 4

AIM: To implement binary to gray code converter using basic digital components.

THEORY:

In the coding, when numbers, letters or words are represented by a specific group of symbols, it is said
that the number, letter or word is being encoded. The group of symbols is called as a code. The digital data is
represented, stored and transmitted as group of binary bits. This group is also called as binary code. The binary
code is represented by the number as well as alphanumeric letter.

The availability of large variety of codes for the same discrete elements of information results
in the use of different codes by different systems. A conversion circuit must be inserted between the
two systems if each uses different codes for same information. Thus, code converter is a circuit that
makes the two systems compatible even though each uses different binary code.

The Binary to Gray code converter is a logical circuit that is used to convert the binary code
into its equivalent Gray code.

a) Binary To Gray Code Converter using EXOR Gate:

b) Gray Code To Binary Converter using EXOR Gate:

PROCEDURE:

15
 1. Connect VCC and ground pins of IC to the power supply.
2. Connect the circuit on bread board as per the design.
3. Connect LEDs at output pins and verify the truth table.

RESULT:

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

CONCLUSION: Binary to Gray code converter was implemented using basic digital components.

LO achieved: LO1
PO achieved: PO1, PO2, PO8, PO9, PO10
PSO achieved: PSO1, PSO2

EXPERIMENT NO.: 5

16
AIM: To simulate MUX & DEMUX using basic gates.

THEORY:

The function of a multiplexer is to select the input of any ‘n’ input lines and feed that to one output line. The
function of a de-multiplexer is to inverse the function of the multiplexer and the shortcut forms of the
multiplexer. The de-multiplexers are mux and demux. Some multiplexers perform both multiplexing and de-
multiplexing operations.

1) Multiplexer
Multiplexer is a device that has multiple inputs and a single line output. The select lines determine which input
is connected to the output, and also to increase the amount of data that can be sent over a network within certain
time. It is also called a data selector.
Multiplexers are classified into four types:
a) 2-1 multiplexer (1 select line)
b) 4-1 multiplexer (2 select lines)
c) 8-1 multiplexer(3 select lines)
d) 16-1 multiplexer (4 select lines)
1.1) 4x1 Multiplexer
4x1 Multiplexer has four data inputs D0, D1, D2 & D3, two selection lines S0 & S1 and one output Y. The
block diagram of 4x1 Multiplexer is shown in the following figure.One of these 4 inputs will be connected to
the output based on the combination of inputs present at these two selection lines. Truth table of 4x1
Multiplexer is shown below.

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2) De-multiplexer
De-multiplexer is also a device with one input and multiple output lines. It is used to send a signal to one of the
many devices. The main difference between a multiplexer and a de-multiplexer is that a multiplexer takes two
or more signals and encodes them on a wire, whereas a de-multiplexer does reverse to what the multiplexer
does.
De-multiplexer are classified into four types:
a)1-2 demultiplexer (1 select line)
b)1-4 demultiplexer (2 select lines)
c)1-8 demultiplexer (3 select lines)
d)1-16 demultiplexer (4 select lines)

2.2) 1x4 De-multiplexer

1x4 De-Multiplexer has one input Data(D), two selection lines, S0 & S1 and four outputs Y0, Y1, Y2 & Y3.
The block diagram of 1x4 De-Multiplexer is shown in the following figure.

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PROCEDURE:
1) 4x1 Multiplexer

Step-1) Connect the supply(+5V) to the circuit.

Step-2) First press "ADD" button to add basic state of your output in the given table.
Step-3) Press the switches "S0" and "S1"to select the desired input line.
Step-4) Press "D0"/"D1"/"D2"/"D3" any one button to add your inputs.
Step-5) Press "ADD" button to add your inputs and outputs in the given table.
Step-6) Repeat step 3, 4 and step 5 for next state of inputs and their corresponding outputs.
Step-7) Press the "PRINT" button after completing your simulation to get your results.

2) 1x4 De-Multiplexer

Step-1) Connect the supply(+5V) to the circuit.

Step-2) First press "ADD" button to add basic state of your output in the given table.
Step-3) Press the switch Data(D) for Input.
Step-4) Press switches "S0" and "S1" to select the desired input line.
Step-5) Press "ADD" button to add your inputs and outputs in the given table.
Step-6) Repeat step 4 and step 5 for next state of inputs and their corresponding outputs.
Step-7) Press the "PRINT" button after completing your simulation to get your results.

CONCLUSION: In this experiment, the simulation of both a 4x1 Multiplexer (MUX) and a 1x4 De-
multiplexer (DEMUX) using basic gates was successfully demonstrated. The functionality of these digital
circuits highlights the essential roles they play in data transmission and distribution.

LO achieved: LO1, LO2

PO achieved: PO1, PO2, PO3, PO9, PO10
PSO achieved: PSO1, PSO2

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 EXPERIMENT NO.: 6

AIM: To simulate ripple carry adder.

THEORY:

Design of Ripple Carry Adders :

Arithmetic operations like addition, subtraction, multiplication, division are basic operations to be implemented
in digital computers using basic gates likr AND, OR, NOR, NAND etc. Among all the arithmetic operations if
we can implement addition then it is easy to perform multiplication (by repeated addition), subtraction (by
negating one operand) or division (repeated subtraction).
Half Adders can be used to add two one bit binary numbers. It is also possible to create a logical circuit using
multiple full adders to add N-bit binary numbers.Each full adder inputs a Cin, which is the Cout of the previous
adder. This kind of adder is a Ripple Carry Adder, since each carry bit "ripples" to the next full adder. The
first (and only the first) full adder may be replaced by a half adder.The block diagram of 4-bit Ripple Carry
Adder is shown here below -

The layout of ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is
relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder.
The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three
levels of logic. In a 32-bit [ripple carry] adder, there are 32 full adders, so the critical path (worst case) delay is
31 * 2(for carry propagation) + 3(for sum) = 65 gate delays.

Design Issues :
The corresponding boolean expressions are given here to construct a ripple carry adder. In the half adder circuit
the sum and carry bits are defined as
Sum = A ⊕ B

Carry = AB

In the full adder circuit the Sum and Carry output is defined by inputs A, B and Carry in as
Sum = ABC + ABC + ABC + ABC

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 Carry = ABC + ABC + ABC + ABC

Having these we could design the circuit. But, we first check to see if there are any logically equivalent
statements that would lead to a more structured equivalent circuit.
With a little algebraic manipulation, one can see that
Sum = ABC + ABC + ABC + ABC

= (AB + AB) C + (AB + AB) C

= (A ⊕ B) C + (A ⊕ B) C

=A⊕B⊕C

Carry = ABC + ABC + ABC + ABC

= AB + (AB + AB) C

= AB + (A ⊕ B) C

CONCLUSION: In this experiment, we successfully simulated a Ripple Carry Adder, a fundamental building block
for performing arithmetic operations in digital circuits.

LO achieved: LO2
PO achieved: PO1, PO2, PO3, PO9, PO10
PSO achieved: PSO1, PSO2

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 EXPERIMENT NO. 7

AIM: To simulate ALU design.

THEORY:

Arithmetic Logic Units: The 4 bit Arithmetic Logic Units perform 16 different Arithmetic operation and 16
different logical operation.This Arithmetic Logic Units controlled by 4 select inputs and one mode control
input.

Figure 1:Pin configuration of 74181(4 bit Arithmetic Logic Unit)

Figure 2:Pin description of 74181(4 bit Arithmetic Logic Unit)

22
Functionality: When the model control input(M) is high, all internal carries are disabled and device performs
logical operation on individual bits as listed. When Mode control input is low the carries are enabled and the
device performs arithmetic operation on two four bit words. The Device includes full internal lookahead and
provides for either ripple carry between devices using C n+4 output, for carry lookahead between packages
using signals P (Carry Propagate) and C (Carry Generate).P and G are not affected by carry in. When speed
requirement are not so much required, it can be used in a simple ripple carry mode by connecting the carry
output signal (Cn+4 )signal to the carry input C n of the next unit. For high speed operation the device is used
in the conjunction with the 182 carry lookahead circuit. One carry lookahead package is required for each
group of four 181' devices. Carry lookahead can be provided in various angle and provide at various levels
and can offer high speed capability over long words length. The A=B output from the device goes High, when
all four output from the device is high and can be used to indicate logical equivalence over 4bit when the unit
is in subtract mode. The A=B output is open collector and can be wired AND with other A=B outputs to give
a comparison for more than 4bits.The A=B signal can be used with C n+4 signal to indicate A< B and A >B
The function table list the arithmetic operation that are performed without a carry in. An incoming carry adds
a one to each operation. Thus the select code LHHS generates A minus B minus 1 (2s compliment notation)
without a carry in and and generates A minus B when a carry is applied. Because subtraction is actually
performed by complimentary addition (1s compliment),a carry out means borrow; thus a carry is generated
when there is no under flow and no carry is generated when there is underflow. As indicated this device can
be used with either active low inputs producing active low outputs or with active high inputs producing active
active high outputs.For either cause the table lists the operations that are performed to operands labelled inside
the logic symbol.

Figure 3: Functional Table of Arithmetic Logic Unit

23
 Figure 4: Logic Diagram of Arithmetic Logic Unit

PROCEDURE:
Part 1:
1. first apply high voltage to Vcc. Then apply high voltage to M(mode control input) and low voltage to
all the 4 select inputs. Logical operation will be performed. The output will be inverted A.

24
2. Next, apply high voltage to S0 and apply low voltage to all other select inputs. The output will be A +
B.

3. Now apply high voltage to S1 and low voltage to all other select inputs.The output will be AB.

4. Next, apply high voltage to S0 and S1 and low voltage to other select inputs.The output will be logical
1

25
5. Apply high voltage to S2 and apply low voltage to all other select inputs.The output will be AB.
6. Apply all the combinations to all the select inputs and check the logical output.

26
7. Apply low voltage to mode control input and high voltage to Cin.Now the operation mode will be
arithmetic mode.
8. Next apply low voltages to all the select inputs.The output will be A + 1.

9. Next, apply high voltage to S0 and low voltage to all other select inputs.The output will be A + B + 1.

10. Apply high voltage to S1 and apply low voltages to all other select inputs. The output will be A + B.

27
11. Now apply high voltage to S0 and S1 and low volage to all other select inputs. The output will be -1 +
1.It means output will be zero.

12. Next, apply high voltage to S2 and low voltage to all other select inputs.The output will be A plus AB.

28
CONCLUSION: Hence, 1-bit ALU using basic digital components was implemented successfully.

LO achieved: LO2, LO4

PO achieved: PO1, PO2, PO3, PO9, PO10
PSO achieved: PSO1, PSO2

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 EXPERIMENT NO.: 8

AIM: To simulate CPU design.

THEORY:

CPU Design:
At the top level a computer consists of a CPU (central processing unit), memory, I/O components, with one or
more modules of each type. These modules are interconnected in a specific manner to achieve the basic
functionality of a computer i.e. executing programs. At the top level a computer system can be described as
followes:
• describing the external behavior of each component i.e the data and the control signals that ir exchanges
with other components
• describing the interconnection structure and the controls required
We are considering the Von Neumann architecture. Some of the basic features of this architecture are as follows:
• data and instructions are stored in a single read-write memory
• the contents of the memory are addressable by location
• execution occurs in a sequential manner (unless explicitly specified) from one instruction to the next
Top level components and interactions among them:
• CPU exchanges data with memory. For this CPU uses two internal resisters. Following is a block
diagram of a basic computer system:

o Memory address register (MAR) which specifies the address for the next read or write
o Memory buffer register (MBR) which contains the data to be written into memory or receives

30
 the data read from memory
o I/O buffer (I/O BR) register is used for the exchange of data between an I/O module and the CPU
• A memory module consists of a set of a locations defined by sequentially numbered addresses. Each
location contains a binary number that cam be interpreted as either an instruction or data.
• An I/O module transfers data from external devices to CPU and memory and vise versa
• The basic function of a computer is to execute a program which consists of a set of instructions stored
in the memory. Processing required for a single instruction is called an instruction cycle which consists
instruction fetch and instruction execute. A register called program counter (PC) holds the address of
the next instruction. Unless told otherwise the processor always increments PC after each instruction
fetch so that the next instruction is fetched in sequence. The fetched instruction is fetched into a register
called instruction register (IR).
The basic instruction cycle is shown in the following figure:

• After fetching an instruction, processor execute the instruction by doing some processing on the data
which may involve arithmetic and logic unit (ALU), specified by the instruction, then processor writes
back the result (if any) to the memory.
This experiment provides a single instruction CPU with built-in controller. A working memory has been
provided to check the working principle of the CPU. The single instruction which this CPU supports is SBN
(subtract and branch if negative). The format of this instruction is:
• SBN a,b,c Mem[a] = Mem[a] - Mem[b] if(Mem[a] < 0) goto c
• a, b, c are 4 bit addresses
• Mem[a] denotes the contents of memory address a
In this experiment, no I/O module has been included for the purpose of simplicity. The working memory should
contain the programm and data in binary format. The CPU executes the programm. For halting, it uses self loop,
no other halt instruction is provided.

PROCEDURE:

1. Start the simulator as directed.This simulator supports 5-valued logic.

2. To perform the experiment on the given modules, we need the CPU, the working memory with a program and
data loaded, a clock input, Bit switch(to give input,which will toggle its value with a double click), Bit
displays(for seeing output), wires.
3. Load memory: click on the load memory button in the left pane. you can either load the memory by filling the

31
 form or you can directly load the program form a text file. The memory provides 4-bit address space and 12 bit
data word, thus providing 16 memory address starting from 0000 to 1111. For loading from file, the file should
contain only binary values, it must contain 16 lines, each line containing the content to be stored in the
corresponding memory address. For example, content of first line will be loaded to the 0000 address of the
memory, similarly, the second line will correspond to the 0001 address and so on, finally the content of last line
will be fed to the 1111 address. The progrm should use self loop for halting, for example, the instruction stored
at address 1010 will cause self loop execution, if it content of a has -1 in binary format (in 2's complement), the
content of b has 0 and c is 1010, then once the execution reaches to this 1010 address, it will finally point to
itself.
4. Instantiating the memory: after loading the memory, click on the memory component from the computer design
drawer in the palette of the simulator then click on the position of the design editor where you want to put the
component(no drag and drop, simple click will serve the purpose).
5. The pin configuration of the component is shown whenever the mouse is hovered on any canned component of
the palette or pressing the show pin configuration button on the toolbar will show it constantly in the left pane.
Pin numbering starts from 1 and from the bottom left corner(indicating with the circle) and increases
anticlockwise.
6. Pin configuration of the memory module:
o Input pins (upper terminals): memory enable : 30, R/W' : 29, address : 25-28, data : 13-24 (13 is LSB)
o Output pins(lower terminals): data output : 1-12 (1 is MSB)
7. Instantiate the CPU from the computer design drawer in the palette of the simulator then click on the position of
the design editor where you want to put the component.
8. Pin configuration of the CPU:
o Input pins (upper terminals): data input : 20-31 (20 is MSB) ,clock input : 19
o Output pins(lower terminals): memory enable : 1, R/W' : 2, address : 3-6( 3 is MSB), data output : 7-18
(7 is MSB)
9. To connect any two components select the Connection menu of Palette, and then click on the Source terminal
and click on the target terminal. According to the following diagram connect all the components. Connect the
memory outputs to the input terminals of the CPU, specified datapath outputs to the inputs of the controller, the
clock input, Bit switches with the inputs and Bit displays component with the outputs (from Display and Input
drawer of the pallet,if it is not seen scroll down in the drawer). After the connection is over click the selection
tool in the pallete.
10. Start clock and observe the behavior of the CPU.See the content of memory by clicking show memory button in
the left pane. Observe how the program is executing sequentially and modify the data content as per the
program.

32
CONCLUSION: In this experiment, we simulated a simple CPU design based on the Von Neumann
architecture. We observed how the CPU interacts with memory, fetches instructions, and executes them
sequentially.

LO achieved: LO2
PO achieved: PO1, PO2, PO3, PO9, PO10
PSO achieved: PSO1, PSO2

33
 EXPERIMENT NO.: 9

AIM: To simulate memory design.

THEORY:

Design of Memory :
A memory unit is a collection of storage cells together with associated circuits needed to transform insformation
in and out of the device. Memory cells which can be accessed for information transfer to or from any desired
random location is called random access memory(RAM). The block diagram of a memory unit-

Internal Construction: The internal construction of a random-access memory of m words with n bits per word
consists of m*n binary storage cells and associated decoding circuits for selecting individual words. The binary
cell is the basic building block of a memory unit.
RAM Design:

Design of a RAM cell :

The binary cell has three inputs and one output. The select input enables the cell for reading or writing and the
reda/write input determines the cell operation when it is selected. A 1 in the read/write input provides the read
operation by forming a path from the flip-flop to the output terminal. A 0 in the read/write input provides the
write operation by forming a path from the input terminal to the flip-flop. the logic diagram is-

34
Design of a 4X4 RAM :
The logical construction of a small RAM 4X3 is shown below. It consists of 4 words of 3 bits each and has a
total of 12 binary cells. Each block labeled BC represents the binary cell with its 3 inputs and 1 output. The
block diagram of a binary cell-

A memory with 4 words needs two address lines. The two address inputs go through a 2*4 decoder to select
one of the four words. The decoder is enabled with the memory enable input. When the memory enable is 0, all
outputs of the decoder are 0 and none of the memory words are selected. With the memory enable at 1, one of
the four words is selected, dictated by the value in the two address lines. Once a word has been selected, the
read/write input determines the operation. the logic diagram is-

35
Design Issues :
A basic RAM cell has been provided here as a component which can be used to design larger memory units.
An IC memory consisting of 4 words each having 3 bits has been aslo provided.

PROCEDURE:
Design of 4X3 RAM memory:
1. Start the simulator as directed.This simulator supports 5-valued logic.
2. To design the circuit we need 12 binary RAM cell, 9 OR gate, 7 bit switch (to give input,which will
toggle its value with a double click), 3 bit display (to see the output), wires.
3. The pin configuration of a component is shown whenever the mouse is hovered on any canned

36
 component of the palette or press the 'show pinconfig' button. Pin numbering starts from 1 and from
the bottom left corner (indicated with the circle) and increases anticlockwise.
4. For a binary RAM cell input is in pin-5, output is in pin-4 and select is pin-8, Read/Write is in pin-6,
for read operation give 1 input to Read/Write pin. For write operation give 0 input to Read/Write pin.
5. For a 'decoder with enable', input A is in pin-6, B is in pin-5, output D0 is in pin-4, D1 is in pin-3, D2
is in pin-2, D3 is in pin-1 and Enable is in pin-8
6. Click on the 'decoder with enable' component (in the Other Components drawer in the pallet) and then
click on the position of the editor window where you want to add the component (no drag and drop,
simple click will serve the purpose), likewise add 12 binary RAM cell (from the Other Components
drawer in the pallet), 9 OR gates (from Logic Gates drawer in the pallete), 7 bit switches (which will
toggle its value with a double click), 3 bit displays (from Display and Input drawer of the pallet,if it is
not seen scroll down in the drawer)
7. To connect any two components select the Connection menu of Palette, and then click on the Source
terminal and click on the target terminal. According to the circuit diagram connect all the components,
connect 2 bit switches to the inputs of the 'decoder with enable' (which will act as address input), 1 bit
switch to the enable pin of the 'decoder with enable' (which will act as memory enable input), connect
a bit switch to the Read/Write(R/W') line, 3 bit switches to the data inputs line, 3 bit displays to the
data output line and OR gates according to the diagram shown in the circuit diagram. after athe
connection is over click the selection tool in the pallete.
8. To see the circuit working, Do some read or write operation by properly setting the R/W', memory
enable then give input and check the output. suppose you give, R/W'=1, memory enable=1, address
input=01, data input=101, then it will be a read operation and you will not see 101 as output, it will
store 101 in the word-1. now again set, R/W'=0, memory enable=1, address input=01, then it will be a
write operation and you will see 101 as the content of word-1 on the output display.

Components:
For Designing a RAM Cell
To build a RAM Cell, we need:
1. AND Gate(2 input)-6
2. NOT Gate-2
3. RS Flip Flop-1
For Designing a 4X3 RAM
To build a 4X3 RAM, we need:
1. OR Gate(2 input)-11
2. RAM Cell-12
3. 2X4 Decoder with Enable-1

37
Circuit diagram of 4X3 RAM memory:

CONCLUSION:
LO achieved: LO2
PO achieved: PO1, PO2, PO3, PO9, PO10
PSO achieved: PSO1, PSO2

38
 EXPERIMENT NO.: 10

AIM: To simulate Flip-Flop and verify there truth table.

THEORY:

A flip flop is an electronic circuit with two stable states that can be used to store binary data. The stored data can be
changed by applying varying inputs. Flip-flops and latches are fundamental building blocks of digital electronics
systems used in computers, communications, and many other types of systems.

1. R-S flip flop

2. D flip flop
3. J-K flip flop
4. T flip flop
5.

1) RS flip flop

The basic NAND gate RS flip flop circuit is used to store the data and thus provides feedback from both of its
outputs again back to its inputs. The RS flip flop actually has three inputs, SET, RESET and clock pulse.

Figure-1:R-S flip flop circuit diagram

39
 Figure-2:Characteristics table of R-S flip flop

2) D flip flop

A D flip flop has a single data input. This type of flip flop is obtained from the SR flip flop by connecting the
R input through an inverter, and the S input is connected directly to data input. The modified clocked SR flip-
flop is known as D-flip-flop and is shown below. From the truth table of SR flip-flop we see that the output of
the SR flip-flop is in unpredictable state when the inputs are same and high. In many practical applications,
these input conditions are not required. These input conditions can be avoided by making them complement of
each other.

Figure-3:Circuit diagram of D flip flop

40
 Figure-4:Characteristics table of D flip flop

3) J-K flip flop

In a RS flip-flop the input R=S=1 leads to an indeterminate output. The RS flip-flop circuit may be re-joined if
both inputs are 1 than also the outputs are complement of each other as shown in characteristics table below.

Figure-5:Circuit diagram of J-K flip flop

41
 Figure-6:Characteristics table of J-K flip flop

4) T flip flop

T flip-flop is known as toggle flip-flop. The T flip-flop is modification of the J-K flip-flop. Both the JK inputs
of the JK flip – flop are held at logic 1 and the clock signal continuous to change as shown in table below.

Figure-7:Circuit diagram of T flip flop

42
 Figure-8:Characteristics table of T flip flop

PROCEDURE:
1) SR flip flop

Step-1) Connect the supply(+5V) to the circuit.

Step-2) First press "ADD" button to add basic state of your output in the given table.
Step-3) Press the switches to select the required inputs "S" and "R" and apply the clock pulse.
Step-4) Press "ADD" button to add your inputs and outputs in the given table and their corresponding graph.
Step-5) Repeat steps 3&4 for next state of inputs and their corresponding outputs.
Step-6) Press the "Print" button after completing your simulation to get your results.

2) D flip flop

Step-1) Connect the supply(+5V) to the circuit.

Step-2) First press "ADD" button to add basic state of your output in the given table.
Step-3) Press the switches to select the required inputs "D" and "Clock" .
Step-4) Press "ADD" button to add your inputs and outputs in the given table and their corresponding graph.
Step-5) Repeat step 3 & step 4 for next state of inputs and their corresponding outputs.
Step-6) Press the "Print" button after completing your simulation to get your results.
3) J-K flip flop

Step-1) Connect the supply(+5V) to the circuit.

Step-2) First press "ADD" button to add basic state of your output in the given table.
Step-3) Press the switches to select the required inputs "J" and "K" and apply the clock pulse.

43
Step-4) Press "ADD" button to add your inputs and outputs in the given table and their corresponding graph.
Step-5) Repeat step 3 & step 4 for next state of inputs and their corresponding outputs.
Step-6) Press the "Print" button after completing your simulation to get your results.

4) T flip flop

Step-1) Connect the supply(+5V) to the circuit.

Step-2) First press "ADD" button to add basic state of your output in the given table.
Step-3) Press the switches to select the required inputs "T" and apply the clock pulse.
Step-4) Press "ADD" button to add your inputs and outputs in the given table and their corresponding graph.
Step-6) Press the "Print" button after completing your simulation to get your results.

CONCLUSION: Hence, we verified the truth table of flip flop.

LO achieved: LO2
PO achieved: PO1, PO2, PO3, PO9, PO10
PSO achieved: PSO1, PSO2

44
 EXPERIMENT NO.: 11

AIM: To implement Booth’s algorithm.

THEORY:

Booth's multiplication algorithm is a multiplication algorithm that multiplies two signed binary numbers in
notation. The Booth's algorithm serves two purposes: Fast multiplication (when there are consecutive 0's or 1's
in the multiplier). And Signed multiplication. Booth's algorithm is a powerful direct algorithm to perform
signed-number multiplication. The algorithm is based on the fact that any binary number can be represented by
the sum and difference of other binary numbers.
Booth's multiplication algorithm is a multiplication algorithm that multiplies two signed binary numbers in
two's complement notation. Booth's algorithm examines adjacent pairs of bits of the N-bit multiplier Y in signed
two's complement representation, including an implicit bit below the least significant bit, y-1 = 0. For each bit
yi, for I running from 0 to N-1, the bits yi and yi-1 are considered. Where these two bits are equal, the product
accumulator P is left unchanged. Where yi = 0 and yi-1 = 1, the multiplicand times 2i is added toP; and where
yi = 1 and yi-1 = 0, the multiplicand times 2i is subtracted from P. The final value of P is the signed product.
The representation of the multiplicand and product are not specified; typically, these are both also in two's
complement representation, like the multiplier, but any number system that supports addition and subtraction
will work as well. As stated here, the order of the steps is not determined. Typically, it proceeds from LSB to
MSB, starting at i = 0; the multiplication by 2 i is then typically replaced by incremental shifting of the P
accumulator to the right between steps; low bits can be shifted out, and subsequent additions and subtractions
can then be done just on the highest N bits of P. There are many variations and optimizations on these details.
The algorithm is often described as converting strings of 1's in the multiplier to a high-order +1 and a low-order
–1 at the ends of the string. When a string runs through the MSB, there is no high- order +1, and the net effect
is interpretation as a negative of the appropriate value.

FLOWCHART:

45
PROCEDURE / CODE:

#include <stdio.h>
#include <math.h>

int a = 0,b = 0, c = 0, a1 = 0, b1 = 0, com[8] = { 1, 0, 0, 0, 0,0,0,0};

int anum[8] = {0}, anumcp[8] = {0}, bnum[8] = {0};
int acomp[8] = {0}, bcomp[8] = {0}, pro[8] = {0}, res[8] = {0};

void binary(){
a1 = fabs(a);
b1 = fabs(b);
int r, r2, i, temp;
for (i = 0; i < 8; i++){
r = a1 % 2;
a1 = a1 / 2;
r2 = b1 % 2;
b1 = b1 / 2;
anum[i] = r;
anumcp[i] = r;
bnum[i] = r2;
if(r2 == 0){
bcomp[i] = 1;
}
if(r == 0){
acomp[i] =1;
}
}
//part for two's complementing
c = 0;
for ( i = 0; i < 8; i++){
res[i] = com[i]+ bcomp[i] + c;
if(res[i] >= 2){
c = 1;
}
else
c = 0;
res[i] = res[i] % 2;
}
for (i = 7; i >= 0; i--){
bcomp[i] = res[i];
}

46
 //in case of negative inputs
if (a < 0){
c = 0;
for (i = 7; i >= 0; i--){
res[i] = 0;
}
for ( i = 0; i < 8; i++){
res[i] = com[i] + acomp[i] + c;
if (res[i] >= 2){
c = 1;
}
else
c = 0;
res[i] = res[i]%2;
}
for (i = 7; i >= 0; i--){
anum[i] = res[i];
anumcp[i] = res[i];
}
}
if(b < 0){
for (i = 0; i < 8; i++){
temp = bnum[i];
bnum[i] = bcomp[i];
bcomp[i] = temp;
}
}
}
void add(int num[]){
int i;
c = 0;
for ( i = 0; i < 8; i++){
res[i] = pro[i] + num[i] + c;
if (res[i] >= 2){
c = 1;
}
else{
c = 0;
}
res[i] = res[i]%2;
}
for (i = 7; i >= 0; i--){

47
 pro[i] = res[i];
printf("%d",pro[i]);
}
printf(":");
for (i = 7; i >= 0; i--){
printf("%d", anumcp[i]);
}
}
void arshift(){//for arithmetic shift right
int temp = pro[7], temp2 = pro[0], i;
for (i = 1; i < 8 ; i++){//shift the MSB of product
pro[i-1] = pro[i];
}
pro[7] = temp;
for (i = 1; i < 8 ; i++){//shift the LSB of product
anumcp[i-1] = anumcp[i];
}
anumcp[7] = temp2;
//display together
for (i = 7; i >= 0; i--){
printf("%d",pro[i]);
}
printf(":");
for(i = 7; i >= 0; i--){
printf("%d", anumcp[i]);
}
}

void main(){
int i, q = 0;
printf("\t\t\tBOOTH'S MULTIPLICATION ALGORITHM");
printf("\nEnter two numbers to multiply: (less than or equal to 125)");
//simulating for two numbers till 125
do{
printf("\nEnter A: ");
scanf("%d",&a);
printf("Enter B: ");
scanf("%d", &b);
}while(a >=126 || b >=126);
printf("\nExpected product = %d", a * b);
binary();
printf("\n\nBinary Equivalents: ");

48
 printf("\nA = ");
for (i = 7; i >= 0; i--){
printf("%d", anum[i]);
}
printf("\tB = ");
for (i = 7; i >= 0; i--){
printf("%d", bnum[i]);
}
printf("\tB'+ 1 = ");
for (i = 8; i >= 0; i--){
printf("%d", bcomp[i]);
}
printf("\tCount = 8");
printf("\n|------------------------------|------------------------------|------------|");
for (i = 0;i < 8; i++){
if (anum[i] == q){//just shift for 00 or 11
printf("\n|\t\t\t\t|AR-SHIFT: ");
}
else if(anum[i] == 1 && q == 0){//subtract and shift for 10
printf("\n| SUB B: ");
add(bcomp);//add two's complement to implement subtraction
printf("\t| AR-SHIFT: ");
}
else{//add ans shift for 01
printf("\n| ADD B: ");
add(bnum);
printf("\t| AR-SHIFT: ");
}
arshift();
q = anum[i];
printf("\t | Count = %d |",8-i-1);
printf("\n|------------------------------|------------------------------|------------|");

}
printf("\nProduct = ");
for (i = 7; i >= 0; i--){
printf("%d", pro[i]);
}
for (i = 7; i >= 0; i--){
printf("%d", anumcp[i]);
}
}

49
RESULT:

CONCLUSION: Booth’s algorithm was implemented successfully.

LO achieved: LO4
PO achieved: PO1, PO2, PO5, PO8, PO12
PSO achieved: PSO1, PSO2

50
 EXPERIMENT NO.: 12

AIM: To implement restoring division algorithm.

THEORY:

Restoring division Restoring division operates on fixed-point fractional numbers and depends on the following
assumptions: The following division methods are all based on the form Q = A/ M where
• Q = Quotient
• A = Numerator (dividend)
• M = Denominator (divisor)
In the process of division, at each step, we need to know whether the dividend set is higher than the divisor.
This can be done by subtraction or comparison. Restoring division is a method wherein, by default, without
identifying the magnitude of the dividend set, the divisor is subtracted. This is called trial subtraction. If the
result of trial subtraction is positive, then the quotient is marked '1' and also the subtraction becomes the desired
step. However, if the trial subtraction result is negative then this becomes an undesired step necessitating a
correction; and hence the step is reverted or restored by adding the divisor. Subsequently, the quotient is marked
'0. For this reason, this method of division algorithm is called Restoring Division method.

FLOWCHART:

51
PROCEDURE / CODE:

#include <stdio.h>
#include <conio.h>
#include <math.h>

int a=0,b=0,c=0,com[8]={1,0,0,0,0,0,0,0};
int anum[8]={0},anumcp[8] ={0},bnum[8]={0};
int acomp[8]={0},bcomp[8]={0},rem[8]={0},quo[8]={0},res[8]={0};

void binary(){
int r, r2, i, temp;
a = fabs(a);
b = fabs(b);
for(i = 0; i < 8; i++){
r = a % 2;
a = a / 2;
r2 = b % 2;
b = b / 2;
anum[i] = r;
anumcp[i] = r;
bnum[i] = r2;
if(r2 == 0){
bcomp[i] = 1;
}
if(r == 0){
acomp[i] =1;
}
}
//part for two's complementing
c = 0;
for( i = 0; i < 8; i++){
res[i] = com[i]+ bcomp[i] + c;
if(res[i]>=2){
c = 1;
}
else
c = 0;
res[i] = res[i]%2;
}
for(i = 7; i>= 0; i--){
bcomp[i] = res[i];

52
 }
}
void add(int num[]){
int i;
c = 0;
for( i = 0; i < 8; i++){
res[i] = rem[i]+ num[i] + c;
if(res[i]>=2){
c = 1;
}
else c = 0;
res[i] = res[i]%2;
}
for(i = 7; i>= 0; i--){
rem[i] = res[i];
printf("%d",rem[i]);
}
printf(":");
for(i = 7; i>= 0; i--){
printf("%d",anumcp[i]);
}
}
void shl(){//for shift left
int i;
for(i = 7; i > 0 ; i--){//shift the remainder
rem[i] = rem[i-1];
}
rem[0] = anumcp[7];
for(i = 7; i > 0 ; i--){//shift the remtient
anumcp[i] = anumcp[i-1];
}
anumcp[0] = 0;
// printf("\nSHIFT LEFT: "); display together
for(i = 7; i>= 0; i--){
printf("%d",rem[i]);
}
printf(":");
for(i = 7; i>= 0; i--){
printf("%d",anumcp[i]);
}
}

53
void main(){
int i;
clrscr();
printf("\t\t\tRESTORING DIVISION ALGORITHM");
//simulating for two numbers till 125
do{
printf("\nEnter the dividend(less than or equal to 125): ");
scanf("%d", &a);
printf("\nEnter the divisor(less than or equal to 125): ");
scanf("%d", &b);
}while(a>=126 || b>=126);

printf("Expected Quotient = %d", a/b);

printf("\t Expected Remainder = %d", a%b);
printf("\t Count = 8");
binary();
printf("\n\nUnsigned Binary Equivalents: ");
printf(" Q = ");
for(i = 7; i>= 0; i--){
printf("%d",anum[i]);
}
printf(" M = ");
for(i = 7; i>= 0; i--){
printf("%d",bnum[i]);
}
printf(" M'+ 1 = ");
for(i = 8; i>= 0; i--){
printf("%d",bcomp[i]);
}
//division part
printf("\n|---------------------|---------------------|---------------------|---------|");
printf("\n| SHIFT LEFT: A : Q | SUB M: A <- A - M | ADD M: A <- A + M | COUNT |");
printf("\n|---------------------|---------------------|---------------------|---------|");
for(i=0;i<8;i++){
printf("\n| ");
shl();
printf(" | ");
add(bcomp);
if(rem[7]==1){ //simply add for restoring
printf(" | ");
anumcp[0] = 0;
add(bnum);

54
 }
else{
printf(" | ");
anumcp[0] = 1;
printf("| %d |", 8-i-1);
printf("\n|---------------------|---------------------|---------------------|---------|");
}
}
printf("\nQuotient = ");
for(i = 7; i>= 0; i--) printf("%d",anumcp[i]);
printf("\t\tRemainder = ");
for(i = 7; i>= 0; i--) printf("%d",rem[i]);
getch();

RESULT:

CONCLUSION: Restoring division algorithm was implemented successfully.

LO achieved: LO4
PO achieved: PO1, PO2, PO5, PO8, PO12
PSO achieved: PSO1, PSO2

55