1 Introduction

In this lab, 4 experiments have been performed and analysed using concepts related to Boolean algebra, com-
binational and sequential logic. This day book attempts to capture an hour by hour reflection of the process
involved in performing the experiments. Each experiment is structured to first encapsulate my thinking process,
plan and then my attempt at making simulations to verify observations. Challenges and key learning points
have also been recorded.

2 Experiment 1: RS Latch constructed by NAND gates

The requested circuit for the first experiment of this lab is designed and demonstaretd in Figure 1. In this
circuit, A0 and B0 are input signals, which result in A1 and B1 output signals respectively. It may be realised,
that this circuit follows combinational logic, meaning the inputs and outputs can be related using Boolean
algerbra. Therefore, A1 is equal to A0 NAND 1 or logical HIGH (5 Volts) and B1 is equal to B0 NAND 1.
These may be mathematically represented, as shown bellow.

A1 = A0 · 1 = A0 and B1 = B0 · 1 = B0 (1)

Figure 1: The first circuit provided in lab handout.

If ports A1 and B0 are connected; the modified circuit has an input signal A0, which results in an output
signal B1. For this circuit, we may now claim mathematicaly that A1 equals B0 (A1 = B0). To simplify this
equation, realise B0 from equation 1 may be expressed as B0 = B1. Substituting these equations and using
the principle of involution to simplify the double negation yields

A1 = A0 = B0 = B1

∴ A1 = B1 =⇒ B1 = A1.

We have realised input signal A0 and output signal B1 are one and the same. Until this point, we have made
multiple theoretical observations. To test if these observations hold merit, we may simulate this circuit using
the LTSpice software and use the CD4000 library to reproduce different forms of logic gates.

2.1 Simulating modified circuit where A1 = B0

The modified circuit is shown in Figure 2. The NAND gates use the CD4011B component of the CD4000
components family. The first NAND gate takes input signal A0 and 1 or logical HIGH (5V) in its second
terminal. Hence signal A0 can assume one of two values 0 (0 volts) and 1 (5 volts), which may be inputed in
0.1 seconds increments. After simulating this circuit, input and output signals may be represented as a voltage
vs time profile (Figure 3).

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 Figure 2: Modified circuit where A1 = B0 and is also known as a digital buffer.

Figure 3: The voltage vs time relationship for input singal A0 and output signal B1.

As displayed in the graph above, the input and output signals are equivalent in all cases. Hence, the
theoretical observation made above are valid. This circuits is also known as a digital buffer. Digital buffers are
used for a host of purposes such as: amplifying a week signal when driving high current loads and isolating the
input and output circuitry, reducing chances of loading effects casued by high impedances of input circuitry.

2.2 Developing the RS Latch

If we further explore the circuit in Figure 2, by connecting output port B1 with A0 we now form a feedback
path. Let voltage sources V 1 and V 2 equal input signals R and S respectively. The output signals are now Q
and Q. This further modified circuit is known as a RS latch demonstrated neatly in Figure 4. The feedback
paths of this latch implies that the circuit no longer obeys combinational logic and therefore Boolean algebra.
In this case, the output signal depends on the previous states of the outputs and so follows sequential logic.

Figure 4: Circuit design of a RS latch with output Q and Q.

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 Before simulating the circuit and analysing its results, we require R S Qn Qn Qn+1 Qn+1
to conduct some preliminary research. It is worth to mention that Q
1 1 1 0 1 0
and Q display an inverse relationship and are so never equal. We can
1 1 0 1 0 1
now build a characteristic table with n = 3 inputs R, S and Qn , which
1 0 1 0 0 1
implies there are 2n = 8 elements in the domain for each variable
1 0 0 1 0 1
(Table 1). As an example take R = S = Qn = 1 and therefore Qn = 0.
0 1 1 0 1 0
In this case, Qn+1 = R NAND Qn = 1 and Qn+1 = S NAND Qn = 0.
0 1 0 1 1 0
The same steps are followed for all other values. The last two rows
0 0 1 0 Invalid Invalid
are invalid, as they claim Qn+1 = Qn+1 which violates their inverse
0 0 0 1 Invalid Invalid
relationship.
Table 1: Characteristic table of RS latch
The characteristic table may can now be represented as a truth
table. When output Q and Q are 1 (HIGH) and 0 (LOW) respectively, R S Qn+1 State
the latch is said to be in the set state. Similarly, when output Q and Q 1 1 Qn No change
are 0 (LOW) and 1 (HIGH) respectively, the latch is said to be in the 1 0 0 Reset
reset state. The RS latch enters a forbidden state when R = S = 0, 0 1 1 Set
in which case outputs Q and Q are equivalent, which is unstable and 0 0 Invalid Forbidden
violates their inverse relationship. Table 2: Truth table of RS latch

2.2.1 Simulating the RS Latch

We may now begin simulating with different values of R and S. Lets start by setting signal R to 0 (LOW - 0V)
and S to 1 (HIGH - 5V) for 0.1 seconds and then allow both signals to equal 1 for the next 0.1 seconds. Realise,
we do not right away change signal R to 1 and S to 0, as if S reaches 0 before R reaches 1, the latch will be
in its forbidden state. We may now set signal R to equal 1 and S to equal 0 for the next 0.1 seconds and then
allow both signals to equal 1 for another 0.1 seconds to prevent the forbidden state. Lastly, to confirm if the
forbidden state exists or not we may set signals R and S to 0 for 0.1 seconds. After simulating this sequence of
signals, a voltage vs time profile is shown for inputs and outputs in Figure 5.

Figure 5: The relationship between voltage and time for different input and output values of a RS latch.

We can formulate a truth table as demonstrated in Table 3. As shown from the profile and truth table,
when input R = 0 and S = 1, the outputs are in their set state where Q = 1 and Q = 0. Then, when both
inputs R and S change to 1, the outputs remain in the set state. Similarly, when input R = 1 and S = 0, the
outputs are in their reset state where Q = 0 and Q = 1. Likewise, when both inputs R and S return to 1, the

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outputs remain in their reset state. When both inputs R and S are equal to 0, the outputs enter their forbidden
state where Q and Q equal 1. These results confirm our theoretical findings made above. Using these we can
produce a state diagram as shown in Figure 6.

R S Q Q State
0 1 1 0 Set
1 1 1 0 No change
1 0 0 1 Reset
1 1 0 1 No change
0 0 1 1 Forbidden
Table 3: Truth table for RS latch.

Figure 6: State Diagram of a RS latch

Hence, the RS latch has two stable states (set and reset), which can be used to store information or used
as a start and stop switch for multiple machinery. However, a drawback of this latch is that both inputs must
be set to 1 before changing states, otherwise the function of this latch is indeterminate. Similarly, inputs to
a RS latch can never equal 0 simultaneously or an unstable forbidden state is realised. This task was very
straightforward. I clearly understood the concept of states and how they are practically useful.

3 Experiment 2: D-latch with synchronised inputs

In the previous experiment, it was realised that RS latches are sensitive to the timing at which input signals
R and S are set. Otherwise, their output becomes uncontrollable and indeterminate. This was seen when the
latch realised its forbidden state. In order to prevent this state, both input signals were brought to logic level
1 and then changed. However, if both inputs are synchronised we can achieve the ideal characteristics of a RS
latch. This implies, signals can interchange without the intermediate step of bringing them to logic level 1. In
order to achieve this synchronisation, we require some form of a control input, which allows both input signals
to act at the same time.
Realise, if one input to a NAND gate is set to logic level 1, the other input is always allowed to propagate.
The contrary is true, if this input is set to logic level 0. Now we may use this idea with two NAND gates. The
first NAND gate has input signals R and a control signal. The second NAND gate has input signal S and the
same control signal as gate 1. If this control signal is set to 1, both R and S are allowed to propagate and the
opposite is true when the control signal is set to 0. Such control signals are known as Enables (En). If these
two NAND gates are connected to a RS latch, we achieve the desired synchronisation.
However, notice how this time the inputs to the latch are R and S, due to the NAND gate. Hence, the
forbidden state now arises when R = S = 1. This means the no change state from Table 3 occurs when
R = S = 0. Also notice, when enable En is set to 0,inputs to the RS latch are 1 which is also the no change
state. These observation are of useful importance before simulating.

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3.1 Simulating RS latch with ’Enable’
The synchronised RS latch with enable is demonstrated in its circuit representation bellow (Figure 7). Input
signal R is first set to logic level 0, then 1 (to test the set and reset states), then 0 and 1 (to test no change
state) in 0.1 second increments. Input signal S is set to logic level 1, then 0 (to test the the set and reset states),
then 0 and 1 (to test no change state) in 0.1 second increments. Lastly, enable is in logic level 1 for the first
0.3 seconds (to test set, reset and no change states) and then 0 for 0.1 seconds (to test no change state). The
simulation results for inputs and outputs are demonstrated as a voltage vs time profile in Figure 8.

Figure 7: Circuit design of a RS latch with enable output Q and Q.

Figure 8: The relationship between voltage and time for different input and output values of RS latch with enable.

Using the graph in Figure 8 a truth table can be constructed as shown

in Table 4. As can be seen, the RS latch is synchronised as no errors R S En Q Q State
appear when R and S vary interchangeably. When enable En = 1, while 0 1 1 0 1 Reset
input signals R and S are at logic levels 0 and 1 respectively, Q and Q 1 0 1 1 0 Set
are at 0 and 1 (reset state). Similarly, when input signal R and S are at 0 0 1 1 0 No change
logic level 1 and 0 respectively, Q and Q are 1 and 0 (set state). Lastly, 1 1 0 1 0 No change
as expected when R and S are both at 0 no change occurs. At the same
Table 4: Truth table of RS latch with enable.
time, when enable En = 0 the outputs again do not change. These results
confirm the observations made in the section above.

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3.2 Developing the D Latch
Whenever changing between states, input signals R and S are always different. For convenience and simplicity,
we can ensure R and S are never equal. In this way we can completely eliminate the concept of a forbidden
state. To achieve this circuit we may use some input signal D, which is directly fed into R and negated before
being fed into S. The no change state can easily be achieved by setting the enable En to 0. This modified circuit
is known as a D latch and represented as a circuit diagram in figure 9. The D latch includes all functionalities of
a RS latch with enable, except it does not have a forbidden state and only one way to achieve a no change state
as the output. Nevertheless, it is more practical and simple in comparison to a RS latch. Before simulating, lets

Figure 9: The circuit diagram of a D latch.

establish a relationship between input signal D and signals R and S. Using the circuit in figure 9, when signal
D is at logic level 1, signals R and S are 1 and 0 respectively. At the same time, when signal D is at logic level
0, signal R and S are 0 and 1 respectively. According to the truth table in Table 4, this implies when D = 1
the outputs are in their set state. The contrary is true when D = 0.

3.2.1 Simulating the D latch

In order to verify the observations made above, the D latch circuit can be simulated. Input signal D is first set
to logic level 1, then 0 (to test set and reset states) and then again 0 (to test no change state) in 0.1 second
increments. Enable is set to 1 for 0.2 seconds (to test set and reset states) and then 0 for 0.1 seconds (to test
no change state). The simulation results are displayed as a voltage vs time profile in Figure 10.

Figure 10: The relationship between voltage and time for different input and output values of a D latch.

Using the graph in Figure 10, the truth table shown in Table 5 is formed. As can be seen, when enable is

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set to En = 1 and input signal is at D = 1, outputs Q and Q are at 1 and 0 respectively (set state). Similarly,
when D = 0 the outputs are Q = 0 and Q = 1 (reset state). Lastly, when the enable En is changed to 0 the
outputs do not change value.

D En Q Q State
1 1 1 0 Set
0 1 0 1 Reset
0 0 0 1 No change
Table 5: Truth table of a D latch.

This experiment was straightforward and very logical to follow. I found it very interesting how circuits can
be simplified and modified to achieve functionalities for different purposes.

4 Experiment 3: D flip-flop with CD4013

Two D latches can be used to create a device known as a D flip-flop. The first latch is known as the master and
the second as slave. In this case, the enable signal is known as the clock signal Clk. By feeding the master’s
output signal Q, as the input signal for the slave and allowing both latches to share the same clock signal we
construct an edge triggered D flip-flop. Such flip-flops are transparent at rising edges of the clock signal (allow
the input signal to pass straight through to the output - Qn+1 ) until falling edges, where the previous output
(Qn ) becomes the current output. At the same time, a falling edge triggered D flip-flop is one where the clock
signal to the slave is negated. This information is directly obtained from Digital Design 2 course material. For
simplicity, we shall only consider a rising edge triggered D flip-flop throughout this experiment.
It must be noted here that, there is a difference between positive/negative edge triggered flip-flops and
rising/falling edge triggered flip flops. The former only memorises and outputs the logic level at which the
rising/falling edge occurs. Meanwhile the later becomes transparent, allowing the input signal to fully pass
through at the output. The later is also simply known as ’edge’ or ’level’ triggered D flip-flops.

4.1 Simulating a D flip-flop using NAND gates

A rising edge triggered D flip-flop is constructed using the descriptions provided above and displayed in Figure
11. For simulating this circuit, I have selected a random pulsating signal for input signal D. The clock signal
Clk alternates between logic levels 1 and 0 every 0.1 seconds. The input and output signals to this circuit are
represented as a voltage vs time profile as shown bellow (Figure 12).

Figure 11: Circuit design of a rising edge triggered D flip-flop.

As can be seen from the graph bellow, at the rising edges of the clock signal (Clk), the D flip-flop is
transparent and allows input signal D to propagate through to the output. At the falling edges, the flip-flip is
no longer transparent and memorises the logic level of the output at this edge. This memorised output becomes

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 Figure 12: The relationship between voltage and time for a rising edge triggered D flip-flop.

its current output. At the next rising edge, the D flip-flop becomes transparent again. The same steps are
followed for the next falling edge too; the output at the edge is memorised and becomes the current output.

4.2 Behaviour of a CD4013 D flip-flop

The CD4000 component library includes a D flip-flop component known as CD4013B. There are many functions
a D flip-flop may be designed to undertake. Therefore, we must understand the behaviour of a CD4013B flip-flop
in order to identify its function. The master-slave D flip-flop designed in the previous section, was a rising edge
triggered flip-flop. To assert what kind of a D flip-flop CD4013B is, we may run it through a simulation.

4.2.1 Simulating a CD4013B D flip-flop

A CD4013B has 4 input terminals and 2 output terminals. The first input signal is D, which is comparable to
the input for our master-slave D flip-flop and D latch. Similarly, the second input signal is the clock signal Clk.
The 2 new input signals are P RE and CLR. If input signal P RE = 0 and CLR = 1 the output is T DAT = 1
(set state), irrespective of input signals D and Clk. When P RE = 1 and CLR = 0 the output is T DAT = 0
(reset state), again irrespective of D and Clk. For our purposes, both input signals P RE and CLR will be
connected ground or logic level 0. Now we only understand the relation between inputs D and Clk and outputs
T DAT and T DAT .
The same input signals D and Clk used for the master-salve D flip-flop simulation can be utilised. To
reiterate, signal D is a random pulsating signal and Clk is a pulsating signal with a period of 0.2 seconds, with
the 0.1 seconds at logic level 1 and the remaining 0.1 seconds at 0. The circuit diagram for this simulation is
shown bellow (Figure 13). The input and output voltage vs time profile is displayed in Figure 14.

Figure 13: Circuit design of CD4013B D flip-flop.

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 Figure 14: The relationship between voltage and time of a CD4013B D flip-flop.

As can be seen from the graph displayed in Figure 14, at every rising edge of the clock signal the logic level of
input D is registered and yielded as the output signal until the next rising edge. Hence, this D flip-flop contrary
to the master-slave one does not become transparent at edges. These characteristics display the behaviour of a
positive edge triggered D flip-flop, as the output changes every rising edge (positive edge) and does not display
transparency. What would happen if two CD4013B flip-flops are connected together (the first components
output becomes the input for the next)?

4.3 Two CD4013B D flip-flops

A simulation can be made by connecting two CD4013B D flip-flops to see what occurs. The same input signals
D and Clk as in the previous section are used for determining the outputs. The circuit has not been presented,
as it involves the circuit represented in Lab 3 handout for this experiment. The simulation results are displayed
as a voltage vs time profile bellow (Figure 15).

Figure 15: The relationship between voltage and time of 2 connected CD4013B D flip-flops.

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 As can be seen from the graph above, output T DAT appears 0.2 seconds delayed from the case with just
one D flip-flop. It may therefore be hypothesised, through connecting more CD4013B components the delay of
output will increase. It must be realised the setup and hold time are very important to consider. The output
of the first CD4013B becomes the input for the second flip-flop, for which the input signal changes very close
to the pulsating clock signal. If here the input signal is unstable within its setup/ hold time, a violation occurs
and the output becomes indeterminate.
The setup and hold time can be determined using a simulation. The simulation was run by using a one
pulse input signal D and Clk. The on time for signal D was varied and brought closed the rising edge of Clk
to test when the output signal becomes indeterminate. Through trial and error it was found the setup time is
20ns (×10−9 - nano seconds) and the hold time is around 7ns.

5 Experiment 4: Shift Register achieved by D flip-flop

As was hypothesised in section 4.3, connecting n CD4013B flip-flops would result in the output from the first
flip-flop delayed by n times. At this point, it is important to define a register. A register is a type of flip-flop
which shares a common clock signal and is able to hold a single bit of information. Hence, n D flip-flop connected
together is considered a register (particularly known as a shift register), as each flip-flop represents one bit and
shares a common clock signal.
In this experiment, we have been tasked to recreate a sequence of 4-bit outputs. Therefore, we require 4
CD4013B components (Figure 16). For each rising edge of Clk, outputs Q4 Q3 Q2 Q1 should change from 0001
to 0010 to 0100 to 1000 and repeat the pattern again respectively. Since, the pattern must repeat, a feedback
path from output Q4 back to input D is required. Realise, there can only be one input signal. Hence, input
signal D should only pass initially and later allow feedback from Q4 to be fed in the register. Hence, the circuit
implements an initial NAND logic gate circuit before being fed in the shift register.

Figure 16: The circuit representation of a shift register.

Figure 17: The circuit representation of a shift register.

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 In order to recreate the sequence described above, Q1 requires to be at logic-level 1 after the first rising
clock edge. Then, the same for Q2 until Q4 each time with a given time delay to follow the sequence (delay is
caused naturally with the D flip-flops). Hence, input signal D requires to only have one pulse at the rising edge
T1 of Clk. The Clk is a pulsating periodic signal with 0.1 seconds at logic level 1 and the next 0.1 second at 0
(period is 0.2 seconds). The results may be represented as a voltage vs time profile bellow in Figure 17.
Using the graph above a table may be formed to display the sequence of outputs (Table 6). Note, Tn
represent the n ∈ Z+ rising edges of Clk. Hence, it may be realised the circuit is able to perform one hot
encoding.

Signal Q4 Q3 Q2 Q1
Initial 0 0 0 1
T1 0 0 1 0
T2 0 1 0 0
T3 1 0 0 0
T4 0 0 0 1
Table 6: Table representing the one hot shift register.

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