PROGRESS AND APPLICATION OF THROUGH GLASS VIA (TGV)

TECHNOLOGY

Aric B. Shorey and Rachel Lu

Corning, Incorporated
Corning, NY USA
shoreyab@corning.com

ABSTRACT electrical loss, low or adjustable dielectric constant, and

Glass provides many opportunities for advanced adjustable coefficient of thermal expansion (CTE). There
packaging. The most obvious advantage is given by the has been much work in recent years as researchers
material properties. As an insulator, glass has low electrical demonstrate leveraging glass properties to achieve these
loss, particularly at high frequencies. The relatively high objectives [3]-[6].
stiffness and ability to adjust the coefficient of thermal In order to leverage glass for many RF and interposer
expansion gives advantages to manage warp in glass core applications, it is often necessary to have precision vias for
substrates and bonded stacks for both through glass vias electrical interconnect and other functional purpose. The
(TGV) and carrier applications. Glass also gives advantages ability to put precision holes in glass and downstream
for developing cost effective solutions. Glass forming metallization to create these vias continues to mature
processes allow the potential to form both in panel format as towards volume manufacture. Work in recent years has also
well as at thicknesses as low as 100 um, giving demonstrated the reliability of these structures in glass [7]-
opportunities to optimize or eliminate current manufacturing [9].
methods. Over the past several years at Corning Incorporated, there
As the industry adopts glass solutions, significant have been significant advances in the ability to provide
advancements have been made in downstream processes high-quality vias in glass substrates of various formats.
such as glass handling and via/surface metallization. Of Examples are shown in Fig.1. The process employed
particular interest is the ability to leverage tool sets and provides the opportunity to leverage both through and blind
processes for panel fabrication to enable cost structures vias in both wafer and panel format. The glass substrates
desired by the industry. Here, we provide an update on with holes have been shown to give strength on par with
advancements in these areas as well as handling techniques bare glass, and filled vias have been shown to have excellent
to achieve desired process flows. We also provide the latest mechanical and electrical reliability after thermal cycle tests
demonstrations of electrical, thermal and mechanical [9]-[11]. The approximate current best practice capabilities
reliability. are summarized in Table 1 below. These represent guidance
for the current TGV process, but in many cases the
Key words: Through glass via (TGV); glass; panel capabilities can be extended.

INTRODUCTION
New initiatives in semiconductor packaging have created
needs for new materials solutions. There has been
substantial effort to extend interposer technology for 3D-IC
stacking. Multiple solutions are being developed to address
some of these needs including traditional interposers 1a: Through Glass Vias 1b: Blind Glass Vias
utilizing various commonly used materials as well as Fan- Fig. 1: Examples of both through glass vias (TGV) and
Out Wafer Level Packaging (FOWLP), which has become a blind glass via (BGV).
popular consideration in attempt to achieve lower cost. [1]
Furthermore, the proliferation of mobile devices and the In addition to enhanced technical performance, packaging
Internet of Things (IoT), leads to increasingly difficult solutions must also be cost effective. Glass forming
processes such as Corning’s fusion forming process, gives
requirements in RF communications. These include such
the ability to form high quality substrates in large formats
requirements as the introduction of more frequency bands,
(>> 1 m in size). The process can be scaled to deliver ultra-
smaller/thinner package size and need to conserve power to
slim flexible glass to thicknesses down to ~100 µm.
increase battery life as new functionality is introduced.
Glass has proven to be an excellent solution to these Providing large substrates in wafer or panel format at 100
µm thickness gives significant opportunities to reduce
challenges. [2]
manufacturing costs. The advantages given by Corning’s
Glass has many properties that support the initiatives
fusion forming process for supplying substrates for
described above. These include high resistivity and low
© 2016 Corning Incorporated. All Rights Reserved.
electronics applications, has been previously reported [7], frequencies. Work done in collaboration with the Industrial
[8]. Technology Research Institute (ITRI) in Taiwan illustrates
this well. [16] In this work co-planar waveguides (CPW),
Table 1. TGV specification micro-strip lines (MS) and co-planar waveguides with 2 vias
Attribute Current Capability* were constructed on glass and silicon substrates, and
Outer Diameter (OD) 25 – 100 um impedance matched to ~50 ohm. The structures where then
Minimum Pitch ~2x OD tested up to 20 GHz and insertion loss was characterized.
Type Through and Blind The results are shown in Fig. 3. Since glass is an insulator,
Wafer Size Up to 300 mm there is much less loss as frequency is increased beyond a
Panel Size Up to 515 x 515 mm few 100’s of MHz. Given the importance of minimizing
Thickness (mm) 0.1 – 0.7 power loss at these higher frequencies coupled with the need
*Approximate. to continue to reduce package size, glass provides valuable
material for all applications working in the GHz range.

II. Glass Material Properties

A. Adjusting the CTE for Carrier and Interposer
Applications
Glass material properties are determined by the specific
chemical make-up of the glass, making it possible to tailor
glass composition to achieve a targeted CTE; thus enabling
management of stack warp. Previously, we have shown
examples of the material properties of two fusion formed
glass types, in which it is possible to achieve very different
CTE values while maintaining similar mechanical properties
[7].
Fig. 3 – The insertion loss (S21) from transmission lines on
One of the important challenges in 3DIC stacking is
glass and standard silicon substrates showing much less loss
reliability due to CTE mis-match and glass provides an
in glass at higher frequencies. A good example of
excellent opportunity to manage warp of 3D-IC stacks but
optimizing CTE. [6] Figure 2 gives an illustration of the leveraging the insulating properties of glass is to provide
challenge of stacking substrates with multiple CTE in an high-Q inductors and capacitors in a glass-based LC
interposer application. Figure 2a schematically shows Si network as recently described [2]. In this work, the high-Q
chips mounted on a Si interposer, which is then mounted on inductors were created by utilizing solenoid inductors
an organic substrate. The CTE mismatch causes failures shown schematically in Fig. 4a. The top and cross sectional
when the substrates go through temperature cycles. view of the fabricated inductors is shown in Figs. 4b and 4c
However, if instead of a Si interposer, a glass interposer respectively. High-Q capacitance was achieved by utilizing
with CTE in between glass and organic is used, this warp a metal-insulator-metal construction. Fig. 5 shows the MIM
can be better managed and increased reliability realized as capacitor formed on the same TGV glass substrate.
demonstrated in work at Georgia Tech’s Packaging
Research Center (PRC) and illustrated Fig. 2b. [6]

2a: CTE mis-match creates 2b: Utilizing the ability to

reliability challenges. adjust the CTE of glass helps to
manage warp and improve
reliability.

Fig. 2: Illustration of CTE mismatch in 3DIC stacking.

B. Electrical Performance
As new, higher frequencies used in RF applications are
released, the electrical properties of the substrates become
increasing important. As a semiconducting material,
standard silicon tends to have increased loss at higher
© 2016 Corning Incorporated. All Rights Reserved.
 Fig. 6 SEM bird’s eye view of completed LC networks
device.

Thermal Cycle Testing

The fabrication of thin glass interposers with Cu filled
through glass vias (TGV) was done using standard back end
of line (BEOL) fabrication tools with no significant
modification of any of the equipment wafer handling to
accommodate glass wafers. In order to test the effect of the
glass CTE on the long term reliability of the glass
interposers, 150 mm glass wafers formulated with two
different CTEs, 3 ppm/°C and 8 ppm/°C, were used in the
Fig. 4. 3D TGV inductor formation. (a) 3D rendering, (b) fabrication process.
top-down photograph, (c) cross-sectional SEM of TGV with Full thickness 150 mm glass wafers with 35 µm x 125
conformal Cu plating on the TGV sidewalls and the top & µm blind TGVs were sputtered with a thin adhesion layer of
bottom sides of the glass to form a 3D TGV inductor Ti and Cu. No barrier or additional dielectric layer were
deposited in the TGVs before the metallization. Highly
conformal copper seed layers were deposited using metal-
organic chemical vapor deposition (MOCVD), in
preparation for TGV plating. The seed layers were
nominally 0.75µm in thickness, which was uniform
throughout the TGVs. Electroplating of Cu was used to fully
fill the TGVs and the overburden was removed using
chemical mechanical polishing (CMP). High resolution x-
ray imaging was used to verify the void-free nature of the
Cu fill in the TGVs. To form the TGV test structures,
plated Cu routing layers were patterned on both sides of the
thin wafers. These routing layers were electroplated on a
Fig. 5 Cross-sectional SEM of TGV with conformal Cu
sputtered Ti/Cu seed layer with no barrier covering the glass
plating on the TGV sidewalls and the top & bottom sides of
substrate. Thin wafer handling was done using 3M’s Wafer
the glass to form a 3D TGV inductor
Support System (WSS). More details on the fabrication of
these glass interposer test vehicle wafers can be found in
previously published work [9].
The TGV IPD parts were mounted on evaluation boards and After fabrication was completed, wafers from each glass
further tested for both electrical functionality and thermal type were electrically tested for continuity of the daisy chain
and mechanical reliability, showing no performance test structures. Electrical continuity testing was done on
degradation or any board-level reliability issues. The eight test arrays, randomly chosen across the diameter of
insulating properties of glass provide very high-Q four wafers. Each test array consisted of 20 x 20 TGVs on
performance. 100 µm pitch, with each of the TGVs connected in series.
The TGV test chain array, an example of which is shown in
Figure 7, has testing points at the front and back of every
TGV, so that any electrical discontinuity can be tracked
down to the single metal link or TGV. The results of the

© 2016 Corning Incorporated. All Rights Reserved.

initial round of electrical continuity testing are shown in SWG8-Wafer 2 8.1 100.00 6.7
Table 2. The combined yield of the TGVs and routing metal
500 SWG3-Wafer 1 3.2 100.00 15.4
links was over 99.85% for both types of glass.
cycles SGW8-Wafer 2 8.1 100.00 13.5

1000 SGW3-Wafer 1 3.2 100.00 16.6

cycles SGW8-Wafer 2 8.1 100.00 15.9

III. Form Factor

Another valuable aspect of leveraging glass as a
semiconductor packaging substrate is that the forming
processes lend themselves to providing large form
factors.[7], [8] This is important as the IoT will require

Figure 7. Optical microscope image of a TGV daisy chain

test feature consisting of a 20 x 20 array of TGVs on 100
µm pitch. The topside metal links appear as copper colored
and the links on the backside appear white.

Table 2. The results of 2-wire electrical continuity tests on

20 x 20 arrays of TGVs on 100 µm pitch

CTE No. of 20x20 Yield of TGVs &

Wafer
(ppm/°C) arrays tested routing metal (%)

SGW3 - Wafer 1 3.2 8 99.97 Figure 8. Cross section SEM image from an interposer
test vehicle in SGW3 glass after 1000 thermal cycles.
SGW3 - Wafer 2 3.2 8 99.97
These were measured to be from 17 µm to 19 µm in
SGW8 - Wafer 1 8.1 8 99.72 diameter at the wafer backside and 35 um diameter at the
SGW8 - Wafer 2 8.1 8 100.00 front side.

After this initial test, eight additional test arrays were billions and even trillions of devices and sensors. Being
selected from each type of glass with starting TGV array able to utilize economies of scale given by panel processing
yields of 100%. These arrays were then subjected to thermal is very important.
cycle testing, which consisted of 1000 cycles from -40°C to Recent work has shown significant progress in the ability
125 °C with 1 hour cycle time and 15 min soak time at each to process glass panels > 500 mm in size [17]. An
temperature extreme (JEDEC JESD22-A104 condition G). important outcome of this work demonstrated one advantage
An intermediate test point of 500 cycles was also done. The of using glass in this application. Specifically, that the
results of electrical testing at 0, 500 cycles, and 1000 cycles increased stiffness and thermal stability of glass relative to
are shown in Table 3. Figure 8 shows the TGV profile after current solutions results in improved flatness (See Fig. 9).
1000 thermal cylcles. Note that there is no cracking or In Fig. 9a, the profile of a 508 mm 508 mm panel size
delamination seen. glass substrate with two layers build-up after pre-cure
processes is shown. Figure 9b shows the profile of organic
Table 3. The results of 2-wire electrical continuity tests on substrate after same processes. There is ~3 x better war
eight known-good 20 x 20 arrays of TGVs on 100 µm pitch page performance for the glass based substrate. This has
before and after thermal cycle testing important implications in that the improved flatness of the
No. of
Yield of Median glass based substrate enables finer lines and spacing for
CTE TGVs & chain redistribution layers relative to organic substrates. This
thermal Wafer
(ppm/°C) routing resistance
cycles
metal (%) ) allows high performance devices to be fabricated in a panel
format, which provides substantial opportunity for both cost
0 cycles SWG3-Wafer 1 3.2 100.00 10.4
effective and high quality solutions.
© 2016 Corning Incorporated. All Rights Reserved.
 processed further. This approach is relevant for wafers and
panels.
Work recently at RTI International in Research Triangle,
NC has been done to demonstrate feasibility of utilizing the
ALoT structure to perform metallization of the vias. Glass
with 100 um thickness and ~30um diameter through vias
was provided on a carrier. RTI then applied the seed layer
and via fill using a process consistent with the method used
9a 9b to fill blind vias.[9] However, instead of back grinding to
Fig. 9: (a) War page measurement result of glass substrate after expose the bottom of the vias, with ALoT the thin glass is
two layers build-up (b) War page measurement result of organic peeled off mechanically as shown schematically in Fig. 12.
substrate after build-up Figure 13 shows the 150 mm bonded wafers.

In addition to scaling glass substrate size, it is possible

scale the process to deliver ultra-slim flexible glass to
thicknesses down to ~100 um (see Fig. 10). Providing large
substrates in wafer or panel format at 100 um thickness
gives significant opportunities to reduce manufacturing
costs because there is likely to be no need for grinding and
polishing operations.

Fig. 12: Cartoon of leveraging ALoT technology

to metallize through vias in 100 um thick glass.

Fig.10. Manufacture of high quality ultra-slim flexible

Corning® Willow® Glass provides substantial opportunities to
deliver substrates for TGV that do not require post processing.
150 mm
Handling of ultra-thin glass in standard wafer or panel
processing operations can be a challenge. However,
solutions are being developed. Corning’s Advanced Lift-off
Technology (ALoT) is a carrier based solution that is
designed to be compatible with high temperatures (> 450 C)
without outgas, as well as maintaining compatibility with
important process chemistries such as cleaning (SC1, SC2,
etc.) and metallization. The process is shown schematically
in Fig. 11. Fig. 13: Image 100 um thick glass with 30 um
diameter vias temporarily bonded onto a glass
carrier using ALoT technology.

Fig. 11. Schematic showing an approach for handling thin glass

through metallization.

The approach is to apply a surface treatment on a glass

carrier wafer to prevent permanent bond at high
temperatures, while maintaining enough adhesion strength
Fig. 14: Cartoon of leveraging ALoT technology
to enable via and surface metallization. The thin metallized
to metallize through vias in 100 um thick glass.
glass TGV wafer will then be mechanically de-bonded and

© 2016 Corning Incorporated. All Rights Reserved.

Figure 14 shows the result after via metallization and leveraged to generate very good Cu filling performance in
overburden removal from the top surface. The thin glass glass in both wafer and panel formats. Reliable performance
completed processes for via metallization, overburden of Cu-filled vias in glass has been demonstrated. These
removal and Chemo-Mechanical Planarization (CMP) and developments make glass an exciting material for next
very good planarity of the Cu and glass surface was generation packaging applications.
achieved. After completion of top surface CMP, the wafers
were mechanically de-bonded and an SEM image of the Acknowledgment
TGV on the back surface was collected to evaluate the The authors would like to extend sincere thanks to their
ability to achieve good planarity without any post- development partners at RTI International, Industrial
processing (e.g. there was no planarization of the back Technology Research Institute (ITRI) and
surface). Figure 15 shows an SEM image of the back Georgia Tech’s Packaging Research Center (PRC).
surface TGV after de-bond. There is work to be done to
achieve perfect bond and planarity, but the result shows the References
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© 2016 Corning Incorporated. All Rights Reserved.