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Integrated Circuit
Design with the BJT

As mentioned in Chapter 8, design of electronic circuits on a chip can be considerably 10.1 Integrated Circuit
Biasing with Current
different from discrete circuit design. Some analog circuits do not require high component
Mirrors
densities, whereas others may pack a great deal of circuitry into a small chip space. For
10.2 High-Gain Stages Using
low-density circuits, more resistors and small capacitors may be used, but for high-density Active Loads
circuits, these elements must be minimized. 10.3 Amplifier Configurations
This chapter will consider circuits that replace resistors and capacitors with additional In BJT Integrated
BJTs, just as Chapter 9 considered replacing these elements with additional MOSFETs. Circuits

The organization of this chapter is similar to that of Chapter 9. The BJT current mirror,
which is quite popular in biasing of IC amplifiers, will be discussed first. The chapter
will then proceed to active load amplifier stages and other single-stage amplifier config-
urations in order to lay a foundation for the important op amp chip to be discussed in
Chapter 11.

DEMONSTRATION PROBLEM
A typical problem that uses the principles appearing in this chapter is shown in the amplifier
circuit. For all devices β = 80, |VBE(on) | = 0.7 V, and |V A | = 62 V (Early voltage). Assume that
Cµ = 2 pF, Cπ = 20 pF, and Ccs = 2 pF for all devices. The dc voltage at the output is 4 V.
Calculate the overall midband voltage gain and upper corner frequency of the amplifier.

8V BJT amplifier for Demonstration

Problem.

Q4 Q3

Q2
1 kΩ
12 kΩ Q1 vout
Rg
vin 10 kΩ

V1

307
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308 CHAPTER 10 INTEGRATED CIRCUIT DESIGN WITH THE BJT

In order to solve this problem, the following questions must be answered.

1. What determines the output current of a current mirror?

2. What determines the voltage gain when the load consists of the output stage of a current
mirror?
3. What determines the upper corner frequencies of a common-emitter stage and an emitter
follower?

These questions will be answered in general terms throughout this chapter.

10.1 Integrated Circuit Biasing

with Current Mirrors

I M P O R T A N T Concepts

1. The simple current mirror is often used on integrated circuit chips to provide bias
current for amplifier stages.
2. The output impedance of current mirrors can be increased by certain
modifications. A higher output impedance leads to a better approximation of a
true current source.

The popular emitter-bias scheme of Fig. 7.16 for discrete BJT stages often uses a large
emitter bypass capacitor to achieve high ac gain. Discrete amplifier stages may also use
relatively large interstage coupling capacitors. The unavailability of large capacitors and
inductors in IC designs requires that special techniques be used to establish bias currents for
integrated amplifiers. Differential stages and complex feedback circuits are often used to
obtain the correct bias in the IC amplifier. Although differential amplifiers will be discussed
in the next chapter, a significant bias scheme used in differential BJT and other IC amplifier
stages will be considered in the following paragraphs.

10.1.1 THE SIMPLE CURRENT MIRROR

The simple current mirror of Fig. 10.1 represents a popular method of creating a constant
current bias for differential stages. The concept of the current mirror was developed specif-
ically for analog integrated circuit biasing and is a good example of a circuit that takes
VCC advantage of the excellent matching characteristics that are possible in integrated circuits.
In the circuit of Fig. 10.1, the current Io is intended to be equal to Iin . Although not shown
in the figure, the external circuit through which Io flows connects to the collector of Q2.
Iin R In Chapter 9 we discussed the specific operation of the MOSFET current mirror. The
following material will expand on the use of current mirrors and apply this material to
Io the BJT version of this circuit. It is useful to discuss the more generalized concept of a
current mirror and to introduce some appropriate terminology. Figure 10.2 illustrates a
Q1 Q2 block diagram representation of a current mirror where the input or reference current and
output currents are shown. Current mirrors can be designed to serve as sinks or sources, as
indicated in the figure.
The general function of the current mirror is to reproduce or mirror the input or reference
Figure 10.1 current to the output while allowing the output voltage to assume any value within some
Current mirror bias stage. specified range. The current mirror can also be designed to generate an output current that
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SECTION 10.1 INTEGRATED CIRCUIT BIASING WITH CURRENT MIRRORS 309

+V
Iin Io

In Out

Sink Source

In Out

Iin Io Figure 10.2

—V Block diagrams of current
mirrors: (a) current sink,
(a) (b) (b) current source.

equals the input current multiplied by a scale factor K . The output current can be expressed
as a function of input current as

Io = K Iin (10.1)

where K can be equal to, less than, or greater than unity. This constant can be established IC A
accurately and will not vary with temperature.
A VB Q1
Current Source Operating Voltage Range Figure 10.3(a) shows an ideal or
theoretical current sink with a practical sink indicated in Fig. 10.3(b). The voltage at node A VE
I
in the theoretical sink can be tied to any voltage above or below ground without affecting the R
value of I . On the other hand, the practical circuit of Fig. 10.3(b) requires that the transistor B
B
remain in the active region to provide an output current of
VE VB − VBE
I = IC = α I E = α =α (10.2) (a) (b)
R R
Figure 10.3
The collector voltage must exceed the voltage VB at all times for active region operation. Current sink circuits:
The upper limit on collector voltage is determined by the breakdown voltage of the transistor. (a) ideal sink, (b) practical sink.
The output voltage must then satisfy

VB < VC < (VE + BVCE ) = (VB − 0.7 + BVCE ) (10.3)

where BVCE is the breakdown voltage from collector to emitter of the transistor. The voltage
range over which the current source operates within a prescribed accuracy is called the output
voltage compliance range or the output compliance.

Current Mirror Analysis The current mirror is again shown in Fig. 10.4. If devices
Q1 and Q2 are assumed to be matched devices, we can write

I E1 = I E2 = IEO e VBE /VT (10.4)

VC2 Figure 10.4

Iin Circuit for current mirror
IC2 = Io analysis.
IC1

Q1 Q2
IB1 IB2
VBE
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310 CHAPTER 10 INTEGRATED CIRCUIT DESIGN WITH THE BJT

where VT = kT /q, IEO = A JEO , A is the emitter area of the two devices, and JEO is the
current density of the emitters. The base currents of the two devices will also be identical
and can be expressed as

IEO VBE /VT

I B1 = I B2 = e (10.5)
β +1

Device Q1 operates in the active region, but near saturation by virtue of the collector-
base connection. This configuration is called a diode-connected transistor. The collector
current of Q1 is β times the base current or

β
IC1 = β I B1 = IEO e VBE /VT (10.6)
β +1

Whereas device Q1 is constrained so that VCE = VB E(on) by the connection between base
and collector, device Q2 does not have this constraint. The collector voltage for Q2 will be
determined by the external circuit that connects to this collector.
If we limit the voltage VC2 to small values relative to the Early voltage, IC2 is approxi-
mately equal to IC1 . For integrated circuit designs, the voltage required at the output of the
current mirror is generally small, often making this approximation valid.
The input current to the mirror is slightly larger than the collector current and is expressed
as

Iin = IC1 + 2I B (10.7)

Since Io = IC2 = IC1 = β I B , we can write Eq. (10.7) as

Iin = β I B + 2I B = (β + 2)I B (10.8)

Relating Iin to Io results in

β
Io = Iin (10.9)
β +2

For typical values of β these two currents are essentially equal. Thus, a desired bias current,
Io , is generated by creating the desired value for Iin .
The current Iin is normally established by connecting a resistance, R1 , between a voltage
source VCC and the collector of Q1 to set Iin to

VCC − VBE
Iin = (10.10)
R1

Control of collector current for Q2 is then accomplished by choosing proper values of VCC
and R1 .
If VC2 becomes larger, the Early effect of Eq. (7.11) must be considered. This equation is
 
VCE
IC = β I B 1+ (10.11)
VA
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SECTION 10.1 INTEGRATED CIRCUIT BIASING WITH CURRENT MIRRORS 311

Iin Io1 Io2 IoN

Q1 QN+1
Q2 Q3

Figure 10.5
Multiple output current mirror.

A more accurate expression for the output current is

 
β 1 + VVC2A
IC2 =   Iin (10.12)
2 + β 1 + VVC1A

where VA is the Early voltage. This equation can be used to find the voltage compliance
range of the current mirror.
Figure 10.5 shows a multiple output current mirror. It can be shown that the output
current for each identical device in Fig. 10.5 is
β
Io = Iin (10.13)
β + N +1
where N is the number of output devices.
The preceding analysis of the current mirror has assumed equal transistor sizes. The
output currents can be scaled by changing the relative areas of the output BJTs compared
to the diode-connected BJT. The ratio of output current to input current scales directly with
the ratio of emitter-base junction area of the output device to that of the input device.
The current sinks can be turned into current sources by using pnp transistors and a power
supply of opposite polarity. The output devices can also be scaled in area to make Io larger
or smaller than Iin . The schematic of Fig. 10.6 indicates a multiple output current mirror

+VCC Figure 10.6

Multiple output sources and
sinks.

Q1 Q2 Q3 Q4

Io2 Io3
R1 Iin
Io4 Io5

Q5 Q6 Q7 Q8

—VEE
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312 CHAPTER 10 INTEGRATED CIRCUIT DESIGN WITH THE BJT

+VCC

Iin
Q0
IC1 (N +1) IB1
␤+1 Io1 Io2 IoN

P R A C T I C E Problems Q1 QN+1
IB1 NIB1 Q2 Q3
10.1 In the current mirror of
Fig. 10.1, VCC = 10 V, β = Figure 10.7
120, V A = 60 V, and I E1 = Improved multiple output
I E2 = 10−12 e VBE /0.026 mA current mirror.
for the matched pair. Select
R to create an output current
of 0.9 mA at VC2 = 6 V. that includes both sources and sinks. Although parallel transistors are shown to indicate
Calculate VBE to three-place higher current output devices, single devices with larger areas would be implemented on
accuracy. Ans: R = 11.03 k ,
the chip.
VBE = 0.713 V.
10.2 Both transistors of a
simple current mirror have
values of β = 120,
10.1.2 A CURRENT MIRROR WITH REDUCED ERROR
VB E(on) = 0.68 V, and The difference between output current in a multiple output current mirror and the input
V A = 62 V. If the output current can become quite large if N is large. One simple method of avoiding this problem
current is to be within 5% of is to use an emitter follower to drive the bases of all devices in the mirror, as shown in
the input current, what is the Fig. 10.7. The emitter follower, Q0, has a current gain from base to collector of β + 1,
output voltage compliance? which reduces the difference between Io and Iin to
Ans: VC2 max = 4.92 V.
10.3 If the mirror of N +1
Practice Problem 10.2 is to Iin − Io = IB (10.14)
have a maximum output
β +1
voltage of 10 V, what must
the tolerance on output The output current for each device is
current be, compared to
input current? Ans: 13%. Iin
Io = N +1
(10.15)
1+ β(β+1)

10.1.3 THE WILSON CURRENT MIRROR

IO In the simple current mirrors discussed, it was assumed that the collector voltage of the
Iin output stage was small compared to the Early voltage. When this is untrue, the output
Q0 current will not remain constant, but will increase as output voltage (VCE ) increases. In other
IC1 words, the output compliance range is limited with these circuits. This limitation occurs
because the output impedance of Q2 in Fig. 10.4 is relatively low, falling in the tens of k
range.
Q1 Q2 An improved current mirror was proposed by Wilson and is illustrated in Fig. 10.8.
The Wilson current mirror is connected such that VCB2 = 0 and VBE1 = VBE2 . The
device Q1 has a collector-emitter voltage of VCE1 = VBE1 + VBE0 , and Q2 has a value of
VCE2 = VBE1 . Both Q1 and Q2 now operate with a near-zero collector-emitter bias, even
though the collector of Q0 might feed into a high voltage point. It can be shown that the
Figure 10.8 output impedance of the Wilson mirror is increased by a factor of approximately β/2 over
Wilson current mirror. the simple mirror. This higher impedance translates into a higher output compliance range.
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SECTION 10.2 HIGH-GAIN STAGES USING ACTIVE LOADS 313

This circuit also reduces the difference between input and output current as a result of the
emitter-follower stage.

P R A C T I C A L Considerations

The following chapter introduces the significant IC op amp. The op amp is a very
high gain amplifier that requires several amplifying stages. Each amplifying stage
requires a bias current. This chip then requires multiple bias current sources. In
practice, these sources can be implemented by a current mirror with multiple output
stages having properly scaled emitter areas. A single resistor along with multiple
mirror stages require far less chip real estate than would the use of separate bias
circuits for each amplifying element.

10.2 High-Gain Stages Using

Active Loads

I M P O R T A N T Concepts

1. An active load may consist of the collector-to-emitter circuit of a transistor biased

into its active region. This device replaces the passive resistor often used in the
collector of a gain stage.
2. The incremental output resistance, looking into the collector terminal of the
passive stage, can be large, leading to a high voltage gain. The dc voltage drop
across the active load is quite low.
3. The active load often takes the form of a current source.

In order to achieve high voltage gains and eliminate load resistors, active loads are used
in BJT IC amplifiers just as they are in MOSFET stages. In a conventional common-emitter
stage, the gain is limited by the size of the collector resistance. The midband voltage gain
of a common-emitter stage is given by

α RC
AMB = −
(re + R E )

It would be possible to increase this voltage gain by increasing RC ; however, making

RC large can lead to some serious problems. A large collector load requires a low quiescent
collector current to result in proper bias. This situation may lead to lower values of β, since
current gain in a silicon transistor typically falls at low levels of emitter current. In order
to achieve a voltage gain of 1000 V/V, a collector load of perhaps 100–200 k might be
required. The low collector current needed for proper bias, perhaps a few microamps, would
lead to a low value of β and a very high value of re . The desired high voltage gain may not
be achievable under these conditions.
A solution to this problem would result if the collector load presented a low resistance
to dc signals but presented a high incremental resistance. This combination of impedances
can result in a stable operating point along with a high gain. An ideal element to use for
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314 CHAPTER 10 INTEGRATED CIRCUIT DESIGN WITH THE BJT

+VCC the collector load of a transistor is another transistor. This device present a low dc and high
incremental impedance, and it is a simple element to implement on a chip.
RE 2

10.2.1 A CURRENT SOURCE LOAD

Q2 The circuit of Fig. 10.9 demonstrates one type of BJT active load. The transistor Q1 is the
amplifying element with Q2 acting as the load. Transistor Q1 looks into the collector of
IB2 vout Q2. The incremental output impedance at the collector of a transistor having an emitter
resistance in the low k range can easily exceed 500 k . With such a high impedance, this
transistor approximates a current source.
Q1 The dc collector currents of both transistors are equal in magnitude. This magnitude
Rg can be set to a value that leads to a reasonable value of β. Since Q2 has a very high output
vin impedance, the midband voltage gain will be determined primarily by the collector-to-
emitter resistance of Q1 and can be calculated from
V1

−β1rce1
AMB = (10.16)
Figure 10.9 Rg + rπ 1
A transistor stage with an active
load.
where rce1 is the output impedance of Q1. If the generator resistance, Rg is negligible, this
equation reduces to

rce1 (V A + VCQ1 )/IC V A + VCQ1

AMB = − =− ≈− (10.17)
re1 VT /I E VT

For an Early voltage of V A = 80 V and VT = 0.026 V, a small-signal voltage gain

exceeding −3000 V/V could result. In a normal application, this stage would drive a second
stage. The input impedance of the second stage will load the output impedance of the
first stage, further lowering the gain. Depending on the input impedance of the second
stage and the impedance of the active load stage, the gain magnitude may still exceed
1000 V/V.
The concept of an active load that presents a large incremental resistance while allowing
a large dc quiescent current is important in integrated circuit design. It can be extended to
FET amplifiers or hybrid bi-FET amplifiers with an FET amplifying stage and an active
BJT load.
In addition to the current source load just considered, the current mirror stage can also
be used to provide the active load of a differential stage. This topic is discussed in the next
subsection.

E X A M P L E 10.1
r
Assume that the active load in the circuit of Fig. 10.10 has an infinite output impedance,
VCQ1 = 4 V, and VEB2 = 0.7 V. The Early voltage of the amplifying device is 68 V and
β = 150. Calculate the midband voltage gain of this stage.

SOLUTION In order to apply Eq. (10.16), the output impedance and rπ for Q1 must be
found. The quiescent emitter current of Q2 is determined by the base-emitter circuit of Q2.
The emitter voltage of Q2 is 0.7 V higher than the base voltage or 8.7 V. The emitter current
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SECTION 10.2 HIGH-GAIN STAGES USING ACTIVE LOADS 315

Figure 10.10 +12 V
An active load amplifier.

2 kΩ

+8 V Q2

vout
600 Ω
Q1 RL
100 kΩ
vin

V1

is then
12 − 8.7
I E2 = = 1.65 mA
2
The emitter current of Q1 will be very near to that of Q2. Since IC1 ≈ I E1 , the output
impedance can be found from Eq. (7.13) to be
V A + VCQ1 68 + 4
rout1 = rce1 = = = 43.6 k
IC1 1.65
The value of rπ 1 is
26
rπ1 = (β + 1)re = 151 × = 2.38 k
1.65
The load impedance consists of rce1 in parallel with 100 k or Rout = 30.4 k . The voltage
gain is
−β Rout 150 × 30.4
AMB = =− = − 1530 V/V
Rg + rπ1 0.6 + 2.38
r
P R A C T I C E Problems
10.4 Assume that the active
P R A C T I C A L Considerations load in the circuit of
Fig. 10.10 is replaced by a
simple current mirror with
Another component that can be used to create a collector load with high incremental
an output current of
or ac impedance and low dc impedance is a transformer. This element generally has 1.65 mA. The output stage
only a few ohms of dc primary resistance while presenting an ac primary resistance of the current mirror has an
of n 2 RL , where n is the turns ratio from primary to secondary and RL is the resistive Early voltage of V A = 60 V.
load connected across the secondary terminals. Calculate the midband
For example, if n = 5 and RL = 8 , the ac primary resistance is 25 × 8 = 200 . voltage gain of the amplifier.
The dc resistance of the primary may be 3 ; thus, the ac resistance is much greater Approximate rce2 as V A /IC .
than the dc resistance. Ans: −833 V/V.
Although transformers are used in high-power amplifiers, they cannot be fabri- 10.5 Repeat Practice
cated by standard IC processes. Thus the active load developed by a biased tran- Problem 10.4 if the 100-k
load is removed from the
sistor remains the most popular load device for IC processes.
circuit. Ans: −999 V/V.
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316 CHAPTER 10 INTEGRATED CIRCUIT DESIGN WITH THE BJT

10.3 Amplifier Configurations In BJT

Integrated Circuits

I M P O R T A N T Concepts

1. A simple pnp current mirror (source) can act as the active load for an npn
common-emitter stage. The load resistance equals the parallel combination of
output resistances of the mirror stage and the gain stage.
2. An npn current mirror stage (sink) can also act as a load for an npn emitter
follower stage.
3. The cascode stage minimizes Miller effect capacitance at the input terminal,
thereby improving frequency response.

The current mirror serves as an active load for several important BJT IC amplifier stages
to be considered in the following paragraphs.

+10 V 10.3.1 THE CURRENT MIRROR LOAD

A rather simple configuration for an amplifying stage is shown in Fig. 10.11. In this stage,
the output impedance of the current mirror is not large enough to be negligible as it was in
Q3 Q2 the circuit of Fig. 10.9. Thus, the analysis will have to account for this element.
In Chapter 7, the high-frequency response of a discrete circuit was considered. Typically,
vout this value was determined by the input circuit, including the Miller effect capacitance. The
collector load resistance in a discrete stage is usually small enough that the output circuit
R1 10 kΩ Q1 does not affect the upper corner frequency. In the circuit of Fig. 10.11, as in most IC amplifier
vin
stages, the output impedance is very high compared to the discrete stage. For this circuit,
the output impedance of the amplifier consists of the output impedance of Q2 in parallel
V1 with that of Q1. This value will generally be several tens of k .
The equivalent circuit of the amplifier of Fig. 10.11 is indicated in Fig. 10.12. The value
of Rout is
Figure 10.11
A common-emitter stage with Rout = ro1  ro2 = rce1  rce2 (10.18)
current mirror active load.

The capacitance in parallel with Rout is approximately

Cout = Cµ1 + Cµ2 + Ccs1 + Ccs2 (10.19)

In this equation, Cµ1 and Cµ2 are the collector-to-base junction capacitances, and Ccs1
and Ccs2 are the collector-to-substrate capacitances of the respective transistors. If no gen-
erator resistance is present, Cµ1 will also appear in parallel with the output terminal and
ground. When Rg is present, we will still approximate the output capacitance with the same

rx1 c␮1
Figure 10.12 b b’ c
Equivalent circuit of the vout
amplifier in Fig. 10.11. v␲1
vin r␲1 C␲1 Rout Cout
gm1v␲1
e
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SECTION 10.3 AMPLIFIER CONFIGURATIONS IN BJT INTEGRATED CIRCUITS 317

equation, although feedback effects between the output and the bases of Q1 and Q2 actually
modify the value slightly.
The midband gain is easy to evaluate as

−β1 Rout
AMB = (10.20)
r x1 + rπ 1

The upper corner frequency is now more difficult to evaluate than that of the discrete
circuit, which often has a low value of collector load resistance. In the discrete circuit, the
input loop generally determines the overall upper corner frequency of the circuit. Although
the Miller effect will be much larger in the IC stage, lowering the upper corner frequency
of the input loop, the corner frequency of the output loop will also be smaller due to the
large value of Rout . Both frequencies may influence the overall upper corner frequency of
the amplifier.
The calculation of upper corner frequency begins by reflecting the bridging capacitance,
Cµ , to both the input and the output. The value reflected to the input side, across terminals
b and e, is

(1 − Ab c1 )Cµ1 (10.21)

as in the discrete circuit amplifier. Thus, the total input capacitance in parallel with rπ 1 is

Cin = Cπ 1 + (1 − Ab c1 )Cµ1 (10.22)

The upper corner frequency resulting from the input circuit of this stage is

1
f in−high = (10.23)
2πCin Req

where Req = r x1  rπ 1 .
The upper corner frequency resulting from the output side of the stage is

1
f out−high = (10.24)
2πCout Rout

The actual overall upper corner frequency, f 2o , must be found using the method of
Chapter 3 for a two-pole response. An example will demonstrate these points.

E X A M P L E 10.2
r
Assume that the circuit of Fig. 10.11 is biased so that the collector currents of Q1 and Q2
have a magnitude of 1.14 mA. The parameters for Q1 are β = 160, r x1 = 10 , rce1 =
68 k , Cπ 1 = 20 pF, and Cµ1 = 2.1 pF. For device Q2, the necessary parameters are
rce2 = 21 k and Cµ2 = 3.1 pF. Each device has a value of Ccs1 = Ccs2 = 2.5 pF. In this
circuit, the power supply is 10 V and R1 = 10 k .
Calculate the midband voltage gain and the upper corner frequency for this amplifier
stage. Do a Spice simulation using 2N3904 (npn) and 2N3905 (pnp) transistors.
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318 CHAPTER 10 INTEGRATED CIRCUIT DESIGN WITH THE BJT

10 V V3 4
Q3 Q2

R1 vout
10 kΩ
2
Q1

vin = 0.005 sin ␻t V2

1
Figure 10.13 0.668 V V1
Schematic for Windows Spice
simulation.

SOLUTION The midband voltage gain can be calculated from Eq. (10.20) after evaluating
rπ 1 and Rout . These resistances are
26
rπ1 = (β + 1)re1 = 161 × = 3672
1.14
and

Rout = rce1  rce2 = 68  21 = 16 k

The midband gain is then

β Rout 160 × 16,000
AMB = − =− = −695 V/V
r x1 + rπ1 10 + 3672
The upper corner frequency is found from a consideration of the two poles caused by
the input circuit and the output circuit. The corner frequency of the input circuit is
1 1
f in−high = =
Table 10.1 Spice 2πCin Req 2π (Cπ 1 + [1 − Ab c ]Cµ1 )(r x1  rπ 1 )
Netlist File for Example
1
10.2 = = 10.7 MHz
2π × 1481 × 10−12 × 10
EX10-2.CIR
Since rπ 1 r x1 , the value of 10 was used for Req . In addition, the midband gain was used
to approximate Ab c .
R1 0 4 10K
The corner frequency of the output circuit is
V1 1 0 0.668V
V2 2 1 AC 0.005V 1 1
f out−high = = = 975 kHz
V3 5 0 10V 2πCout Rout 2π × (2.1 + 3.1 + 2.5 + 2.5) × 10−12 × 16,000
Q1 3 20 0 Q2N3904
The input corner frequency is much higher than the output corner frequency; conse-
Q2 3 4 5 5 Q2N3905
quently, the latter value approximates the overall corner frequency. The result is a value of
Q3 4 4 5 5 Q2N3905
f 2o = 975 kHz.
.AC DEC 100 100 1G
The schematic for a Windows Spice simulation is shown in Fig. 10.13 with node and
.OP
element numbers added. The Spice netlist file used to simulate this circuit is shown in
.PROBE
Table 10.1.
.LIB BIPOLAR.LIB
Note that the connections for the BJT correspond to collector node, base node, emitter
.END
node, and substrate node. Normally, the substrate for a pnp device connects to the positive
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SECTION 10.3 AMPLIFIER CONFIGURATIONS IN BJT INTEGRATED CIRCUITS 319

power supply voltage. The substrate for the npn device connects to the most negative power
supply rail, which is often the ground terminal.
The results of the simulation are AMBsim = −685 V/V and f 2o−sim = 900 kHz. The
calculated and simulated values of midband voltage gain agree within 2%, and the upper
corner frequency values are within 10%.
r

Table 10.2 Summary of Results for the Common-Emitter Current-Source

Load Stage

CL , pF Rg, kΩ AMB cal , V/V AMB sim , V/V f2o−cal , kHz f2o−sim , kHz

0 0 −696 −685 975 900

10 0 −696 −685 480 493
0 10 −187 −186 40 39
10 10 −187 −186 39 38

In order to evaluate the effects of a signal generator resistance and a larger capacitive
load, a 10-k resistance was inserted in the base lead of Q1, which led to a simulated
midband gain of −186 V/V and an upper corner frequency of 39 kHz. If a 10-pF capacitor
is placed across the output and no generator resistance is used, the voltage gain returns
to the value of −685 V/V, but the upper corner frequency is lowered to 480 kHz. Adding
the generator resistance while the capacitor loads the output gives AMB = −186 V/V and
P R A C T I C E Problem
f 2o = 37.8 kHz. The comparison of calculated and simulated values for the different loading
conditions is given in Table 10.2. 10.6 Calculate the value of
The calculated results are designated A M Bcal and f 2o−cal , and the simulated values are Rg that lowers the upper
designated AMBsim and f 2o−sim . The task of calculating values for Table 10.2 is left to the corner frequency of the
student. Note that adding a 10-k generator resistance lowers the upper corner frequency by circuit in Example 10.2 to
a large factor, approximately 25, whereas adding 10 pF to the output lowers this frequency 100 kHz. Assume a 10-pF
load capacitance. Calculate
by a factor of about two.
the midband voltage gain.
Ans: Rg = 1.43 k ,
P R A C T I C A L Considerations AMB = −501 V/V.

For a BJT with a high value of current gain-bandwidth product, f t , the current source
load stage has a relatively low upper corner frequency. In Example 10.2, the value of
f t for these BJTs is 300–400 MHz. The resulting upper corner frequency is just 975
kHz. It should be recognized that this type of stage is used in op amp chips that will 5V
ultimately have a very low upper corner frequency. When used in an amplifier, the op
amp chip will use feedback to improve the overall upper corner frequency. Thus, the
low value of f 2o for an individual gain stage is not significant in these applications. Q1
4 kΩ R1
vin

1 vout
10.3.2 THE EMITTER FOLLOWER
V1
A stage that can be used to minimize the adverse effect on frequency response caused by a
generator resistance is the emitter follower. Although this stage has a voltage gain near unity,
it can be driven by a higher voltage gain stage while the emitter follower can drive a low Q3 Q2
impedance load. A typical stage is shown in Fig. 10.14. The output stage of the npn current
mirror, Q2, serves as a high impedance load for the emitter follower, Q1. An equivalent
circuit that represents the emitter follower of Fig. 10.14 is indicated in Fig. 10.15. For this Figure 10.14
circuit, gm1 = α1 /re ≈ 1/re . An emitter follower.
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320 CHAPTER 10 INTEGRATED CIRCUIT DESIGN WITH THE BJT

Rg rx c1
b1 b’1

vin C␮
r␲ v␲ C␲1 gm v␲

e1, c2
vout
rout2 Cout2
Figure 10.15
Equivalent circuit for the emitter
follower.

This circuit can be analyzed to result in a voltage gain of

 rπ1 +1 
Cπ 1
C(Rg + r x1 )
jω + gm1
rπ1 Cπ1
A= (10.25)
−ω2 + bjω + d

where

C = Cout2 Cµ1 + Cout2 Cπ 1 + Cπ 1 Cµ1 (10.26)

 
1 Cπ 1 + Cout2 Cπ 1 + Cµ1 (1 + gm1rce2 ) Cout2 + Cµ1
b= + + (10.27)
C Rg + r x1 rce2 rπ 1

and

Rg + r x1 + rπ 1 + rce2 (gm1rπ 1 + 1)
d= (10.28)
C(Rg + r x1 )rπ 1rce2

Note that the output capacitance of Q2 can be approximated as the sum of Cµ2 and Ccs2 .
The midband voltage gain is found from Eq. (10.25) by letting ω → 0. This value is

(1 + gm1rπ 1 )rce2
AMB = (10.29)
Rg + r x1 + rπ 1 + (1 + gm1rπ 1 )rce2

This gain is very near unity for typical element values.

The bandwidth is more difficult to calculate since the response has one zero and two
poles. The zero for the circuit of Fig. 10.15 is typically larger than the lowest frequency
pole. If these frequencies canceled, the larger pole would determine the corner frequency.
Since they do not cancel, the overall upper corner frequency is expected to be smaller than
the larger pole frequency. An accurate calculation can be made from Eq. (10.25) when the
parameters are known.

E X A M P L E 10.3
r
The emitter-follower circuit of Fig. 10.14 is biased so that IC1 = 1.08 mA. The value of β1
is 155, and the ohmic base resistance is 10 . The collector-base depletion capacitance for
both Q1 and Q2 is 2.5 pF as also is the collector-to-substrate capacitance. The value of f t
is approximately 300 MHz, and the Early voltage is 75 V for the transistors.
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SECTION 10.3 AMPLIFIER CONFIGURATIONS IN BJT INTEGRATED CIRCUITS 321

Calculate
1. The midband voltage gain of the circuit
2. The approximate upper corner frequency of the circuit
Simulate the operation of this stage using Spice to find the voltage gain and upper corner
frequency.

SOLUTION The value of re is found as

26 26
re = ≈ = 24
IE 1.09
Using this value, the diffusion capacitance or base-to-emitter capacitance can be found as
1 1
Cπ1 = = = 22 pF
2πre f t 2π × 24 × 3 × 108
The output resistance of Q2 is calculated from
VA 75
rce2 ≈ = = 68.8 k
IC 1.09
This equation neglects the voltage VCEQ2 . The value of rπ 1 is (β + 1)re = 3744 . All
element values in the equivalent circuit of Fig. 10.15 are now known.
Substituting element values into Eq. (10.25) results in
 ω

1.239 × 1010 1 + j 1.89×10 9
A=
−ω2 + jω1.581 × 1010 + 2.348 × 1019
The midband gain of this circuit is AMB = 0.9993 V/V. The zero frequency is 301 MHz.
The two pole frequencies are 264 MHz and 2.28 GHz. The gain expression can also be
written
 
f
0.9993 j 301 MH z
+1
A=    
f
j 264 MH z
+1 j 2.28 fGH z + 1

Using iterative methods, the upper corner frequency is found to be 1.67 GHz. Although the
Table 10.3
voltage gain is only unity, the upper corner frequency is much higher than the common-
Spice Netlist File for
emitter amplifier with a current mirror load.
Example 10.3
The schematic for simulation is shown in Fig. 10.16 with node and element numbers
added. The Spice netlist file is shown in Table 10.3. EX10-3.CIR
Figure 10.16
5 R1 5 4 4K
Schematic for simulation of
the emitter follower. V1 1 0 3.2 V
V3 2 V2 2 1 AC 1V
5V Q1
sin ␻t V3 5 0 5V
vin V2 Q1 5 2 3 0 Q2N3904
4 kΩ R1 3 Q2 3 4 0 0 Q2N3904
1
vout Q3 4 4 0 0 Q2N3904
3.2 V
4 .AC DEC 100 100 10G
V1
.OP
Q3 Q2 .PROBE
.LIB BIPOLAR.LIB
.END
P1: FCH/SPH P2: FCH/SPH QC: FCH/UKS T1: FCH
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322 CHAPTER 10 INTEGRATED CIRCUIT DESIGN WITH THE BJT

The results of the simulation are A MBsim = 0.9993 V/V and f 2o−sim = 2.56 GHz.
Whereas the midband voltage gain compares well to the calculated value, the simulated
upper corner frequency is somewhat higher than the calculated value.
r
Table 10.4 Summary of Results for the Emitter-Follower Stage

CL , pF Rg, kΩ AM B cal , V/V AM B sim , V/V f2o−cal , MHz f2o−sim , MHz

0 0 0.9993 0.9993 1670 2560

10 0 0.9996 0.9993 420 420
0 10 0.9982 0.9975 6.56 6.61
10 10 0.9987 0.9975 6.85 6.87

It is again useful to consider the effects of adding a large generator resistance or a load
capacitance to the emitter-follower stage. Table 10.4 summarizes the results of simulations
for different combinations of source resistance and load capacitance.
Note that the insertion of a 10-k generator resistance lowers the upper corner frequency
P R A C T I C E Problem more than the addition of the 10-pF load capacitance. Note also that the addition of the 10-pF
capacitance to the circuit that includes a 10-k generator resistor leads to a higher upper
10.7 An emitter follower
has a midband voltage gain corner frequency rather than a lower value. This result is from a shift in the lower pole
of 0.99. The voltage gain frequency to a value that exceeds that of the zero frequency when the load capacitance is
has a zero at 500 MHz, one added. The added value of C L when no generator resistance is present does not have the
pole at 200 MHz, and same effect.
another pole at 1.6 MHz. Surprisingly, it is possible for the two poles to become complex, depending on element
Find the upper corner values. When this occurs, the frequency response can exhibit a peak and the step response
frequency of the voltage can exhibit ringing.
gain. Ans: 236 MHz.
P R A C T I C A L Considerations

The emitter follower, like the source follower, is often used as a buffer to interface
between a high voltage gain stage and a low impedance load. The emitter follower
+VCC
loads the preceding stage only slightly, but provides a high current to the load with
an accompanying high upper corner frequency.
I
10.3.3 THE CASCODE AMPLIFIER STAGE
vout One of the problems with the common-emitter stage using an active load is the Miller effect.
Q2 This stage has a high voltage gain from base to collector. The circuit of Fig. 10.11 with
the values of Example 10.2 has an inverting voltage gain, AMB , that approaches −700 V/V.
VB2 The base-collector junction capacitance is multiplied by (1 + |AMB |) and reflected to the
input loop. This capacitance adds to the diffusion capacitance from point b to point e and
decreases the upper corner frequency to a relatively small value.
Q1
The cascode amplifier stage of Fig. 10.17 minimizes the capacitance reflected to the
vin input. In this circuit, the input capacitance is primarily composed of the diffusion capacitance
of Q1. The gain from base to collector of Q1 is quite low since the collector load of
this device consists of the impedance looking into the emitter of Q2. This impedance is
VB1
approximately equal to the base-emitter diode resistance of Q2, which is

26
Figure 10.17 re2 =
A cascode stage. I E2
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SECTION 10.3 AMPLIFIER CONFIGURATIONS IN BJT INTEGRATED CIRCUITS 323

R v␲1 C␮1 0
b’1 c1 e2 v␲2

vin r␲1 C␲1 re2 C␲2

gm1v␲1
e1 b2

c2
vout

gm2v␲2 rout2 Cout2 rcs Cout cs

Figure 10.18
Equivalent circuit of the cascode
stage.

The upper device passes the incremental signal current of Q1 to its collector and develops
a large voltage across the current source impedance. There is no Miller multiplication of
capacitance from the input of Q2 (emitter) to the output (collector), since the gain is
noninverting and negligible capacitance exists between emitter and collector. Thus, the
cascode stage essentially eliminates Miller effect capacitance and its resulting effect on
upper corner frequency.
A high-frequency equivalent circuit of this stage is shown in Fig. 10.18. The resistance
R includes any generator resistance and the base resistance, r x1 of Q1. The resistance rcs is
the output resistance of the current source. The output capacitance is the sum of Cµ2 , Ccs2 ,
and any capacitance at the current source output. The resistance rout2 can be quite large,
since Q2 sees a large emitter resistance looking into the collector of Q1. This emitter load
leads to negative feedback that increases the output resistance of Q2.
The midband voltage gain is calculated from the equivalent circuit of Fig. 10.18 after
eliminating the capacitors. This gain is found rather easily by noting that the input current
to Q1 is

vin
i b1 = (10.30)
R + rπ 1

This current will be multiplied by β1 to become collector current in Q1. This current also
equals the emitter current of Q2. The emitter current of Q2 is multiplied by α2 to become
collector current of Q2. The output voltage is then

vout = i c2 × R3 (10.31)

where R3 = rout2  rcs . This resistance could be very large if the current source resistance,
rcs , is large. The value of rout2 will be high since the emitter of Q2 sees a resistance of rce1 .
Combining this information results in a midband voltage gain of

−β1 α2 R3
AMB = (10.32)
R + rπ 1

If no generator resistance is present and if R3 = 100 k , this midband voltage gain might
exceed 5000 V/V.
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324 CHAPTER 10 INTEGRATED CIRCUIT DESIGN WITH THE BJT

The gain as a function of frequency can be found as

1 1 1
A = AMB (10.33)
1 + jωCπ 1 (rπ 1  R) 1 + jωre2 Cπ 2 1 + jω R3 Cout

Typically, the corner frequency of the second frequency term in Eq. (10.33), that is,

1
f2 =
2πre2 Cπ2

is much higher than that of the first term,

1
f in−high =
2π(rπ1  R)Cπ 1

especially if R is large compared to rπ 1 . In this case, since re1 ≈ re2 as a result of equal
emitter currents, then re2 (β + 1)re1 . For hand analysis of the cascode circuit, the second
term in the expression for gain is often neglected.
The gain can then be written as

1 1
A = AMB (10.34)
1+ j f
f in−high
1+ j f
f out−high

where

1
f out−high = (10.35)
2πCout R3

and f in−high was defined previously.

The capacitance Cout is the sum of the current source output capacitance and the output
capacitance of Q2, giving

Cout = Cout2 + Coutcs

If a current mirror with output stage Q3 generates the collector bias current for Q1 and
Q2, the output capacitance is

Cout = Cµ2 + Cµ3 + Ccs2 + Ccs3

E X A M P L E 10.4
r
The cascode circuit of Fig. 10.19 is driven by a current mirror with an output current of
0.38 mA. Devices Q1 and Q2 have values of β = 140 and r x = 10 . The capacitor values
are Cπ 1 = Cπ 2 = 10.8 pF, Cµ1 = Cµ2 = Ccs2 = 2.5 pF, and Cµ3 = Ccs3 = 5 pF. The output
impedance of the current mirror is 52.2 k .
Calculate the midband voltage gain and the upper corner frequency of the circuit. Do a
Spice simulation and compare the measured to the simulated results.
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SECTION 10.3 AMPLIFIER CONFIGURATIONS IN BJT INTEGRATED CIRCUITS 325

7
V4 8 V Q4 Q3
6
3
vout
R1 20 kΩ
5
Q2

V3 3V
4

2
Q1
vin = 0.001 sin ␻t
V2
1

Figure 10.19 V1 0.66 V

Schematic for simulation of
cascode amplifier.

SOLUTION The value of rπ for Q1 and Q2 is calculated to be

26
rπ = (β + 1)re = 141 × = 9647
0.38

Assuming that rout2 is very large, the value of R3 is approximated by rcs = 52.2 k .
From Eq. (10.32), the midband voltage gain is

−β1 α2 R3 −β1 rcs −141 × 52.2

AMB = ≈ = = −763 V/V
rπ1 rπ1 9.647

Table 10.5 Spice Netlist

File for Example 10.4.

EX10-3.CIR

R1 6 0 20K
V1 1 0 0.66V
V2 2 1 AC 0.001V
V3 5 0 3V
V4 7 0 8V
Q1 4 2 0 0 Q2N3904
Q2 3 5 4 0 Q2N3904
Q3 3 6 7 7 Q2N3905
Q4 6 6 7 7 Q2N3905
.AC DEC 100 100 100Meg
.OP
.PROBE
.LIB BIPOLAR.LIB
.END
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326 CHAPTER 10 INTEGRATED CIRCUIT DESIGN WITH THE BJT

The corner frequency of the input stage is

1 1
f in−high = = = 1.47 GHz
2π(rπ1  R)Cπ1 2π × 10 × 10.8 × 10−12

The upper corner frequency due to the output circuit is

1 1
f out−high = = = 203 kHz
2π R3 Cout 2π × 52,200 × 15 × 10−12

In this equation, the output capacitance was taken as

Cout = Cµ2 + Cµ3 + Ccs2 + Ccs3 = 2.5 + 5 + 2.5 + 5 = 15 pF

The overall upper corner frequency is f 2o = 203 kHz.

The Spice netlist file for this circuit is shown in Table 10.5 using the node and element
numbers of Fig. 10.19.
The results of the simulation are AMBsim = −758 V/V and f 2o−sim = 205 kHz.
r

Table 10.6 Summary of Results for the Cascode Stage

CL , pF Rg, kΩ AMB cal , V/V AMB sim , V/V f2o−cal , kHz f2o−sim , kHz

0 0 −763 −758 203 205

10 0 −763 −758 121 123
0 10 −372 −368 201 202
10 10 −372 −368 121 123

P R A C T I C E Problem Additional calculations and simulations were done using a 10-pF load capacitor and/or
a 10-k generator resistance. These results are summarized in Table 10.6.
10.8 If a very large We observe that the insertion of a 10-k generator resistance has little effect on the
generator resistance is upper corner frequency. This is to be expected as a result of the minimization of the Miller
inserted in the circuit of
effect. The input capacitance is small enough that it has little effect on the overall upper
Example 10.4, what is the
corner frequency even with the larger generator resistance in the input loop. In the active
lower limit on f in−high ?
Ans: 1.53 MHz. load stage of Fig. 10.13 considered earlier, insertion of a 10-k generator resistance lowered
the upper corner frequency by a factor of about 25.

DISCUSSION OF THE DEMONSTRATION PROBLEM

The amplifier circuit for the demonstration problem is repeated here. In order to determine
the voltage gain of the common-emitter stage, the values of rπ and rout must be determined.
These depend on the output current of the current stage. Using Eq. (10.9), this current can be
approximated as

β 80 8 − 0.7
Io = Iin = × = 0.59 mA
β +2 82 12
This current is the collector current of Q1 and approximates the emitter current of this device.
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SECTION 10.3 AMPLIFIER CONFIGURATIONS IN BJT INTEGRATED CIRCUITS 327

8V BJT amplifier for Demonstration
Problem.

Q4 Q3

Q2
Rg
12 kΩ Q1 vout
1 kΩ
vin 10 kΩ

V1

The resistance re1 is then

26
re1 = = 44.1
0.59
which leads to

rπ1 = (β + 1)re1 = 81 × 44.1 = 3569

The output impedances of Q1 and Q3 are next calculated to be

VA 62
rce1 = rce3 = = = 105 k
IC 0.59
The voltage gain of Q1 can now be calculated after noting that the load for this stage is made
up of the parallel combination of rce1 , rce3 , and the input impedance of the emitter follower. The
emitter-follower input resistance is approximately Rin2 = (β + 1)R E2 = 810 k , neglecting re2 .
The voltage gain of this stage is

β(rce1  rce3  Rin2 ) 80 × 49.3

A MB1 = − =− = −863 V/V
Rg + rπ1 1 + 3.57

The voltage gain of the emitter follower is

R E2
A MB2 =
R E2 + re2
Since the voltage across R E2 is 4 V, the current through the emitter of Q2 is 0.4 mA, which
results in re2 = 65 and A MB2 = 0.994. The overall midband gain is the product of A MB1 and
A MB2 . This product is

AMB = −863 × 0.994 = −858 V/V

Because the upper corner frequency of the emitter follower is much greater than that of the
common-source stage, the overall upper corner frequency will be equal to that of the common-
source stage. This stage will have an upper corner frequency due to the input loop and another
due to the output loop.
The output capacitance is calculated by Eq. (10.19) to be

Cout = Cµ1 + Cµ3 + Ccs1 + Ccs3 = 8 pF

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328 CHAPTER 10 INTEGRATED CIRCUIT DESIGN WITH THE BJT

The output resistance has previously been found as 49.3 k , giving an upper corner frequency
of
1
f out−high = = 404 kHz
2πCout Rout

The input capacitance is calculated from Eq. (10.22). This value is

Cin1 = Cπ1 + (1 + |Ab c |)Cµ1 = 20 + 1106 × 2 = 2232 pF

This capacitance sees an equivalent resistance of Req = Rg  rπ1 = 1  3.57 = 781 .

The input loop corner frequency is

1
f in−high = = 91.3 kHz
2πCin Req

The two upper corner frequencies cause an overall upper corner frequency of 87 kHz.

SUMMARY
➤ Current mirrors are used to provide bias current for ➤ The emitter follower with an active load provides a
some IC amplifier stages and can also be used as active voltage gain of approximately unity and a very high
loads. upper 3-dB frequency. This stage can drive a large
capacitive load.
➤ Many IC amplifier stages use active loads to achieve
high voltage gains. The high incremental resistance of ➤ The cascode stage minimizes the Miller effect
an active load stage results in a high voltage gain but capacitance at the input and provides a high voltage
may limit the upper 3-dB frequency of the circuit. gain.

PROBLEMS
SECTION 10.1.1 THE SIMPLE CURRENT MIRROR
D 10.1 For the simple current mirror of Fig. 10.1, assume 10.3 If Io can vary by ±5% in the mirror of Prob-
that β1 = β2 = 100, VBE1 = VBE2 = 0.6 V, VCC = 5 V, lem 10.2, determine the voltage compliance of the output
and V A = ∞. Select R to result in Io = 1.00 mA. circuit.
D 10.2 If V A = 50 V in Problem 10.1, select R to result 10.4 What is the percentage variation in output current in
in Io = 1.00 mA when VC2 = 4 V. the mirror of Problem 10.2 as VC2 varies from 2 V to
6 V? What is the incremental output resistance of the
mirror?

SECTION 10.1.2 A CURRENT MIRROR WITH REDUCED ERROR

10.5 Calculate the ratio Io /Iin for the multiple current 10.7 If Q1 has an emitter area that is four times the size
source circuit of Fig. 10.5, assuming N = 4, β = 120, of the four current sinks it drives in Fig. 10.5, what is the
and equal sizes for all transistors. ratio of output current of one sink to input current for
10.6 If Q1 has an emitter area that is 1/4 the size of the β = 120?
four current sinks it drives in Fig. 10.5, what is the ratio of
output current of one sink to input current for β = 120?
P1: FCH/SPH P2: FCH/SPH QC: FCH/UKS T1: FCH
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PROBLEMS 329
SECTION 10.1.3 THE WILSON CURRENT MIRROR
10.8 A simple current mirror sinks 1.00 mA with an output 10.9 In the Wilson current mirror of Fig. 10.8, derive an
voltage of 4 V. The current increases by 10% at an output expression for incremental resistance seen looking into
voltage of 9 V, resulting in a voltage compliance of 5 V. the collector/base of Q2.
This current mirror is now replaced by a Wilson current
10.10 In the Wilson current mirror of Fig. 10.8, derive
mirror designed to sink 1.00 mA with an output voltage
an expression for output impedance of the circuit in terms
of 4 V. The Wilson circuit has a voltage compliance of
of β, re0 , re2 , rce0 , and any other necessary parameters.
64 V. Calculate the output impedance of both circuits.

SECTION 10.2.1 A CURRENT SOURCE LOAD

10.11 In the circuit shown, β1 = 210, β2 = 90, VBE1 = 10.14 For both transistors of the circuit, assume that β =
−VBE2 = 0.68 V, and rout1 = 35 k . The quiescent out- 100 and rce = 60 k .
put voltage is 5 V. Calculate the midband voltage gain of
the circuit. (a) If both emitter currents in (a) of the figure are
0.8 mA, calculate the midband voltage gain of the
Figure P10.11 amplifier.
+12 V (b) After adding a 100- resistor to the emitter of Q2,
the following data were taken for the circuit in (b) of
the figure:
1 kΩ

VC2 , V 3 4 5 6 7
+10 V Q2
IC2 , mA 0.792 0.796 0.800 0.804 0.808
vout
vin
If VCQ1 = 5 V in the circuit of (c), calculate the
Q1
midband voltage gain.
VB
Figure P10.14
+10 V
+10 V
10.12 Repeat Problem 10.11 if a 10-k resistor is inserted
in the base lead of Q1. 100 Ω
+10 V
Q2
10.13 In the circuit of Problem 10.11, V A2 = 56 V. Calcu-
late the output resistance, rout2 , looking into the collec- I Q2
100 Ω
tor of Q2. Compare this to the output resistance of Q1, vout
rout1 = 35 k . Is it reasonable to assume that rout2 = ∞ I
vout
in calculating the voltage gain? Q1 Q2

vin I IC 2 Q1

vin
V1 VC2

V1

(a) (b) (c)

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330 CHAPTER 10 INTEGRATED CIRCUIT DESIGN WITH THE BJT

10.15 Derive an expression for the incremental output D 10.16 Select the emitter resistance of Q1 in Fig.
impedance for circuit (b) in Problem 10.14. 10.10 to lead to a midband gain of −1200 V/V. Assume
that β and VEB2 remain at the values given in Example
10.1 and V1 can be changed to any appropriate value to
maintain VCQ1 = 4 V.

SECTION 10.3.1 THE CURRENT MIRROR LOAD

10.17 For the circuit shown, β1 = 200, β2 = 100, |V A1 | = 60 V, |V A2 | = 40 V, and VBE1 =
−VBE2 = −VBE3 = 0.7 V. Assume that the quiescent output voltage is 5 V. Calculate
the midband voltage gain of the circuit.

Figure P10.17
+10 V

Q3 Q2

vin vout
10 kΩ
8 kΩ R Q1

VB

10.18 If R of the current mirror in Problem 10.17 is changed to 20 k and VB is adjusted

to keep VCQ1 = 5 V, calculate the midband voltage gain of the circuit.
10.19 If the simple current mirror of Problem 10.17 is replaced by a Wilson current mirror
with an output impedance of 420 k , calculate the midband voltage gain of the stage.
Assume that the output current of the mirror remains equal to the value in Problem 10.17.
10.20 In the circuit of Problem 10.17 at the bias point used, the diffusion capacitance of
Q1 is Cπ = 20 pF, Cµ1 = 2 pF, Cµ2 = 4 pF, Ccs1 = 3 pF, and Ccs2 = 3.5 pF. Calculate
the upper corner frequency of the circuit.
10.21 Repeat Problem 10.20 if the source resistance is changed to 1 k . Assume that
r x = 50 .
D 10.22 In Problem 10.20, how large can a load capacitance be to result in a 10%
reduction in bandwidth compared to the case of no load capacitance?

SECTION 10.3.2 THE EMITTER FOLLOWER

10.23 The three transistors of Fig. 10.16 are identical with VBE = 0.68 V, β = 180, r x =
100 , rπ = 2.4 k , and rout = 40 k . If a 100-k generator resistance is inserted in
series with V 2, keeping the bias current constant, what is the midband voltage gain?
10.24 In Problem 10.23, the capacitors Cµ = 3 pF, Cπ 1 = 30 pF, and Cout2 = 5 pF. Cal-
culate the upper corner frequency of the voltage gain.
P1: FCH/SPH P2: FCH/SPH QC: FCH/UKS T1: FCH
PB139B-10 ZP042-Sam.cls March 12, 2002 22:35

PROBLEMS 331
S E C T I O N 1 0 . 3 . 3 T H E C A S C O D E A M P L I F I E R S TA G E
10.25 In Fig. 10.19, the resistor R1 is changed from 20 k
to 10 k . Calculate the new midband voltage gain. As-
sume that the output resistance of the current source, rcs ,
changes from 52.2 k to 70 k .